JPS6152493B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ripple-carry type arithmetic logic circuit, in which when performing logical operations such as OR, logical product, and exclusive OR, the ripple carry generated during addition is used to The purpose is to simplify the circuit.

FIG. 1 shows a general configuration block diagram of a series-parallel arithmetic circuit as an example. Each unit cell 1 has inputs and outputs including calculation inputs A and B, a calculation output, a carry input Ci, a carry output C, and a calculation control input for specifying a calculation mode. This unit cell 1 generally performs operations such as binary addition (ADD), logical product (AND), logical sum (R), and exclusive logical sum (EXR).

FIG. 2 shows a conventional example of a unit cell 1 that performs ADD and AND. FIG. 2A is a configuration diagram and FIG. 2B is a truth table showing the operation. When using the AND function, the unit cell's carry input may be 0 or 1. However, all calculation inputs and outputs are positive logic.

When the calculation control input CAND is “0”, the calculation output is 0.
, the addition result 11 is output, and when CAND is "1", the calculation output is 0, and the AND result 12 is output. Furthermore, if the carry output is 0, the AND result 12 is output. Further, as a carry output C, "1" is output when a carry occurs as a result of addition of calculation inputs A and B and carry input Ci.

The present invention makes it possible to greatly simplify the circuit configuration compared to the conventional one by utilizing ripple carry even during logical operations.One embodiment of the present invention will be described below with reference to the drawings.

FIG. 3a shows an example of the configuration of a unit cell that performs ADD and AND operations, and FIG. 3b shows a truth table of this unit cell. The operation of this unit cell is as follows: (1) During ADD calculation Set the calculation control input CAND to “0”. As a result, the calculation output is the calculation input A, B and the carry input.
The addition result of Ci is output, and the carry output C is
It is clear that the added carries of A, B, and Ci are output.

(2) AND operation Set the operation control input CAND to “1”. and the first
Input "1" to the lowest calculation unit cell in the figure. Therefore, in Fig. 3, the calculation output is the AND of calculation inputs A and B, and the carry output C
“1” is output.

The above conditions are shown in the truth table of FIG. 3b.
That is, in the example circuit for realizing ADD and AND shown in FIG. 3a, the NR gate input of the half adder is
It is sufficient to use the input gate 21 and connect the arithmetic control input.

Next, a fourth example of the configuration of an arithmetic unit cell according to the present invention that executes ADD, AND, R, and EXR will be described.
Figure a shows the truth table of this unit cell, and figure b shows the truth table of this unit cell.

In the unit cell shown in Fig. 4, the calculation control is as follows:
This is done using three control inputs: CAND, and CEXR.

(1) During ADD and AND operations, the operation control input and CEXR are
Set to “1” and “0”. At this time, the circuit becomes exactly the same as the circuit shown in FIG. 3 above, and it is clear that ADD and AND can be executed by the CAND control input.

(2) At R time Set all calculation control inputs CAND, , CEXR to "0" and set the carry input Ci to "0".

It is clear that the calculation output becomes R of the calculation inputs A and B, and the carry output C also becomes "0", making the carry input Ci of the next stage unit cell "0".

(3) At EXR If the calculation control inputs CAND, , and CEXR are set to “0”, “1”, and “1”, and the carry input Ci is set to “0”, the calculation output includes calculation inputs A,
The exclusive OR (EXR) of B is output, and the carry output C becomes "0", setting the carry input Ci of the next stage unit cell to "0".

With the above explanation, ADD,
It can be seen that AND, R, and EXR operations are executable.

In the above embodiment, in order to simplify the explanation, all calculation inputs and outputs are assumed to be positive logic, but the present invention is not limited to the logic states of the inputs and outputs. For example, the arithmetic circuit that calculates ADD, AND, R, and EXR when the arithmetic input is negative logic and the arithmetic output is positive logic is as shown in Figure 5a, and its truth table is:
The result will be as shown in Figure 5b.

As described above, the present invention utilizes the carry input to the full adder in the logic operation circuit to simplify the circuit, and is configured so that the carry input and the carry output have the same value for the logic operation. Therefore, in a counter configured by connecting multiple stages of full adders according to the present invention, when each full adder performs a logical operation, the carry inputs of all full adders automatically become the same value. By simply adding a control signal for performing logical operations, a circuit for switching between logical operations and the functions of the adder can be eliminated. Therefore, in a ripple-carry type arithmetic circuit, it is possible to greatly simplify the arithmetic circuit by skillfully using the carry input even when executing logical operations, and it is especially useful for arithmetic circuits such as microprocessors. This has many advantages, such as improving reliability and reducing the chip area of the arithmetic circuit portion.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a ripple-carry type serial/parallel arithmetic circuit, Fig. 2 is a block diagram and operational state diagram showing a conventional example of an arithmetic unit cell that performs addition and logical product, and Fig. 3 shows an addition system according to the present invention. A configuration diagram and an operation state diagram showing an embodiment of an arithmetic unit cell that performs AND operations. FIG. Configuration diagram and operating state diagram,
FIG. 5 is a block diagram and an operation state diagram of another embodiment of the present invention.

Claims (1)

[Claims] 1 AB+ (or
A full adder is constructed by cascading two stages of half adders having a logic function of AB+), and the half adder in the previous stage has an input terminal for a control signal that instructs a logic operation, and the control signal controls the logic function. The rear half adder is configured to have a terminal for a carry input, and is configured to non-invert (or invert) the output of the front half adder by the carry input; . An arithmetic logic circuit comprising a carry means for outputting a carry output having the same value as the carry input when the control signal is input to the half adder at the previous stage.