JPH04294420A - Divider - Google Patents

Abstract

PURPOSE:To offer a divider capable of shortening a dividing arithmetic time. CONSTITUTION:The divider constituted of connecting plural adders 12h, etc., each of which executes the adding arithmetic of data Y constituting a divisor, data X including the bit data of data constituting a dividend in each digit and carry data in parallel by the number of digits constituting each divisor and each dividend is characteristically provided with detection parts 14h, etc., for detecting that the added result data of the adding operation by the adders 12h, etc., are '0', the 1st selection parts 17g, etc., for selecting and sending either one of carry data and '0' data sent by the adders 12h, etc., based upon a control signal sent from the detection parts 14h, etc., and the 2nd selection parts 18 for selecting and sending either one of residual data and the '0' data sent by the adders 12h, etc., based upon the control signal sent by the detection parts 14h, etc.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a divider.

0002

2. Description of the Related Art When both the dividend A and the divisor B are composed of, for example, 4 bits, a conventional divider is constructed as follows. As shown in Figure 4, divisor B and dividend A
The bit data constituting the 4-bit adder 10 is supplied bit by bit to the 4-bit adder 10 for calculation, so that the 4-bit adder 10 is connected in four stages. Further, a processing circuit is configured of an inverter, an AND gate, and an OR gate, and is supplied with the division result, carry data, and bit data of the dividend A in the bit data processed in each 4-bit adder 10, and processes these supplied data. The output sides of 11 are connected to the next-stage 4-bit adder 10 and the next-stage processing circuit 11, respectively. Also, dividend A and divisor B consisting of 8 bits
FIG. 5 shows the configuration of a divider that divides . Note that 12 is an 8-bit adder, and 13 is a processing circuit corresponding to the processing circuit 11 described above.

0003

However, the conventional divider has the following problems (A) to (C). (b) Even if the data is divisible in the middle of the division operation, the division operation is executed up to the last bit data, so the operation takes a long time. (b) Even when the dividend A is smaller than the divisor B, the division operation is executed up to the last bit data, so the operation takes a long time. (c) Even when the divisor B is 1, the division operation is executed up to the last bit data, so the operation takes a long time.

The present invention has been made to solve these problems, and an object of the present invention is to provide a divider that can reduce the time required for division operations.

[Means for Solving the Problems] The present invention provides an adder that performs an addition operation between data Y constituting a divisor, data X containing bit data of data constituting a dividend for each digit, and carry data. In a divider configured to be connected in parallel in multiple stages corresponding to the number of bits constituting the dividend, the divider includes a detection unit that detects that the addition result data of the addition operation in the adder is 0, and a carry that the adder sends out. a first selection section that selects and sends out data or 0 data based on a control signal sent out by the detection section; It is characterized by comprising a second selection section that selects and sends out the selection based on the control signal to be sent out.

[0005]

[Operation] The detection unit is connected to each stage of the adder other than the adder that processes the least significant bit data of the dividend, and determines whether the addition result data of the adder at each stage is 0 or not. The judgment result is used as a control signal for the first and second
Send to the selection section. Therefore, when the detection unit connected to the adder that processes the bit data of a certain digit of the dividend determines that the addition result data is 0, the detection unit sends a control signal indicating that it is 0 to the first and It is sent to the second selection section. The first and second selection sections select and send out data of 0 based on the selection signal. In this way, the detection unit, the first and second
If the addition result in the adder becomes 0 during the division operation, the selection section does not perform addition operation on each subsequent digit of the dividend, and the 0 data is sent from the first and second selection sections. It acts to be selected and sent.

[0006]

First Embodiment In FIG. 1 showing an embodiment of the structure of a divider according to the present invention, the same components as in FIG. 5 are designated by the same reference numerals. Similar to the adders constituting a conventional divider, all of the 8-bit adders 12h to 12a connected in eight stages are each supplied with 8-bit data constituting the divisor B.
Further, each bit data constituting the 8-bit dividend A is sequentially added to the 8-bit adders 12h and 1 from the most significant bit data side.
2g..., while each 8-bit adder 1
The output side of 2 is connected to the processing circuit 13 described above.

Furthermore, the divider of this embodiment has additional components described below. The most significant bit data of the dividend A is supplied and the most significant bit data Q of the division result data
This is the result of addition of 8-bit data Y corresponding to divisor B, 8-bit data X including the most significant bit data of dividend A data, and carry data in the 8-bit adder 12h that sends Z0 or Z
Eight output terminals Zh that send out data consisting of 8 bits of 7 in parallel are connected to the input sides of an inverter 16 and NAND gates 15f and 15a via an OR gate 14h. Similarly, in the 8-bit adder 12g which is supplied with the second most significant bit of the dividend A and sends out the second most significant bit of data Q6 of the division result data, the output terminal Zg which sends out the addition result is , NAND gates 15f to 15a via OR gate 14g
connected to the input side of the Similarly, in the 8-bit adder 12f, which is supplied with data from the third most significant bit of the dividend A and sends out data Q5 from the third most significant bit of the division result data, an output terminal Z is used to send out the addition result.
f is connected to the NAND gate 15e via the OR gate 14f.
to the input side of 15a. Thereafter, the configuration is the same up to the 8-bit adder 12b.

The least significant bit data of the dividend A is supplied and the least significant bit data Q0 of the division result data is sent out 8
In the bit adder 12a, an output terminal Za for sending out the addition result is connected to a multiplexer 18 via a processing circuit 13. The multiplexer 18 is a circuit that selects the output signal of the NAND gate 15a as a control signal between the 8-bit data supplied from the processing circuit 13 and the 0 data in which all 8 bits are 0. 1 from the NAND gate 15a.
When data of 0 is supplied from the NAND gate 15a, the data of 0 is selected, and when data of 0 is supplied from the NAND gate 15a, the output data of the processing circuit 13 is selected. Note that the output data of the multiplexer 18 becomes the remainder data in the division operation.

The output side of the inverter 16 is connected to a multiplexer 17g to which carry data of an 8-bit adder 12g and 1-bit 0 data are supplied. The multiplexer 17g is a circuit that selects either carry data or 0 data supplied from the 8-bit adder 12g using the output signal of the inverter 16 as a control signal, and if the output data of the inverter 16 is 1, If the data of 0 is selected and the output data of the inverter 16 is 0, the carry data is selected. Note that the output data of the multiplexer 17g is bit data Q6 of the second most significant bit of the 8-bit quotient.

Similarly, the output side of the NAND gate 15f is connected to a multiplexer 17f to which carry data of the 8-bit adder 12f and 1-bit 0 data are supplied. The multiplexer 17f is also the multiplexer 17
Similarly to g, this circuit selects either carry data or 0 data supplied from the 8-bit adder 12f using the output signal of the NAND gate 15f as a control signal, and the output data of the NAND gate 15f is 1. If so, the 0 data is selected, and if the output data of the NAND gate 15f is 0, the carry data is selected. still,
The output data of the multiplexer 17f is bit data Q5 of the third most significant bit of the 8-bit quotient.

Similarly, each multiplexer 17e to 17a is supplied with carry data and 0 data sent out by each 8-bit adder 12e to 12a, and N
Either data is selected by the output data of AND gates 15e to 15a. In addition, multiplexer 17
The output data of a becomes the least significant bit data Q0 of the quotient. Also, the most significant bit data Q7 of the quotient is sent to the 8-bit adder 1.
This is 2h carry data.

The operation of the present divider configured in this manner will be explained below. If the most significant bit data of the dividend A is supplied and the most significant bit data of the dividend A is divisible at this stage as a result of the division operation, that is, the 8-bit adder 12h combines the data Y corresponding to the divisor B and the most significant bit data of the dividend A. When all bit data of the addition result data (hereinafter referred to as data Z) of included data X and carry data are all 0, the OR gate 14h transfers the 0 data to the inverter 16
It is sent to AND gates 15f and 15a. Therefore, according to the logic operation of each circuit, data of 1 is sent from the inverter 16 and NAND gates 15f to 15a to the multiplexers 17g to 17a and 18, and the data of 0 is supplied to the multiplexers 17g to 17a as described above.
Select and send the data. Therefore, in the quotient data, data Q6 to data Q0 are all 0. In addition, the 8-bit adder 12h is used as Q7, which is the most significant bit data of the quotient.
This corresponds to the most significant bit data of the carry data sent by . Further, the multiplexer 18 selects and sends out data of 0 based on the control signal of data of 1 sent out by the NAND gate 15a, so the remainder data becomes 0.

Similarly, if the second bit of data from the most significant bit of the dividend A is supplied and the result of executing the division operation is divisible at this stage, that is, in the 8-bit adder 12g, all bits of data Z are When all are 0,
The OR gate 14g sends 0 data to the NAND gate 15f.
to 15a. Therefore, NAND gate 15f
1 data from 15a to multiplexer 17f
to 17a, and multiplexers 17f to 17a select the supplied 0 data and send it out. Therefore, in the quotient data, data Q5 or data Q0 are all 0.
becomes. Further, data Q7 corresponds to the most significant bit data of the carry data sent out by the 8-bit adder 12h. On the other hand, 8
Since the data Z sent out by the bit adder 12h is not 0, the inverter 16 transfers the 0 data to the multiplexer 17.
Therefore, the multiplexer 18 selects and sends out the most significant bit data of the carry data sent out by the 8-bit adder 12g. Therefore, data Q6 becomes the most significant bit data of the carry data sent out by the 8-bit adder 12g.

Hereinafter, each 8-bit adder 12f to 12
The same operation occurs when the data Z becomes 0 at b. In this way, when the bit data constituting the dividend A is taken in one bit at a time and the division operation is executed, the data Z sent out by the 8-bit adder is
When becomes 0, that is, when it is so-called divisible, the ungenerated quotient and remainder can be generated without using an 8-bit adder, and the division time can be significantly shortened.

If it is not divisible up to the 8-bit adder 12a, the quotient data is made up of the data sent out by the multiplexers 17g to 17a, similar to the conventional divider, and the data sent out by the multiplexer 18 is Construct the remainder data.

Second Embodiment In FIG. 2, an 8-bit divider 20 comprehensively includes the 8-bit adders 12h to 12a shown in FIG. 1 and each processing circuit 13 connected to the output side of each 8-bit adder. 1, and the multiplexer 21 represents the multiplexers 17g to 17a shown in FIG. In this example, O shown in FIG.
R gate 14h or 14b, inverter 16, NAN
A circuit portion constituted by D gates 15f to 15a is not provided.

Comparator 2 supplied with dividend A and divisor B
3 determines the magnitude relationship between dividend A and divisor B and calculates dividend A.
When the divisor B is larger than the divisor B, that is, the dividend A<divisor B, a signal of 1 is sent to the multiplexer, and when the dividend A is larger than the divisor B, that is, when the dividend A>the divisor B, a signal of 0 is sent to the multiplexer. 21 and multiplexer 22.

Similar to the first embodiment, the multiplexer 21 is connected to the carry data output terminal of each 8-bit adder forming the 8-bit divider 20, and carry data is supplied from the 8-bit adder. Also, data of 0 is supplied. Such a multiplexer 21 selects and sends out data of 0 when supplied with the control signal of 1 sent out by the comparator 23 described above, and on the other hand, when the control signal of 0 is supplied, it selects and sends out the carry data. Select and send.

The multiplexer 22 includes an 8-bit divider 20 similar to the multiplexer 18 shown in the first embodiment.
The remainder data is supplied, and the data of the dividend A is supplied, and the control signal of 1 sent from the above-mentioned comparator 23 is supplied, so that the data of the dividend A is selected and sent, while the control signal of 0 is supplied. is supplied, the above-mentioned surplus data is selected and sent.

In the divider configured in this way,
The data of the dividend A and the divisor B are supplied to the 8-bit divider 20 and simultaneously supplied to the comparator 23.
The magnitude relationship between them is compared at
It can be done. Furthermore, the multiplexer 22 selects and sends out the dividend A based on the control signal, so that the remainder data can be forcibly set to the value of the dividend A. In this way, in the divider of this embodiment, if dividend A<divisor B, the quotient and remainder are generated at the same time as the division operation starts, so there is no need to perform operations on all the bits that make up the dividend The time can be significantly reduced.

Third Embodiment In FIG. 3, an 8-bit divider 20 comprehensively includes the 8-bit adders 12h to 12a shown in FIG. 1 and each processing circuit 13 connected to the output side of each 8-bit adder. In this embodiment, the circuit portion constituted by the OR gates 14h to 14b, the inverter 16, and the NAND gates 15f to 15a shown in FIG. 1 is not provided. Further, as shown in FIG. 1, the multiplexer 24 is supplied with the most significant bit data of the carry data sent out by each 8-bit adder constituting the 8-bit divider 20, and is also supplied with the most significant bit data of the carry data sent out by each 8-bit adder constituting the 8-bit divider 20.
The diagram generally shows each multiplexer to which bit data of is supplied. The multiplexer 25 includes
An 8-bit divider 20 similar to the multiplexer 18 shown in FIG.
An output signal from a processing circuit 13 connected to an 8-bit adder 12a constituting the 8-bit adder 12a is supplied, and 0 data consisting of 8 bits is also supplied.

In this embodiment, the output side of the NOR circuit 26 to which 7-bit data excluding the least significant bit data of the data constituting the divisor B is supplied is connected to a NAND gate 27. Further, the least significant bit data of the divisor B is supplied to the input side of the NAND gate 27, and the NAND gate 27 generates a control signal by the logical operation of these supplied signals, and sends the control signal to the multiplexers 24 and 25. Send.

[0023] The multiplexer 24 has a NAND gate 2
Carry data is selected and sent by the 8-bit divider 20 when the control signal for the data from 7 to 0 is supplied, and the data of dividend A is selected and sent, and when the control signal for the data from 1 is supplied from the NAND gate 27. Select and send. The multiplexer 25 outputs 0 from the NAND gate 27.
The 8-bit divider 20 selects and sends out the data of 0 when the control signal of the data is supplied, and the 8-bit divider 20 selects the remainder data to send when the control signal of the data of 1 is supplied from the NAND gate 27. Send.

The 8-bit divider 20 is supplied with a dividend A and a divisor B in the same manner as in each of the embodiments described above. In the divider of this embodiment configured as described above, when the value of the divisor B is 1, the NAND gate 27 sends out a control signal of 0 data, so the multiplexer 24 sends out the value of the dividend A. Then, the multiplexer 25 selects and sends out data of 0. The value of the dividend A sent out by the multiplexer 24 is the quotient value in the division operation, and the value of the dividend A sent out by the multiplexer 25
The value of 0 sent out by is the remainder value in the division operation. In this way, if the value of the divisor B is 1, the quotient and remainder can be generated before the 8-bit divider 20 performs the division operation, and the time required for the division operation can be significantly shortened.

In the explanation of each of the above embodiments, the dividend A and the divisor B are 8 bits, but this is of course not limiting, and data having any number of bits can be used in the configuration shown in each embodiment. This can be done by changing the part according to the number of bits. In addition, the divider having the components shown in the second and third embodiments also has the effect of shortening the division operation time as described above, but the comparator shown in the second and third embodiments 23, NOR gate 26, and NAND gate 27 are preferably added to the divider shown in the first embodiment, and furthermore, both of the above components are added to the divider shown in the first embodiment. A divider added to the .

[0026]

Effects of the Invention As detailed above, according to the present invention, if the division is divisible in the middle of the division operation, the division operation is not performed on the remaining bit data of the dividend, and the division operation is performed on the remaining bit data. will be, the quotient is 0
Since the value of 0 is forcibly generated and the value of 0, which would be generated as the remainder value, is forcibly generated, the time required for the division operation can be shortened. Furthermore, if the divisor is larger than the dividend, the division operation is not performed and the quotient is forced to 0.
and the remainder data is the dividend, or if the divisor is 1, the division operation is not executed, the quotient is forced to be the dividend, and the remainder is forced to be 0. By doing so, the division operation time can be further reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of a divider according to the present invention.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the divider of the present invention.

FIG. 3 is a block diagram showing the configuration of a third embodiment of the divider of the present invention.

FIG. 4 is a block diagram showing the configuration of a conventional divider.

FIG. 5 is a block diagram showing the configuration of a conventional divider that performs a division operation on 8-bit data.

[Explanation of symbols]

14b to 14h...OR gate, 15a to 15f
...NAND gate, 16...Inverter, 17a to 1
7g...Multiplexer, 23...Comparator, 26...NOR gate, 27...NAND gate.

Claims (3)

[Claims] Claim 1: An adder that performs an addition operation between data Y constituting the divisor and data X containing bit data of the data constituting the dividend for each digit and carry data has multiple stages corresponding to the number of bits constituting the divisor and dividend. In the divider configured to be connected in parallel to the divider, a detection unit detects that the addition result data of the addition operation in the adder is 0;
a first selection section that selects and sends either carry data or 0 data sent out by the adder based on a control signal sent out by the detection section; A divider comprising: a second selection section that selects and sends out either one based on the control signal sent out by the detection section. 2. A comparator for determining the magnitude relationship between the dividend and the divisor, and a comparator for selecting and transmitting either carry data or 0 data transmitted by the adder based on a control signal transmitted by the comparator. 3. A fourth selection section that selects and sends out either the remainder data or the dividend data sent out by the adder based on the control signal sent out by the comparator. Divider. 3. A detector for detecting that the divisor is 1, and a detector for selecting and transmitting either carry data or dividend data transmitted by the adder based on a control signal transmitted by the first detector. 5. A sixth selection section that selects and sends out either the remainder data sent out by the adder or the 0 data based on the control signal sent out by the one detector. Divider listed.