JP2617591B2 - Serial operation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial operation circuit that serially outputs the sum of serial data of 2 ⁿ (n ≧ 2) or less as an operation result. .

[Conventional technology]

FIG. 2 is a circuit diagram showing a conventional serial operation circuit.

In the figure, reference numeral 1 denotes eight serial data inputs D0 to D7.
It is an input part which has. The serial data inputs (D0, D1), (D2, D3), (D4, D5), and (D6, D7) of the input unit 1 are used as addend inputs, respectively, and the first-stage full adders FA11, FA12, FA13 and
FA14 is connected. The second stage full adders FA21 and FA22 are connected to adders of the full adders FA11 and FA12 and the full adders FA13 and FA14, respectively, as addend inputs.
A third stage (final stage) full adder FA31 is connected to the adder output of the full adders FA21 and FA2 as an addend input. The addition output of the full adder FA31 is output from the output terminal 3 to the operation result Do.
Output serially as ut.

The full adders FA11 to 14, FA21, FA22, and FA31 (hereinafter, simply referred to as "full adder FA") have carry holding registers R11 to 14, R21, R22, and R31, respectively.
(Hereinafter referred to simply as “carry holding register R”). The carry holding register R stores the carry output of the corresponding full adder FA,
The same full adder delaying the carry output by one bit time
Output as carry input of FA. One carry holding register R and one corresponding full adder FA constitute one serial adder.

As described above, the serial operation circuit configures the calculation unit 10 by serially connecting the serial adders to the two inputs at one ratio with respect to the eight serial data inputs D0 to D7, and configures the calculating unit 10 at the final stage. The addition output of (FA31, R31) is serially output as the operation result Dout.

Since the serial operation circuit having the above-described configuration has a three-stage configuration of a serial adder, the serial operation circuit has a three-stage delay from the time when the most significant bit of the bit data is taken into each of the serial data inputs D0 to D7 of the input unit 1. The calculation result is output from the output terminal 3.

Therefore, when the least significant bit of the next serial data SD1 is taken into the input unit 1 with a delay within 3 bit time from the time when the most significant bit of the previous serial data SD0 is taken into the input unit 1, the serial data SD1 However, there is a problem in that the effect of the least significant bit appears in the operation result Dout of the serial data SD0.

In order to solve this problem, a serial arithmetic circuit
Shown in the figure. As shown in the figure, separately from the calculation unit 10, eight serial data inputs D0 to D7 of the input unit 1 (separated for convenience from 1a and 1b) are input to a full adder FA11 '. ~
A calculation unit 10 'having the same configuration as the calculation unit 10 and comprising a carry holding register R11' to 14 ', R21', R22 ', and R31', is provided to the input unit 1 as 14 ', FA21', FA22 ', and FA31'. Connected.

The addition result of the calculation units 10 and 10 ′ is
Input and B input respectively. The selector 2 selectively outputs to the output terminal 3 the addition result (A input) of the calculation unit 10 in the A mode and the addition result (B input) of the calculation unit 10 'in the B mode as the calculation result Dout.

With this configuration, from the time t0 when the most significant bit of the previous serial data SD0 was taken into the input unit 1, 3
Even if the least significant bit of the next serial data SD1 is taken into the input unit 1 with a delay within the bit time, for example, with the selector 2 set to the A mode, the input unit 1 is sent to the calculation unit 10 until time t0. Connect, and after time t0, input unit 1 is calculated
By connecting to 10 'and setting the selector 2 in the A mode until the time when the desired operation result Dout is obtained, the effect of the least significant bit of the serial data SD1 does not appear in the operation result Dout of the serial data SD0. It can be output as an accurate calculation result Dout.

[Problems to be solved by the invention]

The conventional serial operation circuit is configured as described above, and it takes (m + n) bit time to finally obtain an addition result of 2 ⁿ m-bit serial data as an operation result Dout.

Therefore, when the time interval between successive m-bit serial data sequentially taken into the input unit 1 is within the n-bit time, like the serial operation circuit shown in FIG.
There is a problem that the circuit scale becomes large, such as providing a full adder twice as usual (FIG. 2).

The present invention has been made in order to solve the above-described problems, and does not increase the circuit scale, and is not affected by subsequent serial data even if the serial data input time interval is short. It is another object of the present invention to obtain a serial operation circuit capable of outputting the operation result of the previous serial data.

[Means for solving the problem]

The serial operation circuit according to the present invention has 2 ⁿ (n ≧ 2)
A circuit for serially outputting the sum of the following numbers of serial data as an operation result, comprising: an input unit having 2 ⁿ 1-bit input terminals; and a serial adder having two inputs for the input unit. A first calculator connected in series at one ratio and serially outputting an addition result from a serial adder at a last stage; and a serial adder of a first stage connected to the input unit in the first calculator. A second calculating unit that serially connects the serial adder to the two inputs at one ratio with respect to the carry holding register of the adder, and outputs the addition result serially from the last serial adder; The carry holding register of the serial adder of the calculation unit is selectively connected to one of the carry output of the serial adder and the carry output of the serial adder of the first calculation unit corresponding to the corresponding stage. First choice to give to And stage, among the addition result of the addition result and the second calculation portion of the first calculation unit, and a second selecting means to selectively output one of the addition result as the operation result.

[Action]

According to the present invention, the following processing can be performed.
Until the input time of the most significant bit of the serial data supplied to the input unit, the first selecting means stores the carry holding register of the serial adder of the second calculating unit in the corresponding first calculating unit of the corresponding stage. The carry output of the serial adder is provided, and the addition result of the first calculation unit is output as an operation result by the second selection means. Then, after the input time of the most significant bit of the serial data, the carry output of the serial adder is given to the carry register of the second serial adder by the first selecting means, and the carry output of the serial adder is given by the second selecting means. By outputting the addition result of the calculation unit 2 as an operation result,
An addition process is performed on the output of the carry holding register of the first stage serial adder of the first calculation unit.

〔Example〕

FIG. 1 is a circuit diagram showing a serial operation circuit according to an embodiment of the present invention.

In the figure, reference numeral 1 denotes eight serial data inputs D0 to D7.
It is an input part which has. The serial data inputs (D0, D1), (D2, D3), (D4, D5), and (D6, D7) of the input unit 1 are used as addend inputs, respectively, and the first-stage full adders FA11, FA12, FA13 and
FA14 is connected. The second stage full adders FA21 and FA22 are connected to adders of the full adders FA11 and FA12 and the full adders FA13 and FA14, respectively, as addend inputs.
A third stage (final stage) full adder FA31 is connected to the addition outputs of the full adders FA21 and FA22 as addend inputs. The addition output of the full adder FA31 is connected to the A input of the selector 20.

Carry holding registers R11 to 14, R21, R22 and R31 are connected to the full adders FA11 to 14, FA21, FA22 and FA31, respectively. The carry holding register R stores the carry output of the corresponding full adder FA, delays the carry output by one bit time, and outputs the result as the carry input of the same full adder FA. One carry holding register R and one corresponding full adder FA constitute one serial adder.

Carry holding auxiliary registers SR11 to SR14 are further connected to the first-stage full adders FA11 to FA14. Carry holding auxiliary registers SR11 to SR14 are the corresponding full adders.
The carry outputs of FA11 to FA14 are stored, the stored carry outputs are delayed by one bit time, and the carry outputs stored in SR11 and SR12 are used as the addend inputs of the auxiliary full adder SFA21.
The carry output stored in R13 and SR14 is the auxiliary full adder SFA
It has 22 addend inputs.

The adder outputs of the auxiliary full adders SFA21 and SFA22 become the addend inputs of the auxiliary full adder SFA31. And the auxiliary full adder S
The addition output of FA31 is connected to the B input of selector 20.

The carry outputs of the auxiliary full adders SFA21, SFA22 and SFA31 are supplied to the B inputs of the selectors 21, 22 and 31. The A inputs of these selectors 21, 22 and 31 are connected to a full adder FA2.
1, carry outputs of FA22 and FA31 are provided. selector
21, 22, and 31 selectively output one of the carry outputs obtained by the A input and the B input to the carry holding auxiliary registers SR21, 22, and 31. The carry holding auxiliary registers SR21, SR22, and SR31 store the carry output by one.
The bit times are delayed and output as carry inputs of the corresponding auxiliary full adders SFA21, SFA22 and SFA31. In addition, selector 20
Outputs one of the added outputs obtained from the A input and the B input from the output terminal 3 as an operation result Dout selectively.

As described above, the serial operation circuit is configured by connecting a serial adder composed of a carry holding register R and a full adder FA in series at two inputs to one of eight serial data inputs D0 to D7. With respect to the calculated calculation unit and the outputs of the carry holding auxiliary registers SR11 to SR14, a carry adder register SR, an auxiliary full adder SFA, and a serial adder composed of a selector are connected in series at one input ratio to two inputs. And an auxiliary calculation unit configured as described above. And the selector
According to 20, the addition result of one of the calculation unit and the auxiliary calculation unit is selectively output as the calculation result Dout.

In such a configuration, the selectors 20, 21, 22
And 31 select the bit data obtained from the A input and output the addition result of the calculation unit as the operation result Dout. At this time, the carry outputs of the full adders FA21, 22 and 31 are stored in the carry holding auxiliary registers SR21, 22 and 31, respectively. This is performed so that the auxiliary calculation unit can accurately derive the addition result in consideration of the carry output of the serial data input up to that point, when shifting from the normal operation to the carry operation mode described later. Will be Then, after the time t0 when the most significant bit of the previous serial data SD0 is taken into the input unit 1, the mode shifts to the carry operation mode, and the selectors 20 to 22 and 31 select the bit data obtained from the B input and Output is good, the addition result of the auxiliary calculation unit is the operation result Dout
Output as

Since the addition processing of the auxiliary calculation unit is performed based on the outputs of the carry holding auxiliary registers SR11 to SR14, the least significant bit of the serial data SD1 next taken in the input unit 1 is the serial data of the auxiliary calculation unit. The time that affects the addition processing of data SD0 is determined by carry holding auxiliary registers SR11 to SR11.
As a result of passing through 14, there is a delay of one bit time from the prior art. Therefore, even if the least significant bit of the serial data SD1 is taken in at least three bit times from the time t0, the effect of the least significant bit of the serial data SD1 can be prevented from appearing in the operation result Dout of the serial data SD0. .

Also, the number of full adders can be reduced by four as compared with the serial operation circuit of FIG. 3, so that the circuit scale can be reduced. In other words, ^if a serial arithmetic circuit for adding 2 ⁿ m-bit serial data is configured as in the present embodiment, 2 ^{n -1} full adders can be compared with a serial arithmetic circuit having a configuration as shown in FIG. Can be reduced.

In the present embodiment has described the serial arithmetic circuit for adding the serial data of eight (= 2 ³⁾ is not limited to this, 2 ⁿ pieces (n by applying the present embodiment 2 It is possible to configure a serial operation circuit that adds the serial data of the above integers). Furthermore, even if k ≠ 2 ⁿ , if k ≧ 3, a serial operation circuit corresponding to 2 ⁿ (> k) serial inputs is configured, and (2 ⁿ −k) inputs are
This can be easily realized with a configuration in which “0” is fixed input. In addition, full adders FA and SFA, carry holding register R,
The SR and the selectors 20, 21, 22 and 31 may be any as long as they fulfill their functions.

〔The invention's effect〕

As described above, according to the present invention, the following processing can be performed. Until the input time of the most significant bit of the serial data supplied to the input unit, the first selecting means stores the carry holding register of the serial adder of the second calculating unit in the corresponding first calculating unit of the corresponding stage. The carry output of the serial adder is provided, and the addition result of the first calculation unit is output as an operation result by the second selection means. After the input time of the most significant bit of the serial data, the first
The carry output of the serial adder is given to the carry register of the second serial adder by the selecting means, and the addition result of the second calculating section is output as the operation result by the second selecting means, 1 performs an addition process on the output of the carry holding register of the first-stage serial adder of the calculation unit.

The second calculation unit performs the addition process based on the output of the carry holding register of the first-stage serial adder of the first calculation unit. It is possible to delay the time that affects the operation result of the serial data by one bit time, which is the time that passes through the carry holding register. As a result, even if the input time interval of successive serial data is shortened by one bit time as compared with the related art, the operation result of the previous serial data can be output without being affected by the subsequent serial data.

In addition, since the number of serial adders in the first stage is set to be equal to the number of serial adders in the first stage in the serial arithmetic circuit having a normal configuration, the circuit scale does not increase so much.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a serial operation circuit according to an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams showing a conventional serial operation circuit. In the figure, 1 is an input unit, 20, 21, 22 and 31 are selectors,
3 is an output terminal, FA11 to 14, FA21, FA22 and FA31 are full adders, SFA21, SFA22 and SFA31 are auxiliary full adders, R11 to 14, R2
1, R22 and R31 are carry holding registers, SR11 ~ 14, SR2
1, SR22 and SR31 are carry holding auxiliary registers. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A serial operation circuit for serially outputting a sum of serial data of 2 ⁿ (n ≧ 2) or less as an operation result, comprising: an input unit having 2 ⁿ 1-bit input terminals; A first calculating unit that serially connects a serial adder to two inputs at one ratio with respect to the input unit, and serially outputs an addition result from a serial adder in a last stage; The serial adder is connected in series at one ratio to two inputs to the carry holding register of the first-stage serial adder connected to the input unit in the section, and the addition result is output from the last-stage serial adder. A second calculating unit that outputs serially; and a carry output of the serial adder and a serial addition of the first calculating unit corresponding to the corresponding stage in a carry holding register of the serial adder of the second calculating unit. One of the carry output First selection means for selectively providing a carry output; and selectively outputting one of the addition result of the first calculation unit and the addition result of the second calculation unit as the calculation result. A serial operation circuit including a second selection unit.