JP3123060B2 - Digital arithmetic circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial processing type digital operation circuit applicable to a product-sum operation required in a digital filter or the like.

[Conventional technology]

2. Description of the Related Art Semiconductor microfabrication technology has steadily advanced in recent years. For example, in a parallel multiplier, the upper limit operating frequency (operation repetition frequency) has been increasing year by year. When digitally processing an image signal, for example, a standard television signal, a digital operation circuit operating at a sampling frequency of 4 fsc (14.32 MHz in the NTSC system) has become easily available. Therefore, it is presumed that arithmetic circuits are often used in time division multiplexing in the processing of digital image signals. However, at present, the operation speed is not so fast that it can be used in the stored program method which is typical of the time division multiplex operation, and it is not expected that such a high-speed operation circuit can be realized in the near future.

In the case of the stored program method, it is necessary to perform one operation in about 1/100 of one sampling period. That is, for real-time processing, the processing must be completed before the next sample data comes. At present and in the near future, the operation speed is such that an operation of several to several tens of cycles can be performed in one sample period.

A parallel multiplier is obtained by arranging a plurality of adders,
The adder is obtained by arranging 1-bit full adders.
The smaller the unit circuit is, the higher the operation repetition frequency can be. Therefore, performing time-division processing using a circuit of a small scale and realizing the same function as a circuit of a large scale is effective in increasing the calculation speed.

When examining which of the one-time processing and the time-division processing is more advantageous, since the data word length is generally 8 bits, 12 bits, 16 bits or 20 bits, each bit of data is serially processed. Serial processing is suitable for such a study. In other words, in the example of performing 10-bit addition, a 10-bit addition circuit requires only one cycle of arithmetic processing, but requires 10 full adders, while bit serial processing requires
It requires 10 cycles of arithmetic processing, but can be configured with one full adder. When performing multiplication with 10 partial products, a parallel multiplier can obtain a multiplication result in one cycle, but requires 10 10-bit addition circuits (100 1-bit full adders). On the other hand, the bit serial processing requires 10 cycles when using one 10-bit addition circuit, and requires 100 cycles when using one 1-bit addition circuit.

Among the configurations of the plurality of arithmetic circuits, a circuit configuration in which the ratio obtained by dividing the data cycle by the operation time of the arithmetic unit is equal to the number of cycles is efficient. Recent arithmetic circuits are required to perform digital processing on television signals.
Since several tens of cycles can be calculated in the sampling cycle,
Arithmetic circuits of the bit serial processing or a method based thereon are advantageous in reducing the circuit scale.

However, in order to realize a single target operation unit, bit serial processing, in which a prepared circuit unit is repeatedly operated in multiple cycles, can flexibly cope with differences in word length by providing a margin for the number of cycles. On the other hand,
There is a problem that redundant cycles are likely to occur. For example, when constructing a system in which the word length of the input or output changes each time a multiplication or addition is performed, and when each part performs bit serial processing, the number of cycles required at the processing of the longest word length is the number of data cycles. It places an upper bound on speed, which results in many redundant cycles elsewhere. Alternatively, there may be a problem that the data speed limit defined as described above is lower than the data speed to be processed. A suitable solution in this case is desired.

Prior to the description of a conventional digital multiplier, an example of a conventional bit serial processing addition circuit will be described with reference to FIG. 9-bit output data Y (= A + B) is obtained from 8-bit input data A and B. The data is, for example, a code having 2's complement. Input data A and B are loaded into shift registers 51 and 52, respectively. The load signal is supplied to terminals 53 and 54, respectively. Shift register 51
And the output of the flip-flop of the most significant bit of each of 52 is fed back to the input side so that the word length can be expanded.

The input data A and B are output from the LSB from the shift registers 51 and 52 in bit series in synchronization with a clock (not shown). The serial data a from the shift register 51 and the serial data b from the shift register 52 are supplied to a bit serial type adder circuit 55. The addition circuit 55 includes a full adder 56 and a flip-flop 57 to which the output of the full adder 56 is supplied.
It consists of 58. The full adder 56 is supplied with the serial data a and b and the output c of the flip-flop 57.

The full adder 56 calculates the number of "1" in the three input data as 2
Output as bits. That is, the input of the full adder is a,
b, the carry input is c, the lower bit of the output is s, and the upper bit is c ', (s = xy
c, c '= xy + xc + yc). The upper bit (carry) of the output of full adder 56 is supplied to flip-flop 57, and its lower bit (sum)
Is supplied to the flip-flop 58. The flip-flop 57 marked with * is a flip-flop that can be initially cleared.

The lower bits of the output of the full adder 56 are serially supplied from the LSB to the 9-bit shift register 59. The shift register 59 outputs these 9 bits as an output Y in parallel at the timing when the 9 bits are input.

FIG. 9 shows a timing chart of the addition circuit shown in FIG. Input data A and B are simultaneously loaded into the shift registers 51 and 52 by a load signal, and serial data a and b are serially output from the shift registers 51 and 52 in synchronization with a clock. In FIG. 9, LSB, 1, 2,.
.., MSB is a number assigned to each bit, and a load signal indicated by a broken line indicates a timing at which the next load is possible.

Flip-flop on the output side of full adder 56 of adder circuit 55
57 is cleared by the clear signal. Next, input data A
And the sum of the LSBs of L and B are taken into the flip-flops 57 and 58, and output as the output d of the flip-flop 58 in the next clock cycle.
B is obtained. Since the carry is one bit higher, it is used by the full adder 56 to add the next bit. Hereinafter, the addition operation is repeated in the same manner, and an addition output Y is generated from the shift register 59 at the output timing. Thus, in the addition of 8-bit data, the word length extends one bit higher, so that the addition is completed in 9 clock cycles.

When a bit serial output is required as the addition output, the shift register 59 is omitted.

The addition circuit 55 shown in FIG.
When replaced with an exclusive OR gate, a logical operation can be performed. In the logical operation, a logical output can be obtained with the number of cycles equal to the word length.

FIG. 10 shows an example of a conventional serial / parallel digital multiplier. The 8-bit input data A (multiplicand) is loaded into the 8-bit register 61 by a load signal from the terminal 63. Also, the 8-bit input data B (multiplier) is supplied to the terminal 64.
Is loaded into the 8-bit shift register 62 in response to the load signal. These data A and B are straight binary codes.

The 8 bits of the multiplicand from register 61 are AND gate 65A ~
Supplied to 65H respectively. Each bit of the multiplier from the shift register 62 is sequentially supplied from the LSB to the AND gates 65A to 65H. Therefore, when the bit of the multiplier is "1", the data of A is output from the AND gates 65A to 65H, and when the bit of the multiplier is "0", the data of all eight bits are "0". From the AND gates 65A to 65H, eight partial products equal to the number of bits of the multiplier are generated. This partial product is added by the adder circuits 66A to 66H of the bit serial processing similar to the adder circuit 55 of FIG.

In the adders 66A to 66H, the addition output (sum) is supplied to the lower-order bit addition circuit at the time of the next addition.
The addition output is taken out of the LSB in series from the LSB addition circuit 65A and input to the 16-bit shift register 67. The multiplication output Y (= A × B) is taken out of the shift register 67 in parallel.

FIG. 11 is a timing chart of the configuration of FIG. The loading of the multiplier B into the shift register 62 and its output data a are obtained in the same manner as in the configuration of FIG. Register 61
Is loaded simultaneously with the shift register 62, and AND
LSB is generated in the output data b of the gate 65A. Adder circuit 66
The flip-flops marked with * of A to 66H are cleared by the clear signal.

The bit of bit number 1 is fed back as data c to the full adder of the adder circuit 66A, and the LSB is supplied from the adder circuit 66A to the shift register 67. At this time, the addition circuit 66B
Then, the data c 'fed back to the full adder and the adder 66
The higher order bits occur as data d 'for the full adder of A. In addition circuits 66C to 66H,
An operation similar to 66A and 66B is performed, so that eight partial products are added. Thus, as can be seen from the possible timing of the next load, indicated by the dashed line, one multiplication ends in 16 cycles equal to the output word length.

In the case of a straight binary code, the word length of the multiplied output is the sum of the word lengths of the multiplicand and the multiplier. If the data is a two's complement code, the word length of the multiplied output is one bit less. Regardless of the code, the multiplier uses 1
The word length is approximately doubled by one operation.

[Problems to be solved by the invention]

As described above, in the case of the multiplier of the bit serial processing,
The number of cycles required for one operation is nearly double compared to the logical operation or the addition. Therefore, in a signal processing system in which a logical operation circuit, an adder, a multiplier, and the like are configured in a bit-serial system, the cycle required for the arithmetic processing of the multiplier becomes longer. A considerable idling cycle occurs.

Accordingly, an object of the present invention is to provide a digital operation circuit in which the number of cycles required for multiplication is reduced.

[Means for solving the problem]

According to the present invention, a plurality of partial products are sequentially provided with a multiplicand, a control signal formed by supplying a multiplier to an encoder of a secondary booth is supplied, and a plurality of partial products are generated in units of 2 bits of the multiplier. A plurality of adders (27A, 27B, 27C) in units of 2 bits to which outputs of the generation circuits (6A to 6H) and partial product generation circuits (6A to 6H) are respectively supplied
A digital operation circuit comprising an adder configured in a pipeline format and adding a plurality of partial products by the adder to obtain a multiplied output.

[Action]

If the multiplier is 8 bits, four partial products are generated by the second order Booth algorithm. In this case, these partial products are formed in units of 2 bits. The addition of the partial products is added by a 2-bit serial addition circuit, so that the number of cycles required to generate the multiplied output can be reduced to half.

〔Example〕

Hereinafter, the present invention will be described with reference to the drawings. This description will be made in the following order.

a. Reference Configuration b. One Embodiment a. Reference Configuration FIGS. 1A and 1B separately show a reference configuration of the present invention, and show output data d1 to d8 of the circuit of FIG. 1A.
Are input data of the circuit of FIG. 1B.

8-bit input data A (multiplicand) having a code of 2's complement is loaded into the shift registers 1A and 1B in synchronization with a load signal (not shown). Shift register 1A and
Each of the shift registers 1B is a 4-bit shift register. One shift register 1A is loaded with (LSB, bit of bit number 2, bit of bit number 4, bit of bit number 6), and the other shift register The register 1B is loaded with (bit number 1 bit, bit number 3 bit, bit number 5 bit, MSB). The MSB is fed back to the top of each shift register 1A and 1B in order to increase the word length.

Data a1 output in series from the shift register 1A is supplied to a series connection circuit of flip-flops 2A, 3A and 4A. The data a2 output in series from the shift register 1B is supplied to a series connection circuit of flip-flops 2B, 3B, 4B and 5. These flip-flops can be initially cleared, as indicated by *. The taps derived from the series connection of the flip-flops 2A, 3A and 4A and the taps derived from the series connection of the flip-flops 2B, 3B, 4B and 5 are connected to the decoders 6A to 6H of the secondary booth, respectively. .

The decoders 6A to 6H of these booths have the same configuration as each other, and as shown with respect to the decoder 6A, a selector 7, an AND gate 8, and an exclusive OR gate 9 are provided.
It is composed of Also, flip-flops 10A to 10H are provided to receive the output data of the decoders 6A to 6H.

The outputs of the flip-flops 10A and 10B are supplied to an adder 11A that performs serial addition in units of 2 bits. An adder 11B to which the outputs of the flip-flops 10C and 10D are supplied, an adder 11C to which the outputs of the flip-flops 10E and 10F are supplied,
Adder to which outputs of flip-flops 10G and 10H are supplied
11D is provided. These adders 11A to 11D are provided to add "1" to the LSB required when inverting the polarity. Pulses T1 to T4 correspond to "1"
It is.

When the multiplication of (A × B = Y) is performed by the secondary Booth algorithm, four partial products are formed for every two bits of the multiplier B (8 bits in this configuration). In this case, the multiplier B
Looking at the three consecutive bits of 0, ± 1 times the multiplicand A,
Any partial product of ± 2 times is formed, and the partial products are added to obtain a multiplied output. The configuration shown in FIG. 1A shows a configuration for forming four partial products in two bits in parallel.

Pi, Qi, Ri (i = 1,2,3,4) are Booth's decoder 6A
To 6H. That is, the control signal P
1, Q1, R1 are for decoders 6A and 6B, control signals P2, Q2, R2 are for decoders 6C and 6D, control signals P3, Q3, R3 are for decoders 6E and 6F, and control signals P4, Q4, R4 are for decoders 6G and 6H.

By supplying three consecutive bits of the multiplier B to a Booth encoder (not shown), control signals Pi, Qi, Ri are formed. The selector 7 of each of the decoders 6A to 6H outputs the control signal Pi
And the output signal of the selector 7 and the control signal Qi
The output of the AND gate 8 and the control signal Ri
Are supplied to the exclusive OR gate 9. The selector 7 selectively outputs one and two times the multiplicand when paying attention to a certain bit digit. 1 when the control signal Pi is “0”
Double data is obtained from the selector 7, and when this is “1”, double data is obtained from the selector 7. AND gate 8
Is 0 (that is, 0 of the multiplicand) when the control signal Qi is “0”.
Times) is provided. The exclusive OR gate 9 is provided to invert “0” and “1” when the control signal Ri is “1”. By adding "1" to the LSB by the adders 11A to 11D in addition to this processing, the polarity is inverted.

In the encoder of the secondary booth, the following control signals Pi, Qi, and Ri are generated according to the three bits of the multiplier B.

The booth decoders 6A to 6H output control signals Pi, Qi,
A partial product is generated according to Ri as follows.

The 2-bit adder 11A includes full adders 12 and 13 and flip-flops 14, 15, and 16. The first input of the full adder 12 is always "0", the output of the flip-flop 10A is supplied as its second input, and the carry output of the full adder 13 is supplied as its third input. The pulse T1 is supplied as a first input of the full adder 13, the output of the flip-flop 10B is supplied as its second input, and the flip-flop 14B is supplied as its third input.
The carry output of the full adder 12 passed through is fed back. The sum of the full adder 12 is taken out as the output d1 via the flip-flop 15, and the sum of the full adder 13 is
Retrieved as output d2 via 16.

The other two-bit adders 11B to 11D are also the adders described above.
It has the same configuration as 11A, and outputs d3, d4,. In these adders 11A to 11D, when the control signal Pi is set to "1", the pulse Ti is set to "1" and "1" is added to the LSB.

The outputs d1 and d2 of the adder 11A are partial products corresponding to the LSB of the multiplier B and the two bits of the bit of the bit number 1, and the outputs d3 and d4 of the adder 11B are the bit numbers 2 and 3 of the multiplier B. A partial product corresponding to two bits of bits,
The outputs d5 and d6 of the adder 11C are partial products corresponding to two bits of the bit number 4 and the bit number 5 of the multiplier B, and the outputs d7 and d8 of the adder 11D are the bit number 6 of the multiplier B.
And the partial product corresponding to the two bits of the MSB.

Data d1 to d8 of the partial product determined in units of 2 bits described above
Is supplied to the adders 17A and 17B in FIG. 1B. The outputs e1 and e2 of the adder 17A and the outputs e3 and e4 of the adder 17B are supplied to the adder 18. The outputs f1 and f2 of the adder 18 are supplied to the adder 19. The adders 17A, 17B, 18 and 19 are adders in units of 2 bits similar to the adders 11A to 11D. Adders 17A, 17B and 18 perform tree addition of partial products. When the multiplicand A and the multiplier B are 8 bits, the adder
The 18 outputs f1 and f2 are 15 bits long.

In this example, the multiplication outputs are accumulated as in a filter operation. Therefore, the outputs g1 and g2 of the adder 19 are serially input to the 9-bit shift registers 20A and 20B. From the taps derived from these shift registers 20A and 20B
20-bit output data Y is extracted. The serial outputs h1 and h2 of the shift registers 20A and 20B are fed back to the input side of the full adder 19. Adder 19 and shift registers 20A, 20B
Constitutes a cumulative adder. This accumulator can generate output data Y having a length of 20 bits.
Up to ²⁵ cumulative additions can be performed without overflow.

FIG. 2 is a timing chart of the operation of the reference configuration of the present invention. Input data A is loaded to the shift registers 1A and 1B at the same timing as the clear pulse. By the clear pulse shown in FIG. 2, the flip-flops 2A, 2B, 3A, 3B, 4A, 4B and 5 are cleared at the first timing of one operation processing. The flip-flops 14 of the adders 11A to 11D marked with * are cleared by a pulse obtained by delaying the clear pulse of FIG. 2 by one clock. Adder 17
The flip-flops marked with * in A and 17B are cleared by a pulse obtained by delaying the clear pulse in FIG. 2 by two clocks. In addition, the flip-flop marked with * of the adder 18 is
The clear pulse shown in FIG. 2 is cleared by a pulse delayed by three clocks. Further, the flip-flop marked with * in the adder 19 is cleared by a pulse obtained by delaying the clear pulse in FIG. 2 by four clocks.

Synchronous with the clock, serial data a1 of (LSB, bit of bit number 2, bit of bit number 4, bit of bit number 6, MSB, MSB,...) Is generated from the shift register 1A. From shift register 1B (bit 1 bit, bit 3 bit, bit 5 bit, MS
B, MSB, MSB, ...) serial data a2 is generated.

In the selector 7 of the booth decoder 6A, one of the data b2 identical to a1 and the data b1 identical to a2 is selected by the control signal P1. In the selector 7 of the booth decoder 6B, one of the data b2 and the output data b3 of the flip-flop 2B is selected by the control signal P1. FIG. 2 shows the outputs c1 and c2 of the flip-flops 10A and 10B of the decoders 6A and 6B of the booth when the selector of the decoder 6A selects the data b1 and the selector of the decoder 6B selects the data b2.

The pulse signal T1 is supplied at the timing of the LSB of the data c2. When not reversing the polarity,
The pulse signal T1 is "0". 2-bit adder 11A
From, one partial product and the corresponding 2-bit data
d1 and d2 are obtained. While this partial product is formed, the control signals P1, Q1, R1 do not change. Similarly to the above, data d3 to d8 of the other three partial products are formed. In this way, by generating a partial product in units of 2 bits, the required number of cycles can be reduced to half.

Note that the flip-flops 2A, 2B, 3A, 3B, 4A, 4B, and 5 are provided for adjusting the timing so that the bit digits when the partial products are added are aligned.

The outputs e1 and e2 of the adder 17A and the outputs e3 and e4 of the adder 17B.
Is generated at the timing shown in FIG. 2, and outputs f1 and f2 obtained by tree-adding the four partial products are taken out from the adder 18. Then, the cumulative addition is performed by the cumulative adder including the adder 19 and the shift registers 20A and 20B. Shift registers 20A and 2
0B is cleared in the first cycle of cumulative addition.

A portion of one embodiment of the invention described above can be schematically represented in FIG. The partial product generation circuits 21, 22, 23 and 24 for generating the four partial products respectively comprise the booth decoders 6A to 6A.
6H and adders 11A to 11D.

FIG. 4 shows an embodiment of the present invention, and FIG. 5 is a timing chart showing the operation of the embodiment. FIG. 4 shows the structure from partial product generation to partial product pipeline addition, and if necessary, a cumulative addition consisting of an adder 19 and shift registers 20A and 20B as in FIG. 1B. A container may be connected. Further, the timing chart of FIG. 5 shows the operation until the multiplied outputs f1 and f2 are generated, and the timing chart in the case of cumulatively adding the multiplied outputs is the same as that of the above-described embodiment.

In one embodiment, adders (11A to 11H) for adding "1" to the LSB in FIG. 1A are omitted, and "1" is added to the LSB by an adder for adding a partial product. It was made. In addition, tree addition is changed to a configuration of pipeline addition.

That is, as schematically shown in FIG. 6, the outputs of the partial product generation circuits 21, 22, 23 and 24 can be added in a pipeline manner. Outputs c5, c6, c7 of partial product generation circuits 23 and 24 and
c8 is added by the adder 27C, and the added outputs d5 and d6 are supplied to the adder 27B. The outputs c3 and c4 of the partial product generation circuit 22 via the flip-flop 29 are supplied to the adder 27B. The outputs e3 and e4 of the adder 27B are supplied to the adder 27A. The adder 27A has two flip-flops 30 and 3
The outputs c1 and c2 of the partial product generation circuit 21 via 1 are supplied. The outputs f1 and f2 of the sum of the partial products are obtained from the adder 27A. As shown in FIG. 6, a pipeline adder has a configuration in which flip-flops are provided on the input side and the output side of each adder.

Here, the flip-flop 30 can be made unnecessary by moving the location of the partial product generation circuit 21 to the location of the partial product generation circuit 22. In addition, the partial product generation circuit 21 whose location is thus moved
And 22 are moved to the location of the partial product generation circuit 23,
The flip-flops 29 and 31 become unnecessary. The circuit configuration shown in FIG. 4 has been embodied based on such an idea.

As shown in FIG. 4, the 8-bit multiplicand is converted into two serial data a1 and a2 by the shift registers 1A and 1B, as in the above-described reference configuration. Input data to the secondary booth decoders 6A to 6H are formed by flip-flops 25A, 25B and 26. As described above, the input data b1, b2, and b3 for the decoders 6A, 6B, 6C, 6D, 6E, and 6F are common in order to omit flip-flops for pipeline addition. The decoder 6G has
The data b3 and the data b4 from the flip-flop 25A are supplied. The data b4 and the data b5 from the flip-flop 26 are supplied to the decoder 6H.

The process of adding “1” to the LSB of the outputs of the decoders 6A to 6H and the pipeline addition are performed by the adders 27A, 27B and 27C. 2 for adding the outputs c1 and c2 of the decoders 6A and 6B
OR gate 2 at carry input of serial adder 27A
8A is connected and the carry output that is fed back and the pulse T1
The signal is supplied to the OR gate 28A. Output c3 of decoders 6C and 6D
The OR gate 28B is also connected to the adder 27B that adds C4 and c4.

Adder 27C has two partial products, decoders 6E and 6E.
The outputs c5 and c6 of F and the outputs c7 and c8 of the decoders 6G and 6H are added. Therefore, the adder 27C is supplied with the pulse T3 to one of the full adders and the OR gate 28C and the pulse T4.
And an OR gate 28D to which is supplied. Two O
The R gates 28C and 28D allow the polarity inversion to be performed simultaneously on the two partial products. Multiplied outputs are obtained as the outputs f1 and f2 of the adder 27A in FIG.

In FIG. 4, the flip-flops marked with * are cleared at the same time as the first embodiment, unlike the above-described embodiment.

In the embodiment shown in FIG. 4, the adder 27C and the adders 27A and 27B have different configurations. In order to avoid this, the configuration shown in FIG. 7 may be used. In FIG. 7, an adder 27D for adding the output of the partial product generation circuit 24 and the "0" data is added, and the output of the adder 27D and the one-stage flip-flop 3 are added.
The output of the partial product generation circuit 23 through 2 is added by the adder 27C. The output of the adder 27C and the output of the partial product generation circuit 22 via the two-stage flip-flops 33 and 34 are added by the adder 27B, and the output of the adder 27B and the three-stage flip-flops 35, 36 and The output of the partial product generation circuit 21 passed through 37 is added by the adder 27A.

In the above-described embodiment, a two-bit serial adder is formed by feeding back two full adders and a carry output of one full adder to the other full adder. However, the configuration is not limited to using two 1-bit full adders.
A dedicated circuit configuration that uses a 2-bit full adder and feeds back the carry output may be used.

〔The invention's effect〕

According to the present invention, a partial product output in series every two bits is formed based on the secondary Booth's algorithm, so that the number of cycles of serial addition of partial products can be reduced to half. According to the present invention, in a system in which an arithmetic circuit is configured by serial processing, it is possible to prevent the number of processing cycles of the multiplier from being longer than that of other adders and logical arithmetic circuits. Further, according to the present invention, since partial products are added in a pipeline format, the addition can be performed in synchronization with a high-speed clock.

[Brief description of the drawings]

1A and 1B are block diagrams of a configuration referred to in the description of the present invention, FIG. 2 is a timing chart of the reference configuration, FIG. 3 is a block diagram showing a schematic configuration of the reference configuration, 4 is a block diagram of one embodiment of the present invention, FIG. 5 is a timing chart of one embodiment, FIG. 6 is a block diagram showing a schematic configuration of one embodiment, and FIG. 7 is a modification of one embodiment. FIG. 8 is a block diagram schematically showing an example of a conventional bit-serial adder, FIG. 9 is a timing chart of the bit-serial adder, and FIG. 10 is a conventional serial-parallel digital multiplier. FIG. 11 is a timing chart of a conventional digital multiplier. Description of main symbols in drawings 1A, 1B, 20A, 20B: shift register, 6A, 6B, ..., 6H: second-order booth decoder, 17A, 17B, 18, 19: for tree addition of partial products Adders 27A, 27B, 27C, 27D: adders for performing a process of adding “1” to the LSB for polarity reversal and a process of pipeline adding a partial product.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 7/52 310 H03H 17/00 601 H03H 17/02 655 H03H 17/02 661

Claims (1)

(57) [Claims] 1. A multiplicand is sequentially given, a control signal formed by supplying a multiplier to an encoder of a secondary booth is supplied, and a plurality of partial products are generated in units of 2 bits of the multiplier. A partial product generation circuit; and a plurality of adders each having a unit of 2 bits to which an output of the partial product generation circuit is supplied, and including an adder configured in a pipeline format. A digital arithmetic circuit which obtains a multiplied output by adding partial products of