JP2001005642A - Multiplier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiplier capable of executing high speed operation with a comparatively simple configuration. SOLUTION: This multiplier is such one that finds the multiplied result U=X×Y of a multiplicand X encoded by an i-notation method and a multiplier Y. When the multiplier Y can be developed like Y=(...(((2S1±1)2S2±1)2S3±1)...)2Sm±1), it is noticed that U=X×Y can be expressed as U=(...(((X2S1±X)2S2±X)2S3±X)...)2Sm±X). Each of shifters 1 to m shifts a multiplicand X corresponding to each prescribed shift quantity, each of adders/subtractors 100 to (100+m-1) adds the multiplicand X to each of shifted results of corresponding shifters 1 to m and the adder/subtractor (100+m-1) of the m-th stage obtains the operation result of U=X×Y.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for multiplying digital data, and more particularly to a multiplier for multiplying digital data.

[0002]

2. Description of the Related Art Conventionally, as a digital data multiplication circuit, for example, a circuit called a ripple carry type parallel multiplier as shown in FIG. The ripple carry type parallel multiplier shown in FIG. 4 is an example of a circuit configuration for a 4 × 3 bit operation, and includes 12 unit multipliers U having basically the same circuit configuration.
It is configured using M. That is, the unit multiplying circuit UM is configured around a so-called full adder circuit FA as shown in FIG. The ripple carry type parallel multiplier having such a configuration requires n × m unit multiplier circuits UM when the multiplicand X has m bits and the multiplier Y has n bits. FIG.
In, the subscript consisting of two digits after the unit multiplier UM is a combination representing a row and a column. That is, the first digit represents a row, and the second digit represents a column. For example, UM21 means a unit multiplier circuit in the first row and the second column.

As another example of a digital data multiplying circuit, a series-parallel multiplier as shown in FIG. That is, this serial-parallel multiplier
The full adder circuit FA and the delay element DL are used as main components, and the multiplicand X is calculated in units of 1 bit and the multiplier Y is calculated in each full adder circuit FA. From the Y1 bit side to the Y4 bit side in time series. And the calculation result is transmitted to obtain a multiplication output Z.

[0004]

However, in any of the multipliers described above, the multiplication of the multiplicand X or the multiplier Y is performed in bit units, the operation result of each bit is propagated, and the final multiplication is performed. Since the configuration is such that the result is obtained, the calculation time tends to be longer as the number of bits increases. In particular, it is not suitable for a digital signal processing device that requires high speed, and the number of bits to be handled is There has been a problem that the circuit configuration becomes complicated and the price increases as the number increases.

The present invention has been made in view of the above situation, and provides a multiplier which has a relatively simple configuration and can perform high-speed operations. It is another object of the present invention to provide a multiplier suitable for integration into a circuit, which can be easily reduced in power consumption, increased in speed and reduced in size.

[0006]

The object of the present invention is achieved.
Therefore, the multiplier according to the present invention employs a
A multiplier for obtaining a multiplication result U = X × Y of the multiplier X and the multiplier Y
First, U = X, and the multiplier Y is i ^SDivisible by
It is determined whether or not the multiplier Y is i ^SA place divisible by
If so, shift U by S bits to the most significant bit side
Then, the shift result is set as a new U and Y / i
^SIs a new Y, and the multiplier Y is i ^SDivisible by
If not, subtract the number j smaller than i from the multiplier Y
(Y−j) or the multiplier Y and the above j (Y +
After j) is newly set to Y, this new multiplier Y is i ^SDivided by
If it runs out, the U is shifted to the most significant bit side by the S bit.
And X × j is added to or subtracted from the shift result.
The calculated value is defined as a new U, and Y / i is calculated. ^SA new
And the multiplier Y is i ^SIf divisible by
The multiplier Y is i ^SThe processing when it is not divisible by
Repeat while decreasing sequentially, Y becomes smaller than i
U at the point of time as a result of multiplication of the multiplicand X and the multiplier Y
It is configured to output.

[0007] The multiplier having such a configuration is, for example, a multiplicand X
And the multiplier Y are both represented by binary numbers
And the multiplier Y is Y = (... (((2 ^S1± 1) 2 ^S2±
1) 2 ^S3± 1) ・ ・ ・ 2 ^SmWith the development like ± 1)
If it is possible, U = X × Y = (... (((X2 ^S1±
X) 2 ^S2± X) 2 ^S3± X) ... 2 ^Sm± X) and
X shift and addition / subtraction processing for the shift result
Paying attention to the fact that
Is configured to perform such processing.
Therefore, it is possible to simplify the configuration and improve the calculation speed.
It becomes.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The members, arrangements, and the like described below do not limit the present invention, and can be variously modified within the scope of the present invention. First, a first example of the circuit configuration will be described with reference to FIG.
This will be described with reference to FIG. The multiplier M1 in the first circuit configuration example includes m first to m-th shifters 1 to m and m first to m-th addition / subtraction circuits 100 to (100 + m−
1), the first shifter 1 and the first addition / subtraction circuit 100 constitute a first stage, and the second shifter and the second addition / subtraction circuit 101 constitute a second stage. Hereinafter, similarly, the n-th (n <m) shifter and the n-th addition / subtraction circuit form the n-th stage.

Each of the first to m-th shifters 1 to m basically has the same circuit configuration, and is configured such that input data is shifted by an external shift signal. It has a well-known and well-known circuit configuration. In the embodiment of the present invention, the multiplicand X is n
Bits, the first to m-th shifters 1 to m
, The multiplicand X is input in parallel, and shift signals s1, s2... Sm corresponding to the shift amounts S1, S2.
The first to m-th shifters 1 to m transmit MSBs (Most Signifi? Ers) according to the shift signals s1, s2,.
to the cant Bit) side, input data X1, X2,.
, Xm are shifted.
Then, if the shift result is the first shifter 1,
If the first adder / subtractor 100 is the second shifter 2,
The signals are input to the corresponding addition / subtraction circuits, such as to the second addition / subtraction circuit 101.

The first to m-th addition / subtraction circuits 100 to (10
0 + m-1) are the corresponding first to m-th shifters 1 to m
And performs an addition operation on the shift result input from and the multiplicand X, and has a known / well-known circuit configuration. Then, the first to (m-1) th addition / subtraction circuits 100
The calculation results of .about. (100 + m-2) are configured to be input to the next-stage shifter.

Next, the principle of the multiplication by the multiplier M1 will be described.
explain about. First, let the multiplicand be X and the multiplier be Y
And both are binary numbers. For example, if the multiplier Y is Y =
(... (((2 ^S1± 1) 2 ^S2± 1) 2 ^S3± 1)
...) 2 ^SmIt can be expanded as ± 1)
(This equation is referred to as Equation 1). In this case, U = X × Y
= (... (((X2 ^S1± X) 2 ^S2± X) 2 ^S3±
X) ... 2 ^Sm± X)
Equation 2). In this equation 2, the innermost group
The term (X2 ^S1± X)
Is 2 for the multiplicand X ^S1Multiplied by the result of multiplying by
The number X is added or subtracted. Here, the multiplicand X
To 2 ^S1Is multiplied by the multiplicand X
To MSB (Most Significant Bit) side by S1 bit
There is nothing to shift. (X2 ^S1± X) operation
Assuming that the result is U1, this is the term enclosed in parentheses:
((X2 ^S1± X) 2 ^S2± X) is U1 × 2 ^S2± X
This is also processed in the same way as the first operation described above.
Can be. That is, U1 is shifted by S2 bits on the MSB side.
Add (or subtract) the multiplicand X to the result of shifting
Just do it. After all, in the case of Equation 2, the shift and addition / subtraction processing
Is repeated m times to obtain an X × Y operation result.
Wear. In other words, a combination of a shifter and an addition / subtraction circuit
To form a multiplier by combining m stages in tandem,
The above-described shift and addition / subtraction are repeated m times and U = X ×
Y can be obtained. Multiplication shown in FIG.
The device M1 is configured based on the above-described viewpoint.
is there.

Next, the value of the exponent part of 2 when expressing the multiplier Y as in Equation 1, in other words, the shift amounts S1, S2,.
, Sm will be described with reference to FIG. When the process is started, first, the operation parameters m,
The values of S and D are both set to an initial value of zero (see step 100 in FIG. 2). Next, it is determined whether or not Y is 1 (see step 102 in FIG. 2), and when it is determined that Y is “1” (in the case of NO), a series of processing is terminated without any processing. On the other hand, if it is determined to be “1” (in the case of YES), step 10
Then, it is determined whether Y is an even number or not. When it is determined that Y is an even number (in the case of YES), the process proceeds to step 106, where the value of the calculation parameter S, that is, the shift amount S is set to “1” to the value of S immediately before executing step 106. "Is added to the value. Further, in step 106, the value of Y is updated to a value obtained by dividing Y immediately before the execution of step 106 by 2, and thereafter, the process returns to the previous step 102 to repeat a series of processing. That is, as long as Y is an even number, steps 102, 104, and 106 are repeated, and shift amounts S1, S2,... Are obtained.

On the other hand, when it is determined in step 104 that Y is not an even number (in the case of NO), the process proceeds to step 108, where the calculation parameters m,
Each value of D and S is output as the first result, and is stored in a predetermined storage device (not shown) or the like as necessary. Next, the process proceeds to step 110, where the value of the operation parameter m is updated to a value obtained by adding “1” to the value immediately before execution of step 110, and the value of Y is changed to “1” immediately before execution of step 110. Is added to the value.

Then, it is determined whether or not the value of Y is a multiple of "4" (see step 112 in FIG. 2). If the value of Y is a multiple of 4 (in the case of YES), the routine proceeds to step 114, where the operation parameter D is set to “−1”, and the calculation parameter S is updated to a value obtained by adding “2” to the value immediately before execution of step 114. Further, when the value of Y is
The value immediately before the execution of step 114 is updated to a value obtained by dividing the value by “4”, and thereafter, the process returns to step 102.

On the other hand, if it is determined in step 112 that the value of Y is not a multiple of 4 (in the case of NO), the process proceeds to step 116, where the value of Y is set in step 1
The value is updated to a value obtained by subtracting “2” from the value immediately before the execution of No. 16. Next, in step 118, the value of the operation parameter D is set to “1”, and the value of the operation parameter S is updated to a value obtained by adding “2” to the value immediately before execution of this step 118. Y is updated to a value obtained by dividing the value immediately before execution of step 118 by “4”, and the process returns to step 102.

Here, the meaning of the processing of steps 110 to 118 will be described. First, Y when the processing after step 110 is performed is an odd number. Therefore, in order to take the form of 2 n, it is necessary to add “1” to an odd number or subtract “1” from an odd number to obtain an even number. In addition, any of the values before and after the odd number is a multiple of 2,
Utilizing the property of the number that the other is a multiple of 4, by adding “1” or subtracting “1” so that the odd Y becomes a multiple of 4, the Y becomes a multiple of 4. Where
Steps S110 to S118 update step S by "2". For example, assuming that Y = 5 just before the execution of step 110 for easy understanding, in step 110, Y = 5
5 + 1 = 6. This is not a multiple of 4, so
The process proceeds to step 116, where Y = 6-2 = 4 and Y
Will be updated. That is, this step 11
The process 6 corresponds to subtracting “1” from the value of Y immediately before the execution of step 110. Since Y becomes a multiple of 4, the shift amount is updated in step 118, and Y is divided by 4. Immediately before the execution of step 110, if Y = 7, Y = 8, which is a multiple of 4 in the processing of step 110, the process proceeds to step 114 to update the shift amount and divide Y. ing.

The operation parameter D is calculated in step 11
This is for discriminating between the case where “1” is added to the value of Y immediately before the execution of 0 and becomes a multiple of 4 and the case where it is not. In this example, the multiple of 4 is obtained by adding “1”. D if
= -1 and D =
In this manner, the above-described processing is repeated until the value of Y becomes "1", and the shift amounts S1, S
2,..., Sm are obtained. Note that the above-described processing can be realized, for example, by causing a microcomputer to execute software according to the procedure shown in FIG. 2, in which case, the obtained shift amounts S1, S2,. , Sm together with the multiplicand X is preferably input from the microcomputer to the multiplier M1 shown in FIG.

Next, the operation of the multiplier M1 will be described with reference to FIG. First, it is assumed that the multiplicand X has n bits, its MSB is X1, and the LSB (Least S
It is assumed that the numerical values of the subscripts of X are represented in ascending order as going toward the “significant bit”, and the LSB is represented by Xn. When the multiplicand X is input to the first shifter 1 in parallel and the shift amount S1 determined in advance as described above with reference to FIG. 2 is input, the multiplicand X is shifted to the shift amount S1. Is shifted to the MSB side, and the shift result is output in parallel to the first addition / subtraction circuit 100. In the first addition / subtraction circuit 100, an addition operation of the multiplicand X input in parallel and the data input from the first shifter 1 is performed, and the operation result is input in parallel to the second shifter 2. Becomes

In the second shifter 2, when data is input from the first adder / subtractor circuit 100, a shift amount S2 is input, and a shift corresponding to S2 is performed by the first shifter 1 previously.
Is performed on the data input from the first addition / subtraction circuit 100 in the same manner as described above.
1 is input in parallel. The second addition / subtraction circuit 101 performs an addition operation on the data input from the second shifter 2 and the multiplicand X input in parallel to the second addition / subtraction circuit 101. The data is input to a third shifter (not shown) in parallel. Hereinafter, similarly, the data shift and the addition operation are performed, and the result is repeatedly input to the next stage. At the m-th stage of the final stage, the m-th addition / subtraction cycle (100 + m−1) is performed. ), U which is the result of X × Y operation is obtained as parallel data.

Next, the multiplicand X is multiplied by 100 (decimal number).
Taking the case where the number Y = 151 (decimal number) as an example, the multiplier M
The configuration and operation of No. 1 will be described more specifically. Ma
If Y = 151, Y = (((2 ³+1) × 2 ²+
1) × 2 + 1) 2 + 1. Accordingly
In this case, the multiplier M1 should have a four-stage configuration.
Becomes Then, in the first stage, that is, in the first shift
In data 1, the multiplicand X has three bits to the left, ie, M
A shift of 3 bits toward the SB side
Become. X = 100 means that in a binary number, X = (110010)
0) ₂After the shift of 3 bits, (11
00100000) ₂Becomes Therefore, the multiplicand X and
Addition of (110000000000) ₂+ (11001
00) ₂= (110000100) ₂Becomes

Next, in the second shifter 2, (11
10,000100) ₂Is shifted two bits to the left,
(111000010000) ₂And this has a second
In the addition / subtraction circuit 101, the multiplicand X = (110010)
0) ₂Is added, and (11100001000000) ₂+
(1100100) ₂= (11001110100) ₂
Becomes Next, in a third shifter (not shown),
(11001110100) ₂Is shifted one bit to the left
(110011101000) ₂And the third
In an addition / subtraction circuit (not shown), the multiplicand X is added to this.
Is calculated as (110011101000) ₂+ (110
0100) ₂= (1111000010001100) ₂Tona
You. Finally, the m-th shifter in this case, ie, the fourth
In the shifter 4, (1111000010001100)
₂Is shifted left by one bit (1111000010001).
1000) ₂And the m-th addition / subtraction circuit, that is, the fourth
In the addition / subtraction circuit 103, the multiplicand X is added thereto.
And (11110000100011000) ₂+ (1100
100) ₂= (1110101111100) ₂Tona
You. (1110101111100) ₂Is a decimal number
Back to 15100, which is X = 100 and Y =
151 and the result of the multiplication by the multiplier M1
It can be confirmed that X × Y is required.

Next, the multiplier M in the second circuit configuration example
2 will be described with reference to FIG. This multiplier M
2 is a configuration in which a set of a shifter and an addition / subtraction circuit are provided in a so-called cascade connection, corresponding to the number of shift processes in the multiplier M1. It is configured so that it can be repeatedly used. That is, the multiplier M2 includes an input selector 200 and a delay element 202 in addition to the set of the shifter 1 and the addition / subtraction circuit 100. The shifter 1 and the addition / subtraction circuit 100 are basically the same as the first to m-th shifters 1 to m and the first to m-th addition / subtraction circuits 100 to (100 + m-1) shown in FIG. Therefore, the detailed description here is omitted.

The input selector 200 can receive the multiplicand X and the output data of the addition / subtraction circuit 100 via the delay element 202 in parallel, respectively.
One of the multiplicand X and the output data of the addition / subtraction circuit 100 via the delay element 202 is selectively transmitted to the shifter 1 in response to the control signal So (for example, in response to switching between the logical value High and the logical value Low). It is output.

To the shifter 1, shift signals S1 to Sm corresponding to the shift amount are sequentially input.
In accordance with the shift signal, the data input by the input selector 200 is shifted and output to the addition / subtraction circuit 100. The addition / subtraction circuit 100 adds the multiplicand X to the parallel data input from the shifter 1 and outputs the result. The parallel output data is returned to the input selector 200 via the delay element 202. Has become. Here, the delay element 202 is set to a delay time sufficiently larger than the operation time in the shifter 1 and the addition / subtraction circuit 100. Such a delay element 202 can be realized by, for example, a logic element driven by input of a clock such as a latch or a shift register. Therefore, by appropriately setting the input timing of the control signal So in the input selector 200, the shifter 1 and the addition / subtraction circuit 100
Can be fed back with good timing, and the feedback result can be shifted and added again. As shown in FIG. Is configured to be equivalent to the above configuration.

Next, the operation of the multiplier M2 in the above configuration will be described. First, when the multiplicand X is selected by the input selector 200 and output to the shifter 1,
A shift signal (shift amount) S1 is input to the shifter 1 from the outside, and the multiplicand X is subjected to a shift corresponding to S1 and then output in parallel to the addition / subtraction circuit 100. Here, the shift of the multiplicand X is performed toward the MSB side as in the circuit example of FIG. In the addition / subtraction circuit 100, the multiplicand X is added to the parallel data from the shifter 1 and output, and the operation output is supplied to the input selector 2 via the delay element 202.
00 will be returned.

In the input selector 200, the control signal So is switched to an appropriate signal level, whereby the output of the addition / subtraction circuit 100 via the delay element 202 is selected and input to the shifter 1. . The shifter 1 receives the shift signal S2, shifts the parallel data input from the input selector 200 according to the shift signal, and outputs the parallel data to the addition / subtraction circuit 100 in parallel. In the addition / subtraction circuit 100, an addition operation of the parallel data input from the shifter 1 and the multiplicand X is performed, and the operation result is returned to the input selector 200 again via the delay element 202 and selected. The same operation as described above is repeated. Then, the shift signal Sm is input to the shifter 1, and the result of adding the multiplicand X to the shift result in the addition / subtraction circuit 100 becomes the final operation output.

In the embodiment of the invention described above,
Is used when both the multiplicand X and the multiplier Y are binary numbers.
As described above, the multiplicand X and the multiplier Y are both different bases.
Needless to say, the present invention is also applied to the case where it can be expressed. example
For example, the multiplicand X and the multiplier Y are both expressed in i-ary.
If so, the equation for U corresponding to equation 2 above is
U = (... (((Xi ^S1± X · j) i ^S2± X
j) i ^S3± X ・ j) ・ ・ ・ i ^Sm± X)
(I> j). Therefore, X
Processing to add or subtract X · j of the shift for
Kiko that can get U by repeating
And

When the above-described multiplier is used in, for example, a digital filter, if the coefficients of the digital filter are made to correspond to multipliers, the shift amount of each stage is fixed. This is unnecessary, and the hardware is simplified.

[0029]

As described above, according to the present invention,
Since the multiplication can be processed by shift and addition / subtraction, for example, when the multiplier Y is n bits, the multiplication result can be obtained by the operation of (n-1) at the maximum, and the average is approximately (n) This requires only about -1) / 2 of the amount of calculation, which is advantageous in that the circuit can be simplified as compared with the related art, and that the speed of the calculation processing can be increased. Further, according to the present invention, hardware can be reduced by efficient and regular degeneration, so that, especially when implemented by an integrated circuit, low power consumption and high speed can be achieved, and miniaturization is facilitated. It has the effect of becoming.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a first circuit configuration example of a multiplier according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a procedure for obtaining a shift amount of a multiplicand X by a multiplier according to the embodiment of the present invention.

FIG. 3 is a configuration diagram illustrating a second circuit configuration example of the multiplier according to the embodiment of the present invention;

FIG. 4 is a configuration diagram showing an example of a circuit configuration of a conventional multiplier.

FIG. 5 is a configuration diagram showing a configuration of a unit multiplication circuit in the circuit shown in FIG. 4;

FIG. 6 is a configuration diagram showing another example of a circuit configuration of a conventional multiplier.

[Explanation of symbols]

 1-m shifter 100- (100 + m-1) addition / subtraction circuit 200 input selector 202 delay element

Claims (3)

[Claims] 1. A multiplicand X and a multiplier Y encoded in an i-ary system
Is a multiplier for obtaining a multiplication result U = X × Y of the following equation. First, U = X, and the multiplier Y is i ^SIs divisible by
And the multiplier Y is i ^SIf it is divisible by
S-bit shifted to the most significant bit side, and the shift result
As a new U and Y / i ^SIs a new Y
The multiplier Y is i ^SIf it is not divisible by, the multiplier Y
(Y-j) or multiplier obtained by subtracting a number j smaller than i from
After adding the above j to Y and (Y + j) is newly set as Y,
This new multiplier Y is i ^SIf divisible by
Is shifted S bits to the most significant bit side, and the shift
A result obtained by adding or subtracting X × j to the result is defined as a new U.
And Y / i ^SIs a new Y, and the multiplier Y is i ^SAnd the multiplier Y is
i ^SThe processing when it is not divisible by is subtracted from the above S in order.
And when Y becomes smaller than i
Is output as the result of multiplication of the multiplicand X and the multiplier Y
A multiplier configured as described above. 2. A multiplication result of the multiplicand X and the multiplier Y is calculated.
A parallel data input, and a predetermined input externally input.
Shifts the parallel data in response to the shift signal of
A shifter for applying and outputting, and adding or subtracting the multiplicand X to or from output data of the shifter.
And an adder / subtractor circuit that outputs the result as a set, and the add / subtract is performed in accordance with the number m of stages determined under predetermined conditions.
A pair of the next stage shifter and addition / subtraction circuit is connected to the output side of the arithmetic circuit.
The set of the shifter and the addition / subtraction circuit is set to m
The multipliers are configured by being connected in cascade, and the shift signal input to the shifter of each stage is
It is based on the shift amount determined for each stage.
The shift amount of each stage is obtained by encoding the multiplicand X and the multiplier Y in the i-ary system.
In some cases, the multiplier Y is Y = (... (((2 ^S1± 1) 2 ^S2±
1) 2 ^S3± 1) ・ ・ ・ 2 ^Sm± 1)
, The value of each exponent of 2 in the formula
And the value of the exponent of 2 in the innermost parenthesis in the expression
Starting with the first shifter
Is assigned as the shift amount of each shifter
The number m of stages is an exponent of 2 obtained as the shift amount.
A multiplier corresponding to the number of. 3. A multiplication result of the multiplicand X and the multiplier Y is calculated.
Multiplier that can input two sets of parallel data and
The two sets of parallel data are
An input selector for selecting and outputting one of the two, and parallel data from the input selector being input,
According to a predetermined shift signal sequentially input from the outside,
Shifter that shifts and outputs parallel data
With respect to the parallel data output from the shifter,
Adds or subtracts number X and outputs the result in parallel
And a predetermined delay with respect to the parallel output data of the addition / subtraction circuit.
The output stage delays the output and outputs the same.
A delay element connected to one input stage of the
The input selector includes the multiplicand X in the other input stage.
The multiplicand X is selected and output in parallel.
After the control signal is input, the delay element
These parallel data are selected and output (m-1) times
While the control signal is applied, a new parallel data is input from the input selector to the shifter.
Each time a data entry is made,
The shift signal corresponding to the shifted amount
The respective shift amounts are obtained by encoding the multiplicand X and the multiplier Y in the i-ary system.
In some cases, the multiplier Y is Y = (... (((2 ^S1± 1) 2 ^S2±
1) 2 ^S3± 1) ・ ・ ・ 2 ^Sm± 1)
, The value of each exponent of 2 in the formula
And the value of the exponent of 2 in the innermost parenthesis in the expression
Is assigned as each shift amount starting with
M is the number of exponents of 2 obtained as the shift amount.
The m-th output from the addition / subtraction circuit is multiplied by the multiplicand X.
A multiplier obtained as a result of multiplication with the number Y.