JP2864598B2 - Digital arithmetic circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital operation circuit applicable to a product-sum operation such as a digital filter.

[Summary of the Invention]

The present invention relates to a digital operation circuit applicable to a filter operation for multiplying input data by a coefficient, wherein input data can be loaded in a bit-parallel manner, and input data having a bit shift amount selected from a plurality of shift amounts is provided. , A selector for multiplying the output of the shift register by a power of 2 and generating a positive or negative output of the shift register, and an output of the selector supplied, divided into a carry and a sum. An accumulator for accumulating the output of the selector, and a circuit for generating a control signal for the shift register and the selector in accordance with a program for generating a partial product, capable of reducing the number of steps required for multiplication processing It is.

[Conventional technology]

As shown in FIG. 7, an n-tap, for example, 4-tap FIR digital filter has an input sequence x _i , an output sequence y _i , and an impulse response (coefficient) h ₀ to h _n−1 , as shown in FIG. The following calculation is performed. In FIG. 7, the data extracted from the tap of the shift register unit composed of four unit delay elements is supplied to the multiplier, where the coefficients h ₀ , h ₁ ,
h ₂ and h ₃ are multiplied. The outputs of the multipliers are added by an addition tree, and output data y _i is obtained.

For applications such as modulation for audio signals and modems,
Since the data rate is low, the above-described filter operation is realized using a program control configuration called a DSP (Digital Signal Processor). DSPs can have hardware multipliers or complicate internal buses to efficiently repeat product-sum operations. FIG. 8 shows a DSP applicable to the filter operation.

In FIG. 8, 31 is a multiplier, 32 is an adder / subtractor, and 33 is a register. The output of the register 33 is fed back to the adder / subtractor 32 to form a cumulative adder. 34 is a data memory for storing input data, 35 is an address generation circuit for the data memory 34, 36 is a coefficient memory for storing coefficients, and 37 is a coefficient memory.
36 address generation circuits. Further, the multiplier 31, the adder / subtractor 32, the register 33 and the like are controlled by a control signal from the register 38. An address from the sequencer indicated by 39 is supplied to the microprogram memory 40, and a control signal is read from the microprogram memory 40 and taken into the register 38.

When performing the same operation as the digital filter of FIG. 7 by the configuration shown in FIG. 8, each time a new input data x _i arrives, the address generating circuit 35, the last four cycles (4 means a clock period) Of four data x _i , x _i-1 ,
Generate an address where x _i-2 and x _i-3 are stored. The address generation circuit 37 generates an address in which h ₀ , h ₁ , h ₂ , and h ₃ are stored in four cycles. The multiplier 31 multiplies the data and the coefficients read from the data memory 34 and the coefficient memory 36 in four cycles, and outputs h ₀ x _i , h ₁ x _i-1 , h ₂ x _i-2 ,
Generates a multiplied output of h ₃ x _i-3 sequentially. The sum of these multiplied outputs is generated by an adder / subtracter 32, a register 33, and a cumulative adder including a feedback path, and output data _yi is obtained.

[Problems to be solved by the invention]

The above-mentioned DSP has advantages in that the number of gates is small and the circuit scale is small. However, there is a problem that cannot be applied to processing of video data having a data rate much higher than that of audio data. That is, the multiplier 31 and the adder / subtractor
For 32 speed of about the same as the data rate, from coming input data x _i is until arrival of the next input data x _{i + 1,} we do not have enough time to perform several steps of the program. For example, in the case of an n-tap FIR filter, n-step processing was required.

Accordingly, an object of the present invention is to provide a digital signal processing circuit which can reduce the number of steps without deteriorating the advantages of a DSP and can be applied to processing of high-speed data such as video data.

[Means for solving the problem]

According to the present invention, a shift register (1, 2) which can load input data in a bit parallel manner and generates input data of a bit shift amount selected from a plurality of shift amounts, and a shift register (1, 2) And a selector (3, 4) for generating a positive or negative output of the output of the shift register (1, 2) and an output of the selector (3, 4). Accumulators (5, 6, 7) for accumulating the outputs of the selectors (3, 4) in a form divided into sums; and a shift register (1, 2) and a selector (1, 2) according to a program for generating a partial product. Means (12, 13, 14) for generating control signals for (3, 4).

[Action]

By selecting a coefficient with a small number of “1” bits or a coefficient with as few consecutive “0” s or “1s” as possible, that is, a coefficient that makes the partial product zero, that is, a multiplier that is smaller than when Booth's algorithm is used Thus, the number of steps can be reduced. Therefore,
The operation can be speeded up, and the circuit size can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is input data of n bits.
x _i is a shift register to which bits are input in parallel.
The input data x _i is, for example, a code with 2's complement.
Reference numeral 2 denotes a shift register for extending the word length by m bits in the upper direction. In the case of 2's complement code, MS
The word length can be expanded by adding m bits of B (most significant bit). The number m of bits to be extended corresponds to the word length of the coefficient. The shift registers 1 and 2 each have n and m unit circuits of one bit shown in FIG. 2 connected in series.

In FIG. 2, reference numeral 21 denotes a selector, and reference numeral 22 denotes a flip-flop to which the output of the selector 21 is supplied. The output of the flip-flop 22 is supplied to a subsequent unit circuit. Selector 21
Output ST1 of the previous stage (previous stage), output ST2 of the previous stage,
Output ST3 before stage, output ST4 before stage 4, flip-flop 22
Is supplied. The control signals S for the selectors of the respective unit circuits are commonly supplied to the shift registers 1 and 2. The selector 21 selects one input shifted leftward by an amount corresponding to the control signal S.

The shift register 1 can shift leftward (in the direction from the LSB to the MSB) as viewed in the drawing. Shift register 1 selects input data x _i for the first cycle, taking the flip-flop 22. This is the state of data loading. From the next cycle, the selector 21 selects data other than the input data. When the selector 21 selects the output ST1 one stage before, it is in the data shift state.
When the output ST2 of the previous stage is selected, shifting is performed by skipping one stage. When the selector 21 selects the output ST3 of the previous stage, shifting is performed by skipping two stages.
When 21 is to select the output ST4 four steps before, it is a state of shifting by skipping three steps. The shift register 2 is also the same shift processing as the shift register 1 is performed for the upper bits of the input data x _i. Therefore, the control signal S determines the number of shift stages and the timing of parallel loading. The reason why the shift registers 1 and 2 are configured in this way is to realize the necessary bit shift at the time of addition of the partial products.

Reference numerals 3 and 4 are booth selectors, respectively. (XX
Y) multiplication by the second order Booth algorithm,
A partial product is formed every two bits of the multiplier Y (specifically, a coefficient). In this case, looking at three consecutive bits of the multiplier Y,
Any one of 0 times, ± 1 times, and ± 2 times the multiplicand X is formed by the booth selectors 3 and 4, and the partial products are added to obtain a multiplied output.

P, Q, and R are control signals commonly supplied to the selectors 3 and 4. Usually, by supplying three consecutive bits of the multiplier Y to the booth decoder, the control signals P, Q,
R is formed. In the present invention, the control signals P, Q, and R are formed corresponding to the steps of the program required to multiply the known coefficients, as described later. Selector 3
And 4 are the unit paths shown in FIG. 3 connected in series for n bits and m bits. In FIG. 3, reference numeral 23 denotes a selector controlled by the control signal P, reference numeral 24 denotes an AND gate to which the output signal of the selector 23 and the control signal Q are supplied,
5 is an EX- to which the output of the AND gate 24 and the control signal R are supplied.
OR gate. The selector 23 is supplied with the outputs of the shift registers 1 and 2 as well as the input from the lower one bit.

When the selector 23 selects the input of the shift register 1 or 2 as it is, the selectors 3 and 4 of the Booth obtain 1-fold data as the output. When outputting the shifted data, double data is obtained. When the control signal P is "0", one-time data is obtained from the selector 23,
When this is "1", double data is obtained from the selector 23. The AND gate 24 is a prohibition gate for outputting 0 when the control signal Q is “0”. The EX-OR gate 25 inverts "0" and "1" when the control signal R is "1".

In the secondary booth decoder, the following control signals P, Q, and R are generated according to the three bits of the multiplier Y.

The booth selectors 3 and 4 control signals P,
A partial product is generated according to Q and R as follows.

The partial products of (n + m) bits formed every cycle by the selectors 3 and 4 of the booth are supplied to the accumulators 5 and 6, respectively. Similarly to the shift register 2, an l-bit accumulator 7 is provided for expanding the word length, and the MSB is supplied to the accumulator 7. By the accumulator 7,
When a large number of multiplication results of each tap are added, occurrence of overflow is prevented. The control signal R is supplied as a lower carry input of the accumulator 5. This is because when the EX-OR gate 25 inverts “0” and “1”, the control signal R of “1” is added to the LSB to realize the inversion of two's complement data.

The accumulators 5, 6, and 7 are composed of a full adder, a register to which the output of the full adder is supplied for each input bit, and a feedback path for feeding back the output of the register to the full adder as shown in FIG. Become. The accumulators 5, 6 and 7 perform the accumulation in the form of a redundant binary number in which the sum and the carry are different, so that a 1-bit input produces a 2-bit output of the sum and the carry.
The output of the sum of the outputs of a total of 2 (n + m + 1) bits of the accumulators 5, 6, and 7 is supplied to the shift register 8,
The output of the carry is supplied to the shift register 9.

The serial outputs of the shift registers 8 and 9 are supplied to the full adder 10 in order from the lower bit. The output of the full adder 10 is supplied to the flip-flop 11. The sum output of the flip-flop 11 is taken out, and the carry output is fed back to the full adder 10 as the input of the next upper bit. The full adder 10 has two outputs, that is, an addition output (sum) of three inputs (mod. 2) and a carry that is a logical product output of each two inputs.
Generate book output. Carry addition is performed by the accumulator including the full adder 10 and the flip-flop 11 in order from the lower bit, and a bit serial output is obtained. The flip-flop 11 receives each (n +) signal from the shift registers 8 and 9.
Cleared early in the accumulation of (m + 1) bits.

Each of the accumulators 5, 6, and 7 has a configuration similar to that of the accumulator including the full adder 10 and the flip-flop 11, provided for each 1-bit input. That is, as shown in FIG. 9, one bit of the outputs of the selectors 3 and 4 via the flip-flop is supplied as the first input of the full adder, and the carry output of the full adder is passed to the upper bits.
The sum is provided to the flip-flop, the carry from the lower bit is provided to the flip-flop, and two outputs are taken from these flip-flops,
The two outputs are fed back to the input side of the full adder. Since the accumulators 5, 6, and 7 perform addition of partial products in the form of two signals, that is, carry and sum, there is no carry propagation and high-speed addition processing can be performed.

The control circuit shown in FIG. 4 is provided in connection with the configuration of FIG. In FIG. 4, 12 is a control signal S, P, Q, R
Is an address generating circuit for the program memory 12, and 14 is a register for storing control signals S, P, Q, and R read from the memory 12. The control signals S, P, Q, R are
It depends on a known coefficient.

The memory 12 stores a control signal as shown in FIG. 5 as an example. As will be described later, the number of steps required to multiply the coefficient of each tap can be reduced as compared to using a secondary Booth algorithm. When the coefficient is 12 bits, it is always 6 for the second-order Booth algorithm.
Although steps are required, the present invention reduces the number of steps to five.
It can be reduced to the following. Figure 5 shows the case of a digital filter 4 taps, multiplier MPY1 coefficients h ₀ of the first tap is performed in four steps, multiplication MPY2 coefficients h ₁ of the second tap is performed in three steps, the third tap multiplication MPY3 coefficients h ₂ of is made in five steps, an example in which the fourth multiplication coefficient h ₃ of the tap MPY4 is made in three steps. Therefore, in total
Operations that required 24 steps can be performed in 15 steps. As shown in FIG. 5, if the use is limited to a digital filter, an address generation circuit
The counter 13 can be constituted by a counter for generating an address for repeating the number of steps (for example, 15) of the program.

The calculation processing of the above-described embodiment will be described in more detail with reference to FIG.

FIG. 6A shows that the number of bits having a coefficient of “1” is small (00001000
1000). As in the conventional case, when the secondary Booth algorithm is used, the calculation proceeds in six steps. In the first step, the control signal S is input (IN), ie, x _i
Is selected, and the control signals P, Q, and R are 0, so that the accumulators 5, 6, and 7 receive 0. The control signals P, Q, and R are 0 because the lower 2 bits of the coefficient are (00), and 0 is assumed as a bit lower than the least significant bit.
In order to see the three bits of

In the next step (cycle), the fourth, third, and second bits from the bottom of the coefficient are (100).
The control signal (P, Q, R) becomes (111). In this case, the control signal S for the shift registers 1 and 2 is such that the selector 21 selects the output ST2 two steps earlier (indicated simply by 2 in FIG. 6), that is, shifts two bits to the left. When the input is represented by X, (−2X · 2 ² ) is represented by selectors 3 and 4
Occurs. Therefore, since the initial value is 0 in the accumulators 5, 6, and 7, (−2 × 2 ² ) is stored.

In the next step, since the three bits of the coefficient are (001), the control signals (P, Q, R) are (010). Therefore, + X is formed. The control signal S is supplied to the selector
21 is intended to select a two-stage before the output ST2, 2 ^4-fold is made in conjunction with the shift left 2 bits of the previous step.
Accordingly, (X · 2 ⁴ ) is supplied to the accumulators 5, 6 and 7, and (−2X · 2 ² + X ·
²⁴ ) is formed.

Hereinafter, the same processing is performed for every two bits of the coefficient. Therefore, when the coefficient has 12 bits, the multiplication process is always completed by the 6-step process by the secondary Booth algorithm.

In FIG. 6A, a 3-step process not using the Booth algorithm is shown on the right side of the 6-step process. That is, this is a process in which attention is paid only to the bit where “1” is set in the coefficient, and the input + X bit-shifted according to the position is selected. Since the bit of “0” in the coefficient is a process of cumulatively adding 0, this process is omitted. Therefore, as shown in FIG. 6A, in the case of a coefficient having a small number of "1" bits, the number of steps can be reduced by not using the Booth algorithm.

FIG. 6B to FIG. 6F also show 2
Steps when using the next booth algorithm,
The improved processing steps are respectively shown.

FIG. 6B and FIG. 6C show coefficients of a pattern in which “0” or “1” continues. When “0” or “1” continues, the control signal (P, Q, R) becomes (000),
Booth selectors 3 and 4 select 0 output. By omitting the process of selecting the 0 data, the number of steps required for multiplication of the coefficients can be reduced.

However, the method of omitting the step of selecting 0 data is not very effective in the case of a pattern in which “0” and “1” appear alternately as shown in FIGS. 6D and 6E. . In the example of FIG. 6D, only one step is reduced, and in the example of FIG. 6E, the number of steps does not decrease.

Further, as shown in FIG. 6F, when the coefficient is a mixture of a pattern in which “1” and “0” appear alternately and a pattern in which “1” (or “0”) continues, two steps are reduced. it can. Generally, a coefficient having a pattern as shown in FIG. 6F in which “0” or “1” is consecutive in the upper bit or the lower bit is often used.

As can be seen from the specific example of FIG. 6, the pattern of the coefficient of the filter operation is such that the number of bits of “1” is reduced or “0” or “1” is continuous within the allowable range of the operation error. By selecting, the number of processing steps can be significantly reduced as compared to using Booth's algorithm. The reduction in the number of steps means that the efficiency of the arithmetic circuit is high, and brings about the advantages of high speed and small circuit size.

Note that the output of the accumulator is two of carry and sum.
The output form of the book may be used as it is. In addition, the present invention is not limited to the filter operation, and can be applied to operations such as FFT and cosine transform to obtain similar advantages.

〔The invention's effect〕

According to the present invention, the number of program steps required for multiplying coefficients can be reduced, and the partial products are added by the accumulator without carry propagation. It operates at a very high speed and can achieve a high-speed circuit. Therefore, the present invention can be applied to processing of digital image data. Further, according to the present invention, since the product-sum operation is performed under program control, the circuit scale can be reduced as compared with a configuration in which a plurality of multipliers and a plurality of addition trees are provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram showing the structure of one bit of a shift register, FIG. 3 is a block diagram showing one bit of a booth selector, and FIG. FIG. 5 is a block diagram of an example of a control circuit, FIG. 5 is a schematic diagram showing an example of a program memory, FIG. 6 is a schematic diagram used for explaining the operation of one embodiment of the present invention, and FIG. FIG. 8 is a block diagram of an example of a digital filter which can be applied, FIG. 8 is a block diagram of an example of a conventional digital operation circuit, and FIG. 9 is a block diagram showing one bit of a accumulator. Description of main reference numerals in the drawings 1, 2: shift register, 3, 4: Booth selector, 5, 6, 7: accumulator, 8, 9: shift register, 12: program memory.

Claims (1)

(57) [Claims] 1. A shift register which can load input data in parallel and generates the input data of the shift amount selected from a plurality of shift amounts, and multiplies an output of the shift register by a power of two. Along with
A selector for generating a positive or negative output of the shift register; an accumulator for receiving the output of the selector and accumulating the output of the selector in a form divided into carry and sum; and generating a partial product. Means for generating a control signal for the shift register and the selector according to a program for the digital operation circuit.