JPH04229323A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To reduce a gate scale and realize high-speed operation while widening functions and to prevent the circuit from becoming complex by extending and applying the algorithm of a secondary booth in 4-bit units, and skipping the arithmetic of partial products in a next arithmetic cycle when it is judged that the arithmetic is unnecessary and decreasing the number of arithmetic cycles, and thus generating the partial products efficiently. CONSTITUTION:The selector of a circuit block B1 is a 4-input selector, which can holds an output R(i) in addition to a data bit P1(i) with control signals SFT11 and SFT10, select and shift R(i-4) to the left by four bits, or select and shift R(i-8) to the left by eight bits; and the selector 35 of a circuit block BJ is a 4-input selector, which selects data of bits among the outputs R(i), R(i-1), R(i-2), and R(i-3) with control signals SFT21 and SFT20 and selects one of X1, X2, X4, and X8 partial products.

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic circuit, and particularly to an arithmetic circuit suitable for video signal processing. 2. Description of the Related Art Conventionally, parallel multiplier circuits have been used in arithmetic circuits that require high speed, such as product-sum arithmetic circuits. However, the multistage connection of full adders has a limited high speed due to the problem of carry propagation delay, or when a certain gate is performing a logical operation to determine the output, There was a problem in that the next stage of gates that were installed had idle time waiting for output. [0003] Therefore, in arithmetic circuits for real-time signal processing of images that require high-speed performance, a technique for dividing signals into bits and processing them in a time-division multiplexed manner is proposed, for example, in the patent application proposed by the applicant of the present application. Specification No. 1-284398,
It is disclosed in Japanese Patent Application No. 1-337319. [0004]Series-parallel multiplier circuits or pipeline multiplier circuits have been known for a long time, but these are basically bit-serial multiplier circuits and output the operation results in bit-serial format, so the multiplication results are accumulated one after another. The product-sum calculation circuit for addition requires the circuit configuration shown in FIG. 11 or 14. The product-sum calculation circuit shown in FIG. 11 will be explained below. In the configuration of FIG. 11, the bit length is B1.
The data of the multiplicand X, which is assumed to be , is supplied to the barrel shifter 102 via the register 101. On the other hand, the multiplier P2 is supplied to a decoder (not shown), and this decoder outputs the following control signals SFT,
A control signal MOD is formed. And the control signal SF
T is supplied to the barrel shifter 102 and the control signal MO
D is supplied to logic circuit 103. Barrel shifter 102 receives control signal SFT
This is a logic circuit that arithmetically shifts the multiplicand X by an arbitrary number of bits. As a result, the barrel shifter 102
The bit length B2 of the data output from the multiplicand X is assumed to be at least twice as long as the bit length B1 of the multiplicand X. Then, data of bit length B2 is supplied from this barrel shifter 102 to a logic circuit 103. A specific configuration of this barrel shifter 102 is shown in FIG. The barrel shifter 102 shown in FIG. 12 has a configuration for one bit, and a barrel shifter 102 having a similar configuration is provided for a bit length B2. In other words, the multiplicand X of bit length B1 for one bit of barrel shifter 102 is
2 are commonly connected to all. This barrel shifter 102 has (a1+
B1+a2) bit data is supplied to this barrel shifter 102, (a1+B1+
a2) The above control signal SFT is selected from among the bit data.
Based on , 1 bit data is selected and logic circuit 1
03 is supplied. Therefore, this barrel shifter 102
functions as a selector. The above data a1 is the bit length B of the multiplicand
1 is extended, and the sign bit of the MSB of the multiplicand X is extended and shifted to the left to create upper bits for reducing data. Furthermore, data a2 is input with "0" and shifted to the right to create lower bits for increasing the data. The logic circuit 103 is, for example, a partial product generation circuit for implementing Booth's algorithm, and is controlled by a control signal MOD. Logic circuit 103 as one of this logic circuit 103
1 is shown in FIG. 13, also as another example logic circuit 1
032 is shown in FIG. In the logic circuit 1031 shown in FIG. 13, if the multiplier P2 is simply multiplied one bit at a time starting from the LSB side, each logic circuit
031 is the AND gate 104 as shown in FIG.
You can use However, when generating partial products based on the quadratic Booth algorithm for every 2 bits sequentially from the LSB side of the multiplier P2, as shown in Fig.
A circuit configuration as shown in 4 is required. In addition, 105
is the terminal, and X(i) is the data of the i-th bit in the multiplicand X. The logic circuit 1032 shown in FIG. 14 shows a configuration for one bit, and a similar configuration is used for M
A bit length of B2 is provided from SB to LSB. In this logic circuit 1032, the i-th data bit X(i) in the multiplicand X is connected to the terminal 106.
via the selector 107 and the upper bits (not shown).
That is, it is supplied to the selector of the (i+1)th bit circuit. Further, a data bit X(i-1) supplied from a lower bit (not shown), that is, the (i-1)th bit circuit, is supplied to the selector 107 via the terminal 108. In the selector 107, the control signal MOD
data bits X(i) to logic circuit 1032 based on
Alternatively, either data bit X(i-1) is selected. In this case, selecting data bit X(i) means passing it through; data bit X(i)
-1) will shift left by 1 bit and multiply by 2. And exclusive or gate 1
At step 08, the output from the selector 107 is passed through as is or is inverted, and finally the AND gate 109 selects whether the output from the exclusive OR gate 108 is passed through as is or is set to "zero". In addition, when the output from the selector 107 is inverted in the exclusive OR gate 108 described above, the logic circuit 10
By applying "1" to the LSB carry input of the adder circuit 111 arranged next to 32, the sign of the numerical value is inverted instead of simply inverting the binary number. The generated partial product is supplied by the logic circuit 103 to the addition circuit 111. Addition circuit 111 and register 112
The partial products are accumulated by . Addition circuit 111
Then, the sequentially supplied partial products are stored in the register 112.
The summation value SUM fed back from the SUM is added to the cumulative addition value fed back from the SUM, and the summation output SUM is supplied to the register 112. In the register 112, the adder circuit 111
The addition value supplied from the addition circuit 111 is held as an addition output SUM and is fed back to the addition circuit 111. Note that this register 112 clears the contents of the register 112 with a clear signal CL when storing the first partial product of the multiplicand The above-mentioned addition output SUM is supplied to the circuit. in this way,
The product-sum operation circuit shown in FIG. 11 takes time equal to the number of cycles corresponding to the word length of the multiplier P2. Next, the product-sum operation circuit shown in FIG. 15 will be explained. Note that in FIG. 15, parts common to the configuration shown in FIG. 11 are denoted by the same reference numerals, and redundant explanation will be omitted. In the configuration of FIG. 15, the bit length is B1.
Data of the multiplicand X, which is assumed to be , is supplied to the selector 121. Also, this selector 121 has register 1
22, data whose bit length is B2 bits is fed back. On the other hand, the multiplier P2 is supplied to a decoder (not shown), and this decoder forms the control signal SFT and the control signal MOD shown below. Then, the control signal SFT is supplied to the selector 121, and the control signal MOD is supplied to the logic circuit 103. A specific configuration of this selector 121 is shown in FIG. Selector 121 shown in FIG.
has a configuration for one bit, and a selector 121 having a similar configuration is provided for a bit length B2. In other words, the bit length B for the selector 121 for 1 bit
2 data is fed back from the register 122 and is supplied, and this data with a bit length of B2 is commonly connected to all of the selectors 121. The above-mentioned selector 121 and register 122
It operates like a shift register. That is, in the first calculation cycle, the selector 121 in FIG. 16 selects the supplied multiplicand X and takes it into the register 122. At this time, selector 121 selects data bit X(i) in FIG. Then, in the next cycle, the selector 121 and the register 122 operate like a shift register in order to sequentially generate partial products from the LSB of the multiplier P2. In other words, if the multiplication shown in FIG. 13 is performed, the selector 121 for each bit shown in FIG. 16 shifts the data taken into the register 122 to the left by one bit. Selector 121
The output from the register of the (i-1)th bit lower than 1 bit is selected. Then, from the next operation cycle, the output of the register one bit lower than the bit selected in the previous operation cycle is selected. Furthermore, if multiplication as shown in FIG. 14 is performed, in order to shift the data loaded into the register 122 to the left by 2 bits, the selector 121 for each bit shown in FIG. Selects the output from the register 2 bits lower than the register. Then, from the next operation cycle, the output of the register 2 bits lower than the bit selected in the previous operation cycle is selected. register 1
22, the data of bit length B2 supplied from the selector 121 is held in the logic circuit 103 and fed back to the selector 121. The barrel shifter 102 as a selector shown in FIG. 12 and the selector 121 shown in FIG. 15 are multi-input selectors for the following reasons. For example, data with many “0” like [000010001000], [111000011110]
] In the case of data that has many consecutive "0"s or "1"s, the operation for generating partial products can be skipped and speeding up can be achieved. Bit shifting of arbitrary bits is required for such bit skipping. However, “0” and “1” like [101011010101]
It is not possible to skip calculations for data in which "" appears alternately. [Problem to be Solved by the Invention] In the above-mentioned conventional techniques, a multi-input selector is required in any case, so the number of gates is large. There was a problem that the number of bits increased, the circuit size increased, and the circuit became complicated.Also, since operations were performed on all bits without skipping unnecessary operations, it was not efficient. Therefore, an object of the present invention is to provide an arithmetic circuit that is more efficient in terms of the number of gates, the number of arithmetic cycles, etc. [Means for Solving the Problems] Claims The arithmetic circuit according to item 1 applies the quadratic Booth algorithm to the data in units of 4 bits in the arithmetic circuit that calculates the multiplication result of data consisting of a plurality of bits by forming partial products. , when the data is shifted in 4-bit units to generate partial products in 4-bit units in each calculation cycle, and by looking ahead at the data, it is determined that the partial product to be generated in the next calculation cycle will be zero. is configured to skip the calculation of the next partial product. The calculation circuit according to claim 2 includes a control signal generation circuit that forms various control signals, and a circuit component that processes each bit of data. , and an accumulator that accumulates the outputs of the circuit components, and the circuit component is configured to shift data from among a plurality of bit data or bit data for operation supplied from the lower bit circuit components and having a predetermined bit interval. a first selection means for selecting arbitrary bit data for defining the amount; one-bit data supplied from the first selection means; a second selection means for selecting arbitrary 1-bit data for specifying the shift amount of data from among the 1-bit data composed of the number of bits; and an addition output based on the output from the second selection means. an accumulator that forms a carry output and a carry output of the circuit component, supplies the carry output of the circuit component to the circuit component of the higher bit, and forms a carry output and an addition output from the circuit component of the lower bit as outputs of the circuit component; It selects and holds either the addition output and carry output supplied from the upper bit circuit component or the addition output and carry output supplied from the accumulator, and also transfers the held value to the lower bit circuit component. The configuration includes an output circuit that supplies the [Operation] The arithmetic circuit according to claim 1 applies the quadratic Booth algorithm in units of 4 bits to data consisting of a plurality of bits, and shifts the above-mentioned data in units of 4 bits. Partial products are generated in units of 4 bits in each calculation cycle. At this time, by looking ahead at the next data, if it is determined that the partial product of the calculation cycle will be zero, the calculation of the partial product in the next calculation cycle is skipped. In the arithmetic circuit according to claim 2, the amount of data shift required when applying the Booth algorithm in the first selection means of the circuit component is defined based on the control signal, and the amount of data corresponding to the shift amount is defined based on the control signal. Arbitrary bit data is selected by a selector. In the second selection means, the shift amount of data necessary to obtain the multiple specified by the Booth algorithm described above is defined based on the control signal, and arbitrary bit data corresponding to this shift amount is selected by the selector. be done. In the accumulator, partial products of the circuit component are accumulated based on the output from the second selection means, and an addition output and a carry output of the circuit component are formed. The output from each circuit component is
They are added in sequence to obtain a multiplication result. [Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 10. The arithmetic circuit shown in FIG. 1 consists of N circuit components S(N-1) to S(0
), a control signal generation circuit 10, and an accumulator 20. The control signal generation circuit 10 generates a control signal SFT
11, SFT10, SFT21, SFT20,
Control signals MOD-0, MOD-1, clock signal CLK
, clear signal CL, load signal LD, etc., and send these signals to each of the above-mentioned circuit components S(N
-1) to S(0) to control the circuit operation of each circuit component S(N-1) to S(0). Circuit components S(N-1) to S(
0) are provided in a number corresponding to the bit length B2 in FIG. 11 or FIG. 15 showing the prior art, that is, N (N=B2). Here, terminals AT(N-1) to AT(0
) is originally B1 shown in FIG. 11 or 15, so the data with bit length B2 described above is formed by sign-extending the MSB of bit length B1. ing. For example, circuit component S(N-1)
~Circuit component S(i) at S(0)
Looking at the circuit components of the lower bits, each 1-bit data R(i-1) to R(i-4)
, R(i-8) and 1-bit carry output CY(i-
1) are supplied, and each 1-bit data U(i+1) is supplied from the upper bit circuit component S(i+1).
and V(i+1) are supplied. In addition, the terminal AT (
i) Data bits X(i) are supplied via. Note that this data bit X(i) is the (i)th bit of the multiplicand
It means the data of the bit. The circuit component S(i) supplies a 1-bit carry output CY(i) and 1-bit data R(i) to the upper bit circuit component S(i+1), and 1-bit data U(i) and V(i) are each supplied to the lower bit circuit component S(i-1). In the configurations of FIGS. 1 and 2, the information in parentheses, for example, (i), (i
-1), (i-4), (i-8), etc. are “negative”
It is assumed that all of the following are connected to “zero (ground)”. Each circuit component S (N-1
) ~S(0) all have the same configuration, so
In the following description of circuit components, circuit component S(i) will be taken as an example. The accumulator 20 mainly includes a full adder 21 and flip-flops 22 and 23. The outputs U(0) and V(0) from the circuit component S(0) are added together with the carry output CY20 in the previous cycle in the full adder 21, and the addition output SUM2
0 and a carry output CY20 are formed. The carry output CY20 is sent to the full adder 2 via the flip-flop 22.
Further, the addition output SUM20 is sequentially taken out from the terminal 24 from the LSB side via the flip-flop 23. The structure of circuit component S(i) is shown in FIG. Circuit block BI indicated by a broken line corresponds to selector 121 and register 122 in FIG. 15, and circuit block BJ corresponds to selector 107 in FIG.
The circuit block BK corresponds to the exclusive OR gate 108 and the AND gate 109 in FIG. 14, and the circuit block BM corresponds to the adder circuit 111 and the register 112 in FIG. The data bit X(i) of the multiplicand X supplied via the terminal AT(i) is transferred to the flip-flop 31.
be taken into account. Flip-flop 31 corresponds to the i-th bit of register 122 shown in FIG. 15, and data bit X(i) is supplied from flip-flop 31 to selector 32 of circuit block BI. The selector 32 of the circuit block BI is a 4-input selector, and this selector 32 receives the above-mentioned data bit X(i) and the data R(i-4) and R( i-8) and data R(i) fed back from the flip-flop 33. The selector 32 also receives a control signal SFT1 from the control signal generation circuit 10.
1, SFT10 is supplied. In the selector 32, the above-mentioned control signal SFT
11, based on SFT10, data R(i-8)
, R(i-4), R(i), and X(i) is selected and supplied to the flip-flop 33. By this selector 32, in addition to data bit X(i),
Data R(i) can be held or data R(i-
4) It is possible to select data R(i-8) and shift it to the left by 4 bits, or to select data R(i-8) and shift it to the left by 8 bits. In addition, the above-mentioned control signals SFT11, SF
The selection based on T10 will be described later. Output R(i) from flip-flop 33
is supplied to other high-order bit circuit components, is supplied to the input side of the selector 35 of the circuit block BJ, and is further fed back to the input side of the selector 33 described above. In circuit block BJ, the second-order Booth algorithm is extended to 4 bits and applied.
Data R(i), R(i-1), R(i-2
), R(i-3), and the method of calculating the partial product can be selected from among 1x, 2x, 4x, and 8x. The selector 35 of the circuit block BJ is a four-input selector, and this selector 35 receives the data R(i) from the flip-flop 33 described above and the lower bit circuit components S(i-1) and S(i -2),
Data R(i-1) supplied from S(i-3),
R(i-2) and R(i-3) are supplied. Further, the selector 35 is supplied with control signals SFT21 and SFT20 from the control signal generation circuit 10. In the selector 35, the above-mentioned control signal SFT
21, based on SFT20, data R(i),
One of R(i-1), R(i-2), and R(i-3) is selected, and data R is sent to the flip-flop 36.
is supplied to circuit block BK via. Note that which data R is selected by the above-mentioned control signals SFT21 and SFT20 will be described later. In circuit block BK, NAND gate 41
, 42, or gate 43, FIG.
4 exclusive or gates 108 and AND gates 109 are configured. Data output from the flip-flop 36 described above is supplied to NAND gates 41 and 42. Further, the control signal MOD-0 is supplied to the NAND gate 41, and the control signal MOD-1 is supplied to the NAND gate 42, respectively. The outputs of the NAND gates 41 and 42 are then supplied to an OR gate 43, and the output of this OR gate 43 is supplied to the circuit block BL via a flip-flop 44. The following relationship exists between the combination of control signals MOD-0 and MOD-1 described above and the operation of circuit block BK. The circuit block BL is an accumulator, and the circuit block BL is a full adder 5.
1 and flip-flops 52 and 53. Prior to execution of the calculation, the control signal generation circuit 1
The contents of the flip-flops 52 and 53 are cleared by the clear signal CL supplied from 0. The full adder 51 receives the output from the flip-flop 44 of the circuit block BK, the output fed back from the above-mentioned flip-flop 53, and the circuit block B of the lower bit circuit component S(i-1).
A carry output CY(i-1) from K is supplied, and these values are added. In this full adder 51,
A carry output CY(i) and an addition output SUM(i) are formed. The carry output CY(i) is supplied to the flip-flop 52, and the addition output SUM(i) is supplied to the flip-flop 53. In the first calculation cycle, the contents of the flip-flops 52 and 53 are cleared, so in each calculation cycle, the addition output SUM(i) is fed back to the input side of the full adder 51 via the flip-flop 53. At the same time, the carry output CY(i) is supplied to the selector 56 of the circuit block BM, and the carry output CY(i) is sent to the upper bit circuit component S via the flip-flop 52.
(i+1) is supplied to the circuit block BL. on the other hand,
The carry output CY(i-1) supplied from the circuit component S(i-1) of the lower bit is the full adder 51
It is supplied to the input side of the circuit block BM, and also to the selector 57 of the circuit block BM. The output from the circuit block BL described above is a redundant binary number in which each bit is represented by two bits. [0048] The circuit block BM has selectors 56 and 57.
and flip-flops 58 and 59, and a load signal LD is supplied from the control signal generation circuit 10 to each selector 56 and 57. The selector 56 is supplied with the addition output SUM(i) and the output U(i) supplied from the circuit component S(i+1) of the upper bits, and the selector 57 is supplied with the output U(i) supplied from the circuit component S(i+1) of the lower bits. (i-
1) Carry output CY(i-1) supplied from
The outputs V(i) supplied from the circuit components S(i+1) of the upper bits are respectively supplied. When the product-sum result from circuit block BL is obtained, load signal LD is supplied to circuit block B.
M selectors 56 and 57 are switched, the addition output SUM(i) from the circuit block BL described above is loaded into the flip-flop 58, and the carry output CY(i) is loaded into the flip-flop 59. After that, the outputs U(i) and V(i)
is shifted from the MSB circuit component S(N-1) side to the LSB circuit component S(0) side at the timing of the clock signal CLK, and the above-mentioned accumulator 2
Cumulative addition is performed at 0. The shift output from this circuit requires the number of cycles equal to the output word length, but
This is the circuit blocks BI to BM required for one product-sum operation.
There is no problem as long as it is small compared to the number of cycles. By the way, in FIGS. 1 and 2, the noteworthy point is the selectors 32 and 35 of the circuit blocks BI and BJ.
It is. This is the selector 121 in FIG. 15 showing the prior art.
The circuit allocation for the operation skip is changed for the selector 107 in the logic circuit 103. In the product-sum calculation, if generation of partial products is not skipped, the circuit block BI may be as shown in FIG. 8. In FIG. 8, the selector 61 has a terminal A.
Data bits X(i) supplied via T(i)
and data R(i-1) or R(i-2) are supplied. In this case, use Booth's algorithm
Otherwise, it becomes just a shift register (shift input is output R(i-1)). Furthermore, if the second-order Booth algorithm is used, a two-bit shift is always performed, so the shift input in FIG. 8 is the output R(i-2). On the other hand, if the generation of partial products is to be skipped, the circuit block BI must be similar to the selector 121 in FIG. 16 showing the prior art. However, in such a configuration, a large number of gates are required for infrequent multi-bit skipping, resulting in a decrease in efficiency. Therefore, as shown in FIG. 9 or 10, a configuration may be considered in which the range in which skipping is possible is limited to a certain extent. Here, the configuration shown in FIG. 9 is designed to allow only 2-bit skipping on the premise that the second-order Booth algorithm is applied. In addition, FIG. 10 shows a selector 65 configured by combining the selector 107 of FIG. 13 showing the prior art, and data R(i-1)
It is possible to selectively skip within the range of ~R(i-6). However, these configurations still require multi-input selectors 63 and 65, and therefore are not very suitable because the loop for selecting data R(i-1) to R(i-6) takes time. do not have. On the other hand, the circuit blocks BI and BJ shown in FIG. 2 have uniform four-input selectors 32 and 35, respectively. Such small input selectors 32, 3
5 is preferable because it can be configured with a small number of gates and the feedback loop can be made faster. The fan-out of the flip-flop 33 of the circuit block BI that holds data R(i) is also kept small compared to other methods. Also, circuit block BJ
~BM is all feedforward except for the feedback loop in circuit block BL, and in such a feedforward circuit, it is possible to easily increase the speed by pipelining. In addition to the equalized circuit configuration, the pipelined circuit shown in FIG. 2 is capable of very high-speed operation. The control signal generating circuit 10 in FIG. 1 generates various control signals as described above, and a memory can be used as one means for realizing such functions. This is because the required calculation cycles differ depending on the value of the multiplier, and there are various combinations of partial integral decomposition methods for the multiplier, and the method with the minimum number of cycles should be searched for. from,
This is because it is appropriate not to perform such a process in real time, but to obtain a solution in advance and store only the time series of various control signals in a memory before generating them. Furthermore, if the multiplier cannot be determined in advance, or if there are too many multipliers to store in the memory, the control signal generating circuit 10 may be configured as shown in FIGS. 3 and 4, for example. will be used. The following explanation regarding FIGS. 3 and 4 is not only an explanation of the hardware, but also a description of the method of determining the time series of various control signals in advance when a memory is used in place of the controller as described above. An example is shown. In the configuration of FIG. 3, (N+1) circuit components T(N-1) from MSB to LSB
~T(0) are connected in cascade. The circuit block BI in FIG. 2 is used as the circuit components T(N-1) to T(0), and the control signal SF supplied to the circuit components T(N-1) to T(0) is
T11 and SFT10 are also common. This circuit component T(N-1) ~
Multiplier P2 is supplied to T(0) via terminals CT(N-1) to CT(0), and this circuit component T(N-1) to T(0) as a whole constitutes a shift register. However, the way of connection when constructing a shift register is different between FIG. 3 and FIG. In other words,
What was a left shift in FIG. 1 is a right shift in FIG. Further, N matches the input word length of the multiplier P2 and is different from B2. Note that the values in the parentheses of the data R(i-8) and R(i-4) supplied to the circuit block BI, for example, (i-8) and (i-4) are (N-1).
When it is larger, it is assumed to be (N-1). For example, circuit component T(N-1)
Any circuit component T(
i), the upper bit circuit components T(i+8) and T(i+4) output 1-bit data R(i+8) and R(i+4), respectively, and the terminal CT(
The data bit P2(i) is supplied via the bit P2(i), and one bit of data R(i) is supplied to the circuit component of the lower bit. Each of the above circuit components T(N-1)
~T(-1) are the control signals SFT11 and SFT10 supplied from the control signal generation circuit 10, and the clear signal C
The circuit operation is controlled by L and the like. This control signal SF
T11 and SFT10 are the same as those in FIG. 1, and are controlled so that the shift directions are opposite. Further, since each of the above-mentioned circuit components T(N-1) to T(-1) all have the same configuration, the above-mentioned circuit component T(i) will be used as an example in the following description of the circuit components. Circuit component T(-1) is for the quadratic Booth algorithm, and this circuit component T(-1) is cleared upon input loading of multiplier P2. The above circuit components T(7) to T
Data R(7) to R(-1) from (-1) are supplied to circuit block BO shown in FIG. This circuit block BO includes a logic circuit 71 that is supplied with signals R(3) to R(-1) and realizes the logic of FIGS. 6 and 7, which will be described later.
, a comparator 72 to which signals R(7) to R(3) are supplied, and a skip circuit 73 for determining the shift amount for the next calculation cycle. The logic circuit 71 receives the supplied signal R(
3) Based on ~R(-1), shift amount regulation signals X to 8X, control signals MOD-0 and MO in the upper columns of FIGS. 6 and 7
Signals TH, IV, and skip signal SK corresponding to D-1
etc. This skip signal SK is supplied to the skip circuit 73. In the comparator 72, the supplied signal R
(7) -R(3) are checked for coincidence or mismatch, and for example, a high-level comparison signal CP is detected only when all 5 bits of the above-mentioned signals R(7) -R(3) are at high level or low level. This comparison signal CP is supplied to the skip circuit 73. The skip circuit 73 is a circuit for determining the shift amount for the next operation cycle in the shift register constituted by the circuit block BI of FIGS. 1 and 3. In this skip signal SK, control signals SFT11 and SFT10 having the contents shown in FIG. As described above, various signals, control signals, etc. are formed in the logic circuit 71, and these will be explained below. The signal R(
3) The 5-bit data of ~R(-1) can be divided into 32 patterns depending on the combination of levels. By applying the quadratic Booth algorithm to 4 bits, the partial product PP0 of the multiplicand X corresponding to each pattern becomes as shown in FIG. This partial product PP0 can be further decomposed into partial product PP1. This partial product PP1 can be formed by a partial product PP2 that is a combination of two terms or less of the multiplicand X times a power of 2. This partial product PP2 can be formed by combining two terms that are powers of 2, so as shown in FIG. The partial product PP0 can be obtained by calculating the partial product PP2 for each and then adding the partial products PP2. The partial products PP2 mentioned above are all terms of powers of 2 times the multiplicand X [0X, ±1X, ±2X, ±4X, ±
8
The term that is a power of 2 times the multiplicand X that constitutes can be obtained by shifting the multiplicand X by the required number of bits. The signal for defining this shift amount is shown in FIG.
are defined as shift amount regulation signals X to 8X. The shift amount of the multiplicand X is defined in accordance with the signal that is at a high level among the shift amount regulation signals X to 8X. Then, control signals SFT21 and SFT20 are determined based on the combination of levels of the shift amount regulation signals X to 8X, and a shift operation is performed based on these control signals SFT21 and SFT20. The partial product PP2 mentioned above is the data R(i) in the selector 35 of the circuit block BJ shown in FIG.
~R(i-3) can be obtained by selecting. That is, selecting data R(i) corresponds to multiplying the multiplicand X by 1, selecting data R(i-1) corresponds to multiplying the multiplicand X by 2, and data R(i- 2
) is equivalent to multiplying the multiplicand X by 4, and selecting the data R(i-3) is equivalent to multiplying the multiplicand X by 8.
Equivalent to doubling. Signals TH and IV in FIG. 7 correspond to control signals MOD-0 and MOD-1, respectively, and in circuit block BK in FIG. It controls whether to pass through as is, invert it, or set it to "zero". for example,
When the signal TH (=L), IV (=L), it is "zero",
When the signals TH (=L) and IV (=H) are present, the signal is inverted, and when the signals TH (=H) and IV (=L) are present, the signal is passed through as is. Furthermore, the skip signal SK in FIG. 7 is based on the 5-bit data R(3) to R(-1) input to the logic circuit 71 shown in FIG. It is sometimes made to reach a high level. For example, in the pattern of partial product PP2, if there is only one term that is a power of 2 times the multiplicand . For example, in the pattern in which there is only one term in the partial product PP2 shown in FIG. 7, there is no calculation of the partial product PP2 in the second cycle C2, so the skip signal in the first cycle C1 is SK becomes high level. Of course, in the second cycle C2, the skip signal SK becomes high level. In the column of the second cycle C2 mentioned above, “*
” means that it is a skippable part. Next, an operation example will be explained. FIR
Taking a digital filter as an example, the number of taps is 3, and the coefficient h1 ~
Let each h3 be 12 bits (N=12). (1) Coefficient h1=[0000 0100 0010
](2) Coefficient h2=[0010 0000 01
01 ] (3) Coefficient h3 = [1111 1110
1100] However, the above-mentioned coefficients h1 to h3 are expressed in two's complement numbers. (1) Coefficient h1=[0000 010
0 0010 ], the multiplicand X is supplied to the circuit block BI in the circuit component S(i), and the multiplier P2, in this case the coefficient h1 mentioned above, is supplied to the circuit component T(i). In the circuit block BI in the circuit component S(i), the data bit X(i) supplied via the terminal AT(i) is selected and taken in by the supplied control signals SFT11 and SFT10. In the first cycle for multiplication of the coefficient h1, the 4 bits of the multiplier corresponding to data R(3) to R(-1) in FIG.
1)=0] is checked in the logic circuit 71. In the logic circuit 71, the above-mentioned 5-bit data is [00100], so the following can be seen from FIGS. 6 and 7. The shift amount regulation signals X to 8X are “LHLL”.
”, only the shift amount regulation signal 2X is output at high level, the signal TH is output at “H”, the signal IV is output at “L”, and the skip signal SK is output at “H” level. [0081] As a result, the partial product PP0 only needs to be calculated as "2X", and the circuit block BK outputs the output from the circuit block BJ as it is, and furthermore, the calculation is performed only in the first cycle C1. It can be seen that it is possible to skip to the processing of the next 4 bits of the multiplier P2.
In order to obtain X'', in circuit block BJ in circuit component S(i), control signals SFT21, SFT
20 selects the output of the circuit block BI of the data R(i-1), that is, the one-bit lower circuit component S(i-1). Furthermore, as described above, in circuit block BK, the output from circuit block BJ is output as is, and this output is held in the accumulator of circuit block BL. When the processing of the lower 4 bits of the coefficient h1 is completed, the process moves to the next upper 4 bits. circuit component S
(i), T(i) circuit block BI uses control signals SFT11, SFT10 to control data R(i-
4) Select. The above data R(i-4) is selected and shifted by 4 bits. Note that this shift operation is performed by the multiplier P2(i), that is, the circuit component S
(i) is left shifted, and data bit X(i), ie, circuit component T(i), is shifted right. The central 4 bits of coefficient h1 are [0100]
Since the lower bit is [0], the 5-bit data corresponding to data R(3) to R(-1) in FIG. 4 is [01000]. In the logic circuit 71, the above-mentioned 5-bit data is [01000], so the following can be seen from FIGS. 6 and 7. The shift amount regulation signals X to 8X are “LLHL”.
”, only the shift amount regulation signal 4X is output at high level, the signal TH is output at “H”, the signal IV is output at “L”, and the skip signal SK is output at “H”. [0087] As a result, the partial product PP0 only needs to be calculated as "4X", and the circuit block BK outputs the output from the circuit block BJ as it is, and furthermore, the calculation is performed only in the first cycle C1. It can be seen that it is possible to skip to the processing of the next 4 bits of the multiplier P2.
In order to obtain X'', in circuit block BJ in circuit component S(i), control signals SFT21, SFT
20 selects the output of the circuit block BI of the data R(i-2), that is, the 2-bit lower circuit component S(i-2), and selects the output of the circuit block BI of the data R(i-2), that is, the 2-bit lower circuit component S(i-2), and
The data of " When the processing of the middle 4 bits of coefficient h1 is completed, circuit components S(i), T(i)
The circuit block BI attempts to select data R(i-8). At this time, the comparator 72 shown in FIG.
is supplied with the most significant 4 bits [0000] mentioned above, and the most significant data R(3) of the middle 4 bits mentioned above is supplied to
[=0] is added and the 5-bit data becomes [000]
00], the comparison signal CP is output at "H". The skip circuit 73 determines that since the above-mentioned 5-bit data becomes [00000], processing of the next 4 bits is unnecessary. Therefore, the processing of the coefficient h1 ends at this stage. The processing of coefficient h1 took two cycles. (2) Coefficient h2=[0010 000
0 0101 ], the multiplicand X is supplied to the circuit block BI in the circuit component S(i), and the multiplier P2, in this case the above-mentioned coefficient h1, is supplied to the circuit component T(i). In the circuit block BI in the circuit component S(i), the data bit X(i) supplied via the terminal AT(i) is selected and taken in by the supplied control signals SFT11 and SFT10. In the first cycle for multiplication by the coefficient h2, the 4 bits of the multiplier corresponding to data R(3) to R(-1) in FIG.
1)=0] is checked in the logic circuit 71. In the logic circuit 71, the above-mentioned 5-bit data is [01010], so the following can be seen from FIGS. 6 and 7. That is, in the first cycle C1, the shift amount regulation signals X to 8X are "LLHL" and the shift amount regulation signal 4 is "LLHL".
Only X is output at high level, and signal TH is “H”.
", the signal IV is output at "L", the skip signal SK is output at "L", and in the second cycle C2, the shift amount regulation signals X to 8X are "HLLL".
”, only the shift amount regulation signal X is output at high level, the signal TH is output at “H”, the signal IV is output at “L”, and the skip signal SK is output at “H” level. As a result, in the first cycle C1, the partial product PP0 only needs to be calculated as "4X", and in the circuit block BK, the output from the circuit block BJ is output as is, and furthermore, the calculation It can be seen that the process does not end only in the first cycle C1 and cannot be skipped to the processing of the next 4 bits of the multiplier P2.Also, in the second cycle C1, the partial product P
P0 only needs to find "X", and circuit block BK
It can be seen that the output from circuit block BJ is output as is, and that the calculation ends in the second cycle C2. Therefore, in the first cycle C1, "4X"
In order to obtain the control signals SFT21 and SFT20 in the circuit block BJ in the circuit component S(i),
selects the output of the circuit block BI of the data R(i-2), that is, the 2-bit lower circuit component S(i-2). Furthermore, as described above, in circuit block BK, the output from circuit block BJ is output as is, and this output is held in the accumulator of circuit block BL. Next, in the second cycle C2, in order to obtain "X", the circuit block BJ in the circuit component S(i) uses the control signals SFT21 and SFT20 to control the data R(i), that is, the relevant bit. Select the output of circuit block BI of circuit component S(i). Furthermore, as described above, in circuit block BK, the output from circuit block BJ is output as is, and this output is held in the accumulator of circuit block BL. [0100] When the processing of the lower 4 bits of the coefficient h2 is completed, the circuit block BI of the circuit components S(i) and T(i) performs control in order to proceed to the processing of the next middle 4 bits, that is, [0000]. Signal SFT11, SFT10
The data R(i-4
). At this time, the comparator 72 shown in FIG.
is supplied with the above-mentioned middle 4 bits [0000],
In addition, the most significant signal R(3) of the middle 4 bits described above [
=0] is added to create 5-bit data [00000]
Therefore, as is clear from FIGS. 6 and 7, both the skip signal SK and the comparison signal CP are output at "H". The skip circuit 73 determines that since the above-mentioned 5-bit data becomes [00000], processing of the next 4 bits is unnecessary. Therefore, at this stage, the processing of the middle 4 bits of the coefficient h2 is completed. When the processing of the middle four bits of the coefficient h2 is completed, the circuit block BI of the circuit components S(i) and T(i) controls the processing of the next upper four bits, that is, [0010]. Signal SFT11, SFT10
The data R(i-8
). [0104] The data of the upper 4 bits [0010] mentioned above includes the most significant data R(3) [=0] of the middle 4 bits.
] is added to form 5-bit data [00100]. In the logic circuit 71, the above-mentioned 5-bit data is [00100], so the following can be seen from FIGS. 6 and 7. In the first cycle C1, the shift amount regulation signals X to 8X are "LHLL" and only the shift amount regulation signal 2X is output at a high level, and the signal TH is "H".
For example, the signal IV is output at "L" and the skip signal SK is output at "H". [0106] As a result, the partial product PP0 only needs to be calculated as "2X", and the circuit block BK outputs the output from the circuit block BJ as it is, and furthermore, the calculation ends only in the first cycle C1. I understand. Therefore, in order to find “2X”, the circuit component S(i
) In the circuit block BJ inside, the control signal SFT21
, SFT20 selects the output of the circuit block BI of the data R(i-1), that is, the one-bit lower circuit component S(i-1). Furthermore, as described above, in circuit block BK, the output from circuit block BJ is output as is, and this output is held in the accumulator of circuit block BL. Therefore, the processing of the coefficient h2 ends at this stage. The processing of coefficient h2 takes 3 cycles, and the processing of coefficient h1
, h2 has a total number of cycles of 5 cycles. (3) Coefficient h3=[1111 111
0 1100] The multiplicand X is the circuit component S(i
), the multiplier P2, in this case the above-mentioned coefficient h3, is applied to the circuit component T(i)
is supplied to In the circuit block BI in the circuit component S(i), the supplied control signal SFT11
, SFT10 selects and captures the data bit X(i) supplied via terminal AT(i). In the first cycle for multiplication by coefficient h3, the 4 bits of the multiplier corresponding to data R(3) to R(-1) in FIG.
1)=0] is checked in the logic circuit 71. In the logic circuit 71, the above-mentioned 5-bit data is [11000], so the following can be seen from FIGS. 6 and 7. The shift amount regulation signals X to 8X are “LLHL”.
”, only the shift amount regulation signal 4X is output at high level, the signal TH is output at “L”, the signal IV is output at “H”, and the skip signal SK is output at “H”. [0111] As a result, the partial product PP0 only needs to be calculated as "4X", and the output from the circuit block BJ is inverted in the circuit block BK.
It can be seen that it is possible to complete only cycle C1 and skip to processing of the next 4 bits of multiplier P2. Therefore, in order to obtain "4X", circuit block BJ in circuit component S(i) uses control signals SFT21 and SFT20 to obtain data R(i-2), that is, circuit component S(i-2 ) circuit block BI
Select the output of Furthermore, as described above, in circuit block BK, the output from circuit block BJ is inverted, and this output is held in the accumulator of circuit block BL. [0113] When the processing of the lower 4 bits of coefficient h3 is completed, the process moves on to the next middle 4 bits. In the circuit block BI of circuit components S(i) and T(i), data R(i) is controlled by control signals SFT11 and SFT10.
-4) Select. The above data R(i-4) is selected and shifted by 4 bits. Note that this shift operation is performed by the multiplier P2(i), that is, the circuit component S
(i) is left shifted, and data bit X(i), ie, circuit component T(i), is shifted right. [0115] The central 4 bits of coefficient h3 are [1110]
Since the lower bit is [1], the 5-bit data corresponding to data R(3) to R(-1) in FIG. 4 is [11101]. In the logic circuit 71, the above-mentioned 5-bit data is [11101], so the following can be seen from FIGS. 6 and 7. The shift amount regulation signals X to 8X are “HLHL”.
At "L", only the shift amount regulation signal X is output at high level, the signal TH is output at "L", the signal IV is output at "H", and the skip signal SK is output at "H". [0117] From this, the partial product PP0 can be obtained by finding "X", and the output from the circuit block BJ is inverted in the circuit block BK, and furthermore, the calculation is performed only in the first cycle C1. It can be seen that it is possible to skip to the processing of the next 4 bits of the multiplier P2.Therefore, in order to obtain "X", the circuit block BJ in the circuit component S(i) uses the control signals SFT21 and SFT20 to process the data R(i ), selects the output of the circuit block BI of the circuit component S(i) of the bit. Furthermore, as described above, the output from the circuit block BJ is inverted in the circuit block BK, and this output is transmitted to the circuit block BL. When processing of the middle 4 bits of the coefficient h3 is completed, circuit components S(i), T (i)
The circuit block BI attempts to select data R(i-8). At this time, the comparator 72 shown in FIG.
is supplied with the most significant 4 bits [1111] mentioned above, and the most significant data R(3) of the above mentioned middle 4 bits.
[=1] is added and the 5-bit data becomes [111]
11], so the skip signal SK and comparison signal C
P is output at "H". [0121] In the skip circuit 73, since the above-mentioned 5-bit data becomes [11111], there is no need to process the next 4 bits, which means that there is no need to form the partial product PP0. . Therefore, the processing of the coefficient h3 ends at this stage. The processing of coefficient h3 is 2
The total number of cycles from coefficient h1 to coefficient h3 was 7 cycles. [0122] In the case of 12 bits, it usually takes 12 cycles if there is only an accumulator, and 36 cycles if there are 3 taps.
It takes a cycle. Using the second-order Booth algorithm requires half that, 18 cycles. However, in this embodiment, only seven cycles are required. Generally speaking, multiplication of B bits can basically be realized with the number of calculation cycles B if there is one accumulator, and if the second-order Booth algorithm is used, the number of calculation cycles can be reduced to (B/2). ), and if the fourth-order Booth algorithm is used, the number of calculation cycles becomes (3/8)B. In this embodiment, the fourth-order Booth algorithm is used as the basis, and a calculation skip is added, but the coefficients h1 to h
The number of calculation cycles is approximately (3/8)B because the cycle for acquiring 3 cannot be skipped. in this way,
The quadratic Booth algorithm is applied to data consisting of multiple bits in units of 4 bits, and partial products are generated in units of 4 bits in each calculation cycle. Since it is determined whether the partial product in the next calculation cycle becomes zero, if it is determined that the partial product calculation in the next calculation cycle is unnecessary, the calculation can be skipped. The number of cycles can be reduced and partial product generation is efficient. When the multiplier P2 is a fixed value, such as in a digital filter with fixed characteristics or cosine transformation, if the multiplier P2 is determined so as to reduce the number of calculation cycles, the effect of reducing the calculation cycles becomes greater. The selector 32 of the circuit block BI is a 4-input selector, and the control signals SFT11, SFT10
In addition to data bit P1(i), output R(i)
It is also possible to select R(i-4) and shift left by 4 bits, or select R(i-8) and shift left by 8 bits. The BJ selector 35 is a 4-input selector, and the output R(
i) , R(i-1) , R(i-2) , R(i-3
), and the partial product calculation method can be selected from 1x, 2x, 4x, and 8x, so in addition to the above-mentioned effects, it has a wide range of functions. It is possible to reduce the gate scale, achieve high speed, and prevent circuit complexity. [0125] Circuit components T(7) to T(-1
), the circuit block BO outputs signals TH and IV corresponding to shift amount regulation signals X to 8X and control signals MOD-0 and MOD-1.
, skip signal SK, etc. This skip signal SK is supplied to a skip circuit 73. Furthermore, since the work of skipping the generation of unnecessary partial products and minimizing the number of arithmetic cycles is not performed by hardware, but is separately determined in advance, there is an effect that optimization becomes possible. [0126] According to the arithmetic circuit according to the invention of claim 1, the quadratic Booth algorithm is applied to data consisting of a plurality of bits in units of 4 bits, and a partial calculation is performed in each arithmetic cycle. The product is generated in units of 4 bits, and the data is separately looked ahead to determine whether the partial product in the next calculation cycle will be zero, so the calculation of the partial product in the next calculation cycle is This has the effect that the calculation can be skipped when it is determined that the calculation is no longer necessary, the number of calculation cycles can be reduced, and the efficiency of partial product generation is high. According to the arithmetic circuit according to the invention of claim 2,
Expanding and applying the secondary Booth's algorithm to 4-bit units, and realizing the functions required when applying the Booth's algorithm with a small-input selector [4-input selector] without using the conventional multi-input selector. In addition to the effects of the invention of claim 1, this configuration has the advantage that the gate scale can be reduced while providing a wide range of functions, high speed can be realized, and circuit complexity can be prevented. Furthermore, since the work of skipping the generation of unnecessary partial products and minimizing the number of arithmetic cycles is not performed by hardware, but is separately determined in advance, there is an effect that optimization becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an arithmetic circuit according to the present invention.

FIG. 2 is a block diagram showing the configuration of a circuit component S(i).

FIG. 3 is a block diagram showing the configuration of a control signal generation circuit.

FIG. 4 is a block diagram showing the configuration of a control signal generation circuit.

FIG. 5 is a schematic diagram showing contents controlled by control signals.

FIG. 6 is a schematic diagram showing the relationship between data input to a logic circuit and a signal output corresponding thereto.

FIG. 7 is a schematic diagram showing the relationship between data input to a logic circuit and signals output in response to the data.

FIG. 8 is a block diagram showing the configuration of a circuit block BI of circuit components.

FIG. 9 is a block diagram showing the configuration of a circuit block BI of circuit components.

FIG. 10 is a block diagram showing the configuration of a circuit block BI of circuit components.

FIG. 11 is a block diagram showing a conventional product-sum calculation circuit.

FIG. 12 is a block diagram showing a barrel shifter.

FIG. 13 is a circuit diagram showing an example of a logic circuit.

FIG. 14 is a circuit diagram showing an example of a logic circuit.

FIG. 15 is a block diagram showing a conventional product-sum calculation circuit.

FIG. 16 is a block diagram showing a selector.

[Explanation of symbols]

32, 35 Selector 51 Full adder 52, 53, 58, 59 Flip-flop

Claims (2)

[Claims] Claim 1: In an arithmetic circuit that obtains the multiplication result of data consisting of a plurality of bits by forming partial products, the quadratic Booth algorithm is applied to the data in units of 4 bits, and the When the data is shifted in 4-bit units to generate partial products in 4-bit units in each calculation cycle, and by looking ahead at the above data, it is determined that the partial product to be generated in the next calculation cycle will be zero. is an arithmetic circuit characterized by skipping the next partial product operation. 2. The circuit component comprises a control signal generation circuit that forms various control signals, a circuit component that processes each bit of data, and an accumulator that accumulates the outputs of the circuit component. , a first selection means for selecting arbitrary bit data for specifying a data shift amount from a plurality of bit data or bit data for operation supplied from the lower bit circuit component and having a predetermined bit interval; , the first
from among the 1-bit data supplied from the selection means and the 1-bit data that is continuous from the circuit component to the lower side and has the same number of bits as the first selection means,
a second selection means for selecting arbitrary 1-bit data for defining the amount of data shift, and an addition output and a carry output based on the output from the second selection means, an accumulator that supplies a carry output to a higher-order bit circuit component and forms the carry output from a lower-bit circuit component and the addition output as outputs of the circuit component; and an addition output supplied from the upper-bit circuit component. and a carry output, and an output circuit that selects and holds either the addition output or the carry output supplied from the accumulator, and supplies the held value to the lower bit circuit component. An arithmetic circuit characterized by: