KR100386979B1 - Method of paralleling bit serial multiplier for Galois field and a bit serial-parallel multipiler using thereof - Google Patents

Abstract

The present invention relates to a method for parallelizing a bit serial multiplier on a galloche, and to a bit serial-parallel multiplier on a galloche with a simple configuration.

The method of the present invention multiplies the multiplier g [N-1: 0] on GF ( ^2N ) by the multiplied multiplicand x '[N-1: 0] and transforms the result of the calculation z' [N-1: 0]. In the method of parallelizing a bit serial multiplier on a galloche outputting a parallel output, the parallel shift register for storing the multiplier is parallelized to a predetermined number according to the depth of parallelization, and a combination circuit for obtaining the sum of the product of the multiplier and the multiplier is parallelized. By parallelizing a predetermined number according to the depth, the number of clocks required for the multiplier calculation is reduced to improve the calculation speed.

Accordingly, the present invention can shorten the time required to multiply without adding a lot of hardware by parallelizing the bit-serial multiplier on Galoache, and optimize the parallelization depth by parallelizing only as much as necessary in the used system. Compute time and hardware area can be optimized.

Description

Parallel method of bit serial multiplier on Galoache and method of parallel multiplier using the same {method of paralleling bit serial multiplier for Galois field and a bit serial-parallel multipiler using about}

The present invention relates to a multiplier on a galloche, and more particularly, to a method for parallelizing a bit serial multiplier and to a bit serial-parallel multiplier on a galloche with a simple configuration using the same.

In general, the method of implementing multiplication on Galoa is divided into a parallel multiplier and a serial multiplier. A serial multiplier is widely used because it takes less hardware area to implement. There is a problem that takes a lot of computation time. On the other hand, the parallel multiplier can reduce the operation speed, but there is a problem in that the cost increases because the hardware is complicated and takes up a lot of area when implemented as a chip. That is, conventionally, a bit-serial multiplier is used to reduce the hardware area or a parallel multiplier is used to reduce the computation time. However, in the case of a serial multiplier on Galoische, multiplication of the multiplier requires N clocks, and a parallel multiplier requires a large amount of hardware to store N * N bit elements.

An object of the present invention is to provide a parallelization method of a bit serial multiplier and a serial-to-parallel multiplier using the same in the Galloche to solve the problems of the parallel multiplier and the bit-serial multiplier.

1 is a diagram showing the configuration of a general bit serial multiplier;

2 is a diagram illustrating the concept of a bit-parallel multiplier (parallelization depth 2) according to the present invention;

3 is a detailed block diagram of the bit-parallel multiplier shown in FIG.

4 is a diagram illustrating the concept of a bit-parallel multiplier (parallelization depth 4) according to the present invention.

* Explanation of symbols for main parts of the drawings

301 to 309: shift register 311 to 318: register

321--328,331--338: Galoache Multiplier 341,342,351,352: Galoache Adder

In order to achieve the above object, in the method of the present invention, a multiplication multiplier g [N-1: 0] on GF ( ^2N ) multiplied by the multiplied multiplier x '[N-1: 0] is converted to result z A method of parallelizing a bit serial multiplier on a galloche that outputs [N-1: 0], wherein the shift register for storing the multiplier is parallelized to a predetermined number according to the parallelization depth, and the product of the multiplier and the multiplier The combination circuit for obtaining the sum is parallelized to a predetermined number according to the parallelization depth, thereby reducing the number of clocks required for the multiplier operation, thereby improving the operation speed.

In addition, the apparatus of the present invention for achieving the above object multiplies the multiplier g [7: 0] on the GF (2 ⁸ ) by the multiplied multiplicand x '[7: 0] converted z' [7: In the multiplier on Galoache that outputs 0], four shift registers (x '[1], x' [3], x '[5], x' [7]) are connected in series and stored at every clock. The first shift register group for shifting the? And five shift registers (x '[0], x' [2], x '[4], x' [6], and x '[8]) are connected in series. A register unit including a second shift register group for shifting a stored value for each clock in parallel, and loading the initially multiplied multiplier into the registers x '[1] to x'[8]; Outputting the result of the calculation (z '[t]) every clock by calculating the sum of the outputs of the registers x' [0] to x '[7] and the multipliers g [0] to g [7]. 1 combination circuit; And calculating the sum of the outputs of the registers x '[1] to x' [8] and the multipliers g [0] to g [7] by the sum of the products to calculate the calculation result z '[t + 1] every clock. And a second combination circuit for outputting.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the present invention, by reducing the number of clocks required for the operation by parallelizing the shift registers used in the bit-serial multiplier on the galloche GF ( ^2N ), the operation time is reduced without adding a lot of hardware. The number of clocks needed to perform multiplication using a bit-serial multiplier on Galoache GF ( ^2N ) is N, and each time the parallelizing depth (P) is increased by 2 times according to the present invention. The number of clocks required is reduced by half. On the other hand, there is a need for a combination circuit to perform the product of the additional 2 * P-3 registers needed. If N is not a large value, then the amount of additional hardware required until the parallelization depth is N / 2 is not large.

Figure 1 shows a general implementation of a bit-serial multiplier on GF (2 ⁸ ), where the primitive equation is x ⁸ + x ⁴ + x ³ + x ² +1. In FIG. 1, g [7: 0] is a multiplier, x '[7: 0] is a transformed form of multiplicand, and z' [7: 0] is a deformation of the operation result. Form. Reference numerals 101 to 108 denote shift registers that shift according to a clock after loading a multiplicand. 111 to 118 denote registers for storing and storing multipliers, and 121 to 128 output the multipliers and registers output by the shift register. Galoache multiplier to multiply. 131 is a galloche adder for summing the outputs of the shift registers and providing them back to the shift register. In a Galoache operation, a Galoache adder can be implemented as an exclusive EX-OR gate, and a Galoache multiplier can be implemented as an end (AND) gate.

In this configuration, the operation of the multiplier consists of a loading step and an operation step of loading a multiplier and a multiplier value into each register. In the operation step, z '[0] to z' [7] are sequentially output every clock. That is, when the multiplier and the multiplicand of the modified form are stored as initial values, the first bits z '[0] of the multiplication result can be obtained by the circuits 121 to 128 and 132 performing the sum of the products of FIG. Each time the clock CLK is input to the shift registers 101-108, a new state is reached, from which the next bit of the output can be obtained. When the clock CLK is continuously input and all bits of the output are obtained, the new multiplication is performed by the new multiplier and the modified multiplicand by the above process. The time required to multiply by this circuit requires eight clocks after initializing the registers with a multiplier and a multiplicand, and a circuit that performs the sum of eight registers and two products.

FIG. 2 is a conceptual diagram of parallelizing the shift register of FIG. 1 to a parallelization depth 2 according to the present invention. In FIG. 2 g [7: 0] is a multiplier, x '[7: 0] is a transformed form of multiplicand, z' [t] and z '[t + 1 ] Is a variant of the result of the operation. 201 to 209 are shift registers, in which 201 to 204 are connected in series, and 205 to 209 are connected in series. The "^" in x '[1] ^ x' [3] ^ x '[4] ^ x' [5] represents an exclusive oramic operation, that is, addition, so x '[1], x' [3], The sum of x '[4] and x' [5] is fed back to the shift register 201 and inputted. x '[2] ^ x' [4] ^ x '[5] ^ x' [6] is the sum of x '[2], x' [4], x '[5], x' [6] It is inputted to the shift register 205 and shown. Reference numerals 211 to 218 and 231 to 238 indicate multiplying the multiplicands stored in the register with the corresponding multipliers, respectively, and the outputs of 211 to 218 are summed together by the galloace adder 220 and output as z [t]. The outputs are summed together by the galloche adder 240 and output as z [t + 1].

As described above, the multiplier of the present invention parallelized to the parallelization depth 2 stores the multiplier and the multiplicand of the modified form in g [0] to g [7] and x '[1] to x' [8]. Thus, the first output bits z '[0] and z' [1] of the multiplication result are obtained. Subsequently, when the clock is input, the shift registers 201 to 209 are shifted to the new state by two combination circuits, and the next two bits (z '[2], z [') of the multiplication result by the sum circuit of the two products. 3]). Keep getting the clock and getting all eight output bits ("z '[4], z' [5]", "z '[6], z' [7]") of the multiplication results in a new multiplier and The multiplicand of the type is input to prepare for the next multiplication. As described above, in the case of the multiplier composed of the circuit of FIG. 2, a 2-bit operation result (z '[t], z' [t + 1]) is output for each clock, so that the required number of clocks is 1 / It is 2, and one clock that is initially needed can be added together to multiply all by 5 clocks.

FIG. 3 is an example in which the bit serial-parallel multiplier shown in FIG. 2 is implemented by hardware logic. Referring to FIG. 3, 301 to 309 are shift registers corresponding to 201 to 209 of FIG. 2, and 211 to 218 and 231 to 238 of FIG. 2 have two galloace multipliers and one register as shown in FIG. 3. Implemented in the same configuration. 341 of FIG. 3 is a galloach adder corresponding to 220 of FIG. 2, and 342 is a galloach multiplier corresponding to 240. And x '[1] ^ x' [3] ^ x '[4] ^ x' [5] in Figure 2 is x '[1], x' [3], x '[4], x' [5 ] Is implemented by a Galloche adder (351), where x '[2] ^ x' [4] ^ x '[5] ^ x' [6] is x '[2], x' [4] It is implemented by a Galloche adder 352 to obtain the sum of x '[5] and x' [6].

In FIG. 3, a multiplicand is loaded into the shift registers 302 ˜ 309 and a multiplier is loaded into the registers 311 ˜ 318 in the loading step. Subsequently, the values of the shift register are shifted to the left every clock CLK in the calculation step, and two calculation results z '[t] and z' [t + 1] are output by two combination circuits of product sums. do. That is, since the multiplier of the parallelization depth 2 according to the present invention outputs two calculation results in one clock CLK, the calculation result can be obtained by four clocks, and thus the overall processing speed can be improved by adding less hardware.

4 is a diagram illustrating the concept of a bit-parallel multiplier (parallelization depth 4) according to the present invention. Referring to FIG. 4, when the multiplier and the modified multiplicand are stored in g [0] to g [7] and x '[3] to x' [10], the first output bit of the multiplication result by the sum circuit of the product (z '[0], z' [1], z '[2], z' [3]) are obtained respectively. In this state, when the next clock is input, the shift register is shifted to the new state by four combination circuits, and the next four bits of the multiplication result by the sum circuit of the four products (z '[4], z' [5). ], z '[6], z' [7]).

In this state, when the next clock is input, a new multiplier and a modified multiplicand are prepared to prepare for the next multiplication.

In this way, the multiplier composed of the circuit of FIG. 4 has four bit calculation results (z '[t], z' [t + 1], z '[t + 2], and z' [t + 3]) for each clock. The number of clocks required to be output is 1/4 of the case of FIG. 1, and one clock is added to all three clocks.

As described above, the present invention can shorten the time required to multiply without adding a lot of hardware by parallelizing the bit-serial multiplier on Galoache, and by parallelizing only as much as necessary in the system used, the depth of parallelization can be reduced. It can be optimized, which has the effect of optimizing computation time and hardware area.

Claims (3)

Multiplied by multiplier g [N-1: 0] on GF (2 ^N ) and the transformed multiplicand x '[N-1: 0] to output the transformed result z' [N-1: 0] In the method of parallelizing a bit serial multiplier, Parallelizing a shift register for storing the multiplicand by a predetermined number according to the parallelization depth, The combination circuit for obtaining the sum of the products of the multiplier and the multiplier is parallelized by a predetermined number according to the parallelization depth And reducing the number of clocks required for the multiplier operation to improve the operation speed. In the multiplier on Galloche that multiplies the multiplier g [7: 0] on GF (2 ⁸ ) by the converted multiplicand x '[7: 0] and outputs the converted result z' [7: 0], Four shift registers (x '[1], x' [3], x '[5], x' [7]) are connected in series so that the first shift register group and five shifts shift the stored value every clock. Second shift register group in which registers x '[0], x' [2], x '[4], x' [6], x '[8] are connected in series to shift the stored value every clock A register having parallel to and loading the initially multiplied multiplier into the registers x '[1] to x' [8]; Outputting the result of the calculation (z '[t]) every clock by calculating the sum of the outputs of the registers x' [0] to x '[7] and the multipliers g [0] to g [7]. 1 combination circuit; And The output of the registers x '[1] to x' [8] and the multiplier g [0] to g [7] are calculated as the sum of the products to output the calculation result z '[t + 1] every clock. And a bit series-parallel multiplier on Galoache, characterized in that it comprises a second combination circuit. In the multiplier on Galloche that multiplies the multiplier g [7: 0] on GF (2 ⁸ ) by the converted multiplicand x '[7: 0] and outputs the converted result z' [7: 0], A first shift register group in which two shift registers x '[3] and x' [7] are connected in series to shift a stored value every clock, and three shift registers x '[0] and x' [ 4], x '[8]) are connected in series to shift a stored value every clock, and three shift registers (x' [1], x '[5], x' [9). ] Is connected in series, and the third shift register group for shifting the stored value every clock and the three shift registers (x '[2], x' [6], x '[10]) are connected in series. A register unit including a fourth shift register group for shifting a stored value in every clock in parallel, and for loading an initially multiplied multiplier into the registers x '[3] to x' [10]; Outputting the result of the calculation (z '[t]) every clock by calculating the sum of the outputs of the registers x' [0] to x '[7] and the multipliers g [0] to g [7]. 1 combination circuit; The output of the registers x '[1] to x' [8] and the multiplier g [0] to g [7] are calculated as the sum of the products to output the calculation result z '[t + 1] every clock. A second combination circuit; The output of the registers x '[2] to x' [9] and the multiplier g [0] to g [7] are calculated as the sum of the products to output the calculation result z '[t + 2] every clock. A third combination circuit; And The output of the registers x '[3] to x' [10] and the multiplier g [0] to g [7] are calculated as the sum of the products to output the calculation result z '[t + 3] every clock. A bit serial-parallel multiplier on a galloche, characterized by comprising a fourth combination circuit.