RU2797164C1 - Pipeline module multiplier - Google Patents

Abstract

FIELD: computing technology.

SUBSTANCE: conveyor multiplier contains n parallel registers, n keys, (n−1) module multipliers by two, (n−1) module adders, where n is the capacity of the numbers being processed, with the corresponding links.

EFFECT: increasing speed of operations of multiplying numbers by an arbitrary module during conveyor processing of information.

1 cl, 2 dwg

Description

The field of technology to which the invention belongs

The invention relates to computer technology and can be used in conveyor-type digital computing devices, as well as in digital signal processing devices and in cryptographic applications.

State of the art

From the existing prior art known multiplier modulo two, containing an adder and a multiplexer that allows you to multiply numbers by two by arbitrary modules [1]. A technical problem that cannot be solved using this technical solution is the impossibility of multiplying numbers in arbitrary modules by other numbers that are not equal to two, since additional technical means will be required to perform such an operation.

From the existing prior art, a device is known for multiplying numbers modulo an arbitrary, containing ( m -1) adders, ( m -1) multiplexers, m keys, ( m -2) shift blocks, an inverter and a modulo adder, which allows multiplication of two numbers modulo [2]. A technical problem that cannot be solved using this technical solution is the low speed when multiplying numbers modulo an arbitrary number during pipeline processing of information, since the multiplication of successive numbers modulo in a stream cannot be started until the multiplication of the previous ones is completed. modulo numbers.

The closest to the claimed technical solution in terms of technical essence and the achieved technical result, selected as a prototype, is a modulo multiplier containing keys, adders, multiplexers, which allows to perform reduction of numbers by arbitrary modules [3]. A technical problem that cannot be solved when using this technical solution for pipelined processing of information is the low speed when multiplying numbers modulo an arbitrary, since the multiplication of successive numbers modulo in the stream cannot be started until the multiplication modulo is completed. modulus of previous numbers.

The technical result provided by the above set of features is to increase the speed of operations of multiplying numbers by an arbitrary modulus during pipeline processing of information.

Disclosure of the essence of the invention

The specified technical result in the implementation of the invention is achieved by the fact that the pipeline calculator containing n keys, where n is the capacity of the processed numbers, the first information inputs of the device, the second information inputs of the device, the third information inputs of the device, the information outputs of the device, the code is fed to the first information inputs of the device multiplier, the second information inputs of the device are supplied with the multiplier code, the third information inputs of the device are supplied with the inverse code of the module, the code for the product of numbers modulo is removed from the information outputs of the device, n parallel registers are introduced, ( n − 1) multipliers by two modulo, ( n −1) modulo adders, the clock input of the device, which is connected to the clock inputs of n parallel registers, the first information inputs of the device are connected to (1, ..., n )-bits of the information inputs of the first parallel register, the second information inputs of the device are connected to ( n +1, …, 2 n )-bits of the information inputs of the first parallel register, the third information inputs of the device are connected to the second inputs of multipliers by two modulo and to the third inputs of modulo adders, the output of the ( n −1)-th adder modulo the module is connected to the information outputs of the device, the first bit of the information outputs of the (1, ..., n )-th parallel registers is connected respectively to the control input of the (1, ..., n )-th keys, (1, ..., n − i +1) - e bits of information inputs of i -th parallel registers, i =(2, …, n ), are connected to (2, …, n − i +2)-th bits of information outputs of ( i −1) -th parallel registers, ( n − i +2, …, 2 n − i +1)-th bits are connected to information outputs of ( i -1)-th multipliers by two modulo, (2 n , …, 3 n −1)-th bits of information inputs of the second parallel register are connected to the outputs of the first key, and (2 n - i +2, ..., 3 n - i + 1)-th bits of information inputs of the (3, ..., n )-th parallel registers with outputs (1, ..., n − 2)-th modulo adders, (2, …, n+ 1)-th bit of information outputs of the n -th parallel register is connected to information inputs of the n -th key, (2 n − i +2, …, 3 n-i + 1)th bits of the information outputs of the i -th parallel registers are connected to the first information inputs of the ( i −1)th modulo adders, the second information inputs of which are connected to the information outputs of the i -th keys, ( n−i +2, ..., 2 n−i +1)-th bits, i =(1, …, n ), information outputs of the (1, …, n − 1)th parallel registers are connected respectively to information inputs (1, …, n − 1) -th keys and with the first inputs of (1, …, n − 1)-th multipliers by two modulo.

The essence of the invention lies in the implementation of the following method of multiplying two numbers modulo. Let

where A and B are positive integers, 0≤ A , B < P , called the multiplier and multiplier respectively;

P is a positive integer called the modulus;

C is a positive integer that is the product of A and B modulo P .

And

- коэффициенты, принимающие значение 0 или 1 в зависимости от значения числа A; where a _i ,

- coefficients that take the value 0 or 1 depending on the value of the number A ;

- коэффициенты, принимающие значение 0 или 1 в зависимости от значения числа B; b _i ,

- coefficients that take the value 0 or 1 depending on the value of the number B ;

коэффициенты, принимающие значение 0 или 1 в зависимости от значения модуля P; p _i ,

coefficients that take the value 0 or 1 depending on the value of the module P ;

- коэффициенты, принимающие значение 0 или 1 в зависимости от значения произведения C; c _i ,

- coefficients that take the value 0 or 1 depending on the value of the product C ;

n is the number of digits in the representation of numbers.

The problem is to find the product of C modulo P given the known A and B. The product of numbers A and B modulo P can be represented as follows:

Given that the modulo reduction operation is invariant to addition and multiplication, expression (6) can be written as:

Expression (7) can be represented as:

Let us introduce the following notation:

It's obvious that

Then expression (8) can be written in the following form:

As a result, the calculation of expression (11) in the pipeline mode can be reduced to the following computational steps.

и t ₀:At the 1st stage of the pipeline, calculate

_and t0 :

a ₁

и t ₁:At the 2nd stage of the pipeline, they calculate

a ₁

_and t1 :

а также t _{n −1}:At the nth stage of the pipeline, the value is calculated

and also t _{n −1} :

The value of t _{n -1} will be the desired product (6).

в соответствии с (9) осуществляется последовательным удвоением числа B с одновременным приведением результата по модулю P.calculation

in accordance with (9) is carried out by successive doubling of the number B with simultaneous reduction of the result modulo P .

The procedure described above defines the calculation of the product of one pair of numbers A and B .

Consider the implementation of the calculation of products for the stream of numbers A _j and B _j , coming cycle by cycle to the input of the conveyor multiplier, j =1, 2, 3, …, .

Expression (1) will then take the following form

Denote by t _{i , j} the value of the i -th partial product of the j -th pair of numbers A _j and B _j modulo P on the i -th stage of the pipeline, where i =1, 2, … , n is the number of the pipeline stage, j =1 , 2, 3, …, is the number of the device operation cycle. Then

where a _{i -1, j} are coefficients in expression (2) for A _j numbers,

It's obvious that

As a result, the calculation of expression (11) in the pipeline mode for pairs of numbers A _j and B _j modulo P can be reduced to the following computational steps.

и t _0,1:On the first stroke of the device at the 1st stage of the conveyor in accordance with (19), (20) and (21) for pairs of numbers A ₁ and B ₁ calculate

_and t0.1 :

и t _0,2:On the second cycle of operation of the device at the 1st stage of the conveyor in accordance with (19), (20) and (21) for pairs of numbers A ₂ and B ₂ calculate

_and t0.2 :

и t _{0, j} :On the j -th cycle of the device at the 1st stage of the conveyor in accordance with (19), (20) and (21) for pairs of numbers A _j and B _j calculate

and t _{0, j} :

и t _1,1:On the second stroke of the device at the 2nd stage of the conveyor in accordance with (18) and (19) for pairs of numbers A ₁ and B ₁ calculate

and t _1,1 :

и t _1,2:On the third stroke of the device at the 2nd stage of the conveyor in accordance with (18) and (19) for pairs of numbers A ₂ and B ₂ calculate

and t _1,2 :

и t _{1, j} :On the j -th cycle of the device at the 2nd stage of the conveyor in accordance with (18) and (19) for pairs of numbers A _j and B _j calculate

and t _{1, j} :

и t _1,1:Onnth cycle of the device onn-th stage of the pipeline in accordance with (18) for pairs of numbersA ₁ AndB ₁ calculate

Andt _1.1:

The value t _{n − 1,1} will be the desired product C ₁ ≡( A ₁ · B ₁ ) mod P .

и t _1,2:On (n+1)-th cycle of the device onn-th stage of the pipeline in accordance with (18) for pairs of numbersA ₂ AndB ₂ calculate

Andt _1.2:

t value   _{n − 1,2} and will be the desired product C ₂ ≡( A ₂ · B ₂ ) mod P .

и t _{1, j} :On the ( n + j )-th cycle of the device at the n -th stage of the conveyor, in accordance with (18) for pairs of numbers A _j and B _j calculate

and t _{1, j} :

The value t _{n − 1, j} will be the desired product C _j ≡( A _j B _j ) mod P .

Brief description of the drawings

The essence of the invention is illustrated by drawings.

In FIG. 1 shows the scheme of the conveyor multiplier modulo. The pipeline multiplier modulo containsn parallel registers 1.1 ÷ 1.n,n keys 2.1 ÷ 2.n, (n−1) multipliers by two modulo 3.1 ÷ 3.n-1, (n−1) adders modulo 4.1 ÷ 4.n–1, wheren - word length of the processed numbers, the first information inputs of the device 5, the second information inputs of the device 6, the third information inputs of the device 7, the information outputs of the device 8, the clock input of the device 9. The multiplier code is fed to the first information inputs of the device 5, the multiplier code is fed to the second information inputs of the device 6, the inverse code of the module is fed to the third information inputs of the device 7, the modulo product code is removed from the information outputs of the device 8. The clock input of the device 9 is connected to the clock inputsn parallel registers 1.1 ÷ 1.n. The first information inputs of device 5 are connected to (1, ...,n)-bits of the information inputs of the first parallel register 1.1, the second information inputs of the device 6 are connected to (n+1, ..., 2n)-bits of the information inputs of the first parallel register 1.1, the third information inputs of the device 7 are connected to the second inputs of multipliers by two modulo and to the third inputs of adders modulo 4.1 ÷ 4.n-1. Exit (n−1)th adder modulo 4.n-1 is connected to the information outputs of the device 8. The first bit of the information outputs (1, ...,n)th parallel registers 1.1 ÷ 1.n connected respectively to the control input (1, ...,n)th keys 2.1 ÷ 2.n, (1, …,n−i+1)th digits of information inputsith parallel register 1.i,i=(2, …,n), connected to (2, ...,n−i+2) digits of information outputs (i−1)th parallel registers 1.i−1, (n−i+2, ..., 2n−i+1)th digits are connected to information outputs (i−1)-x multipliers by two modulo 3.i−1, (2n, …, 3n−1)-th digits of the information inputs of the second parallel register 1.2 are connected to the outputs of the first key 2.1, and (2n−i+2, ..., 3n−i+1)-th digits (3, ...,n)th parallel registers 1.3 ÷ 1.n with outputs (1, ...,n−2)th adders modulo 4.1 ÷ 4.n-2. (2, …,n+1)-th category of information outputsnth parallel register 1.n connected to information inputs 2.n-th key, (2n−i+2, ..., 3ni+1)th digits of information outputsi-x parallel registers 1.i connected to the first information inputs (i−1)-th adders modulo 4.i−1, the second information inputs of which are connected to the information outputsi-x keys 2.i, (n−i+2, ..., 2n−i+1)-th digits,i=(1, …,n), information outputs (1.1, ..., 1.n−1)th parallel registers are connected respectively to the information inputs (2.1, ..., 2.n−1)-th keys and with the first inputs (3.1, ..., 3.n−1)-th multipliers by two modulo.

а в разряды с (2n−i+2)-го по (3n−i+1)-й записываются значения разрядов чисел t _{i -2}. In FIG. 2 shows the distribution of the capacity of parallel registers 1.1 ÷ 1. n devices. The first parallel register 1.1 has a capacity 2 n equal to the sum of the capacity of the input numbers A and B . Numbers A _j are written into bits _from 1st to nth of the first parallel register 1.1, and numbers Bj are written into bits from ( n +1)th to 2nth . Parallel registers 1. i , where i = (2, …, n ) is the number of the pipeline stage, have a capacity equal to (3 n − i +1). The digits from the 1st to ( n − i +1)-th i -th parallel register 1. i are filled with the values of the digits of the number A , and the number of these digits decreases at each subsequent stage of the pipeline by one from the lower ones, into digits with ( n − i +2)-th to (2 n − i +1)-th the corresponding values of the digits of numbers are written

and in the digits from (2 n − i +2)-th to (3 n − i +1)-th the values of the digits of numbers t _{i -2} are written.

Implementation of the invention

Pipeline calculator works as follows (see Fig. 1).

In the initial state, the parallel registers 1.1 ÷ 1. n −1 are set to zero. The clock input 9 of the device receives clock pulses. The first information inputs 5 of the device and the second information inputs 6 of the device with each clock pulse are supplied with the numbers A _j and B _j for which it is necessary to calculate the product C _j modulo P . The inverse code of the module P is fed to the third information inputs 7 of the device during the entire cycle of creating works. The product C _j modulo P numbers A _j and B _j is removed from the information outputs 8 of the device.

mod P. Умножители на два по модулю 3.1 ÷ 3.n–1 могут быть реализованы в соответствии с [1].On the first cycle of the device, the first two numbers A ₁ and B ₁ are written to the parallel register 1.1. In this case, the value of the least significant digit a _0.1 of the first number A ₁ from the outputs of the parallel register 1.1 is fed to the control input of the first key 2.1, and the remaining values ( a _1,1 , …, a _{n −1,1} ) of the digits of the first number A ₁ are received to (1, …, n − 1)-th bits of the information inputs of the second parallel register 1.2. The information inputs of the first key 2.1 and the first information inputs of the first multiplier by two modulo 3.1 with ( n +1, ..., 2 n )-bits of the information outputs of the first parallel register 1.1 receives the code of the first number B ₁ . In accordance with (23), at the output of the first key 2.1, the product t _0.1 = a _0.1 B ₁ is formed, and in accordance with (22), at the output of the first multiplier by two modulo 3.1, the number

mod P . Multipliers by two modulo 3.1 ÷ 3. n –1 can be implemented in accordance with [1].

а в (2n, …, 3n−1)-е разряды записывается значение числа t _0,1. С выхода первого разряда второго параллельного регистра 1.2 значение (a _1,1)-го разряда первого числа A ₁, поступает на управляющий вход второго ключа 2.2. Значения (a _2,1, …, a _{n −1,1}) разрядов первого числа A ₁ с (2, …, n−1)-х разрядов информационных выходов второго параллельного регистра 1.2 поступают на (1, …, n−2)-е разряды информационных входов третьего параллельного регистра 1.3. Значение числа

с (n, …, 2n−1)-х разрядов информационных выходов второго параллельного регистра 1.2 поступает на информационные входы второго ключа 2.2 и на первые информационные входы второго умножителя на два по модулю 3.2. Значение числа t _0,1 с (2n, …, 3n−1)-х разрядов информационных выходов второго параллельного регистра 1.2 поступает на первые информационные входы первого сумматора по модулю 4.1, на вторые информационные входы которого поступает значение

а на информационных выходах образуется значение числа t _1,1 в соответствии с (29), которое поступает на (2n−1, …, 3n)-е разряды информационных входов третьего параллельного регистра 1.3, на (n−1, …, 2n−2)-е разряды которых поступает значение числа

в соответствии с (28). Сумматоры по модулю 4.1 ÷ 4.n–1 могут быть реализованы согласно [4].On the second cycle of device operation, the (1, …, n −1)-th bits of the information inputs of the second parallel register 1.2 are filled with the values ( a _1,1 , …, a _{n −1,1} ) of the bits of the first number A ₁ , in ( n , …, 2 n −1)-th digits the value of the number is written

and in (2 n , …, 3 n −1)-th digits the value of the number t _0.1 is written. From the output of the first digit of the second parallel register 1.2 value ( a _1,1 )-th digit of the first number A ₁ is supplied to the control input of the second key 2.2. Values ( a _2,1 , …, a _{n −1,1} ) bits of the first number A ₁ with (2, …, n −1)-th bits of the information outputs of the second parallel register 1.2 are sent to (1, …, n −2 )-th bits of information inputs of the third parallel register 1.3. Number value

with ( n , ..., 2 n −1)-th bits of the information outputs of the second parallel register 1.2 is supplied to the information inputs of the second key 2.2 and to the first information inputs of the second multiplier by two modulo 3.2. The value of the number t _0.1 s (2 n , ..., 3 n −1)-th bits of the information outputs of the second parallel register 1.2 is supplied to the first information inputs of the first adder modulo 4.1, the second information inputs of which receive the value

and the value of the number t _1.1 is formed at the information outputs in accordance with (29), which goes to (2 n −1, …, 3 n )-th bits of the information inputs of the third parallel register 1.3, to ( n −1, …, 2 n − 2)-th bits of which the value of the number comes

according to (28). Adders modulo 4.1 ÷ 4. n –1 can be implemented according to [4].

Also on the second cycle of the device, the second two numbers A ₂ and B ₂ are written to the parallel register 1.1. In this case, the value of the least significant bit a _0.2 of the second number A ₂ from the outputs of the parallel register 1.1 is fed to the control input of the first key 2.1, and the remaining values ( a _1.2 , ..., a _{n −1.2} ) of the digits of the second number A ₂ are received to (1, …, n − 1)-th bits of the information inputs of the second parallel register 1.2. The information inputs of the first key 2.1 and the first information inputs of the first multiplier by two modulo 3.1 with ( n +1, ..., 2 n )-bits of the information outputs of the first parallel register 1.1 receives the code of the second number B ₂ . In accordance with (25), at the output of the first key 2.1, the product t _0.2 = a _0.2 B ₂ is formed, and in accordance with (24), at the output of the first multiplier by two modulo 3.1, the number

On the following cycles, the operation of the device is carried out in a similar way.

On the nth cycle of the device operation, at the information outputs 8 of the device, in accordance with (34), for pairs of numbers A ₁ and B ₁ , the value t _{n − 1.1} will be obtained, which will be the desired product

On the ( n +1)-th cycle of the device operation, at the information outputs 8 of the device for pairs of numbers A ₂ and B ₂ , in accordance with (36), the value t _{n − 1.2} will be obtained, which will be the desired product

On the ( n + j )th cycle of the device operation, at the information outputs 8 of the device for pairs of numbers A _j and B _j in accordance with (36) the value t _{n − 1 will be obtained, j} which will be the desired product

The invention allows in the pipeline mode to carry out modulo multiplication of the numbers coming to its input.

(хотя фактически T_пр>T_из), получим выигрыш B в быстродействии для указанных условий вычислений Let's compare the speed of calculating the products of numbers of the prototype device [3] and the proposed device when implementing the operation of calculating products for 100 pairs of 16-bit numbers. The prototype device, when implemented to work with 16-bit numbers, will contain 8 consecutive conversion steps. Denote by T _pr - the time of calculation at one stage of the transformation. Provided that the calculation of the next product of numbers cannot be started until the current calculation is completed, the time taken by the prototype device to calculate the product of 100 pairs of 16-bit numbers will be 800 T _pr . The proposed device for performing a similar task will contain 16 successive stages of the conveyor. Let us denote by T _out the time of information processing by one stage of the conveyor. Then the total time for calculating the product of 100 pairs of 16-bit numbers will be 132 T _of . Assuming

(although in fact T _pr >T _from ), we get a gain B in speed for the specified calculation conditions

Thus, when organizing sequential calculations of the products of 100 pairs of 16-bit numbers in the pipeline mode, the speed gain of the claimed device compared to the prototype device will be 6 times. Obviously, with an increase in the bit depth and an increase in the number of numbers, the gain will only increase.

Information sources

1. Patent for invention RU 2015537 C1. IPC G06F 7/49 (1990.01). Multiplier by two modulo. Published 06/30/1994.

2. Patent for invention RU 2316042 C1. IPC G06F 7/523 (2006.01), G06F 7/72 (2006.01). A device for multiplying numbers modulo arbitrary. Published on 01/27/2008. Bull. No. 3.

3. Patent for invention RU 2751802 C1. IPC G06F 7/72 (2006.01), G06F 7/523 (2006.01). Modulo multiplier. Published on 19.07.2021 Bull. No. 20.

4. Patent for invention RU 2032934 C1. IPC G06F 7/49 (1995.01). Modulo adder. Published 04/10/1995.

Claims (1)

Modulo pipeline multiplier containing n keys, where n is the number of bits being processed, the first information inputs of the device, the second information inputs of the device, the third information inputs of the device, the information outputs of the device, the code of the multiplier is fed to the first information inputs of the device, the code of the multiplier is fed to the second information inputs of the device multiplier code, the inverse code of the module is fed to the third information inputs of the device, the code of the product of numbers modulo is removed from the information outputs of the device, which differs in that it contains n parallel registers, ( n − 1) multipliers by two modulo, ( n − 1 ) modulo adders, the clock input of the device, which is connected to the clock inputs of n parallel registers, the first information inputs of the device are connected to (1, ..., n)-bits of the information inputs of the first parallel register, the second information inputs of the device are connected to ( n +1, ..., 2 n )-bits of the information inputs of the first parallel register, the third information inputs of the device are connected to the second inputs of multipliers by two modulo and to the third inputs of modulo adders, the output of the ( n − 1)-th modulo adder is connected with the information outputs of the device, the first bit of the information outputs of the (1, ..., n )-th parallel registers is connected respectively to the control input of the (1, ..., n )-th keys, (1, ..., n − i +1)-th bits information inputs of i -th parallel registers, i =(2, …, n ), are connected to (2, …, n − i +2)-th bits of information outputs of ( i −1)-th parallel registers, ( n − i +2, …, 2 n − i +1)-th bits are connected to information outputs of ( i -1)-th multipliers by two modulo, (2 n , …, 3 n −1)-th bits of information inputs of the second parallel register are connected to the outputs of the first key, and (2 n - i +2, ..., 3 n - i + 1)-th bits of information inputs of the (3, ..., n )-th parallel registers with outputs (1, ..., n - 2)-th adder modulo, (2, ..., n + 1)-th bit of the information outputs of the n -th parallel register is connected to the information inputs of the n -th key, (2 n−i +2, ..., 3 n-i +1) -th bits of the information outputs of the i -th parallel registers are connected to the first information inputs of ( i −1)-th adders modulo, the second information inputs of which are connected to the information outputs of the i -th keys, ( n−i +2, ..., 2 n −i +1)-th bits, i =(1, …, n ), information outputs of the (1, …, n −1)-th parallel registers are connected respectively with information inputs of the (1, …, n −1)-th keys and with the first inputs of the (1, …, n − 1)th multipliers by two modulo.

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