RU2796555C1 - Computing device - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: digital computing devices, digital signal processing devices, cryptographic applications, as well as devices for generating code sequences, the construction of which is based on the theory of finite fields. The device contains two n/2 - bit shift registers, a quotient and remainder formation unit containing three adders, a four-input multiplexer, a remainder code register, two n/2 - bit shift registers.

EFFECT: increasing the speed of the formation of the remainder of the modulo number and the incomplete quotient.

1 cl, 3 dwg, 2 tbl

Description

The invention relates to computer technology and can be used in digital computing devices, digital signal processing devices, in cryptographic applications, as well as in devices for generating code sequences, the construction of which is based on the theory of finite fields.

Known computing device [1], containing adders and multiplexers, allowing you to form the remainder of the number modulo and incomplete quotient. It is also known a device for forming a remainder modulo an arbitrary number [2], containing a register and a unit for generating a quotient and a remainder, allowing you to form a remainder modulo a number and an incomplete quotient.

The disadvantages of these devices are a large amount of equipment.

The closest in technical essence to the claimed invention is a computing device [3], containing an n - bit shift register, a unit for generating a quotient and a remainder, consisting of one ( n -1) - bit register, one ( n -1) - bit shift register , n -bit adder and multiplexer.

The disadvantage of this device is the low speed.

The technical result of the invention is to increase the speed of the formation of the remainder of the number modulo and partial quotient.

To achieve a technical result in a computing device containing a number code register, a quotient and remainder generation unit containing the first adder, a remainder code register, an incomplete quotient code register, number code inputs, module inverse code inputs, remainder code outputs, partial quotient code outputs, calculation start input, clock pulse supply input, moreover, number code inputs are connected to information inputs of the number code register, the first information inputs of the quotient and remainder generation unit are connected to the module inverse code inputs, the first information outputs are connected to the device remainder code outputs, the second information outputs are connected with the code outputs of the partial partial device, the first control input is connected to the clock input of the device, the outputs of the remainder code register are connected to the first information outputs of the partial and remainder generation unit, the incomplete private register outputs are connected to the second information outputs of the partial and remainder formation unit, the second information the inputs of the first adder are connected to the first information inputs of the quotient and remainder formation unit, a logical unit signal is applied to the transfer input, the first control input of the remainder code register is connected to the first control input of the quotient and remainder formation unit, the number code register is made in the form of two n / 2 - bit shift registers, two adders, a four-input multiplexer are introduced into the quotient and remainder formation unit, and the remainder code register is made in the form of two n / 2 - bit shift registers, and the four-input multiplexer contains three inverters, three AND elements, four keys, a block of elements OR, two OR elements, while the even bits of the device number code input are connected to the information inputs of the first n /2 - bit shift register, and the odd bits are connected to the information inputs of the second n /2 - bit shift register, the clock input of the device is connected to the first control inputs of the first and second n /2 - bit shift registers, the input of the beginning of the calculation of the device is connected to the second control inputs of the first and second n /2 - bit shift registers and with the second control input of the quotient and remainder formation unit, the second and third information inputs of which are connected respectively to the inputs of the inverse doubled code of the device module and to the inputs of the inverse tripled code of the device module, the output of the most significant bit of the first n /2 - bit shift register is connected to the fourth information input of the quotient and remainder formation unit, and the output of the most significant bit of the second n /2 - bit the shift register is connected to the fifth information input of the quotient and remainder generation unit, the second information inputs of the second and third adders are connected respectively to the second and third information inputs of the quotient and remainder formation unit, the information outputs of the remainder code register are connected to the first information output of the quotient and remainder formation unit, and with a shift by two digits towards the senior with the first information inputs of the four-input multiplexer and the first, second and third adders, the information outputs of which are connected respectively to the second, third and fourth information inputs of the four-input multiplexer, and the transfer outputs are connected respectively to its first, second and third control inputs, a logical unit signal is applied to the transfer inputs of the second and third adders, the first two least significant bits of the first information inputs of the four-input multiplexer, the first information inputs of the first, second and third adders are connected to the fourth and fifth information inputs of the quotient and remainder formation unit, the first information outputs of the four-input multiplexer are connected to the information inputs of the remainder code register, the second and third information outputs are connected to the lower bits of the information inputs of the third and fourth n /2 - bit shift registers, respectively, the first control inputs of which are connected to the first control input of the quotient and remainder formation unit, and the second the control inputs are connected to the second control input of the quotient and remainder formation block and the second control input of the remainder code register, the information outputs of the third n /2 - bit shift register are connected by even bits of the second information outputs of the quotient and remainder formation block, and the information outputs of the fourth n /2 - of the bit shift register are connected to the odd bits of its second information output, the first control input of the four-input multiplexer is connected to the input of the first inverter and the first input of the second AND element, the second control input is connected to the input of the second inverter and to the first input of the third AND element, the third control input is connected to input of the third inverter, with the control input of the fourth key and with the first inputs of the first and second elements OR, the output of the first inverter is connected to the first input of the first element AND, the output of the second inverter is connected to the second inputs of the first and second elements AND, the output of the third inverter is connected to the third inputs of the first and second AND elements and with the second input of the third AND element, the output of the first AND element is connected to the control input of the first key, the output of the second AND element is connected to the control input of the second key and to the second input of the first OR element, the output of the third AND element is connected to the control input of the third key and with the second input of the second OR element, the information inputs of the first, second, third and fourth keys are connected to the first, second, third and fourth information inputs of the four-input multiplexer, respectively, and the outputs are connected to the first, second, third and fourth inputs, respectively, of the block of OR elements , the outputs of which are connected to the first information outputs of the four-input multiplexer, the output of the first OR element is connected to the second information output of the four-input multiplexer, and the output of the second OR element is connected to its third information output.

The essence of the invention lies in the implementation of the following method for calculating the remainder R and partial quotient Q of the number A modulo P . Let

where A is a positive integer from which it is necessary to calculate the remainder;

P is a positive integer called the modulus;

Q is a positive integer that is the incomplete quotient of dividing A by P ;

R is a positive integer that is the remainder of dividing A by P .

And

– коэффициенты, принимающие значение 0 или 1 в зависимости от значения числа A; where a _i ,

- coefficients that take the value 0 or 1 depending on the value of the number A ;

– коэффициенты, принимающие значение 0 или 1 в зависимости от значения модуля P; p _i ,

– coefficients that take the value 0 or 1 depending on the value of the module P ;

– коэффициенты, принимающие значение 0 или 1 в зависимости от значения неполного частного Q; q _i ,

- coefficients that take the value 0 or 1 depending on the value of the partial quotient Q ;

– коэффициенты, принимающие значение 0 или 1 в зависимости от значения остатка R; r _i ,

– coefficients that take the value 0 or 1 depending on the value of the remainder R ;

n is the number of digits in the representation of numbers.

The task is to find the remainder R and the incomplete quotient Q from the known A and P. The remainder R is, in terms of number theory, the residue of the number A modulo P , so we say that A is congruent with R :

The value of the remainder R can be calculated as follows:

Let us rewrite expression (2) in the following form by combining two neighboring terms:

, принимает только четные значения:From each sum in brackets in expression (8), we take 2 ⁱ out of brackets, where

, takes only even values:

, принимает только четные значения.In expression (9) before each of n /2 formed sums of the form ( a _{i +1} 2+ a _i ), we obtain a factor 2 ⁱ , where

, takes only even values.

Next, we take out the smallest nonzero power 2 in (9):

Performing successively the transformation (10) ( n /2)-2 times we get:

where 2 ² occurs ( n /2)-1 times.

Then expression (7) can be represented as follows:

It is known from number theory that the modulo reduction operation is invariant to addition and multiplication, i.e. the value of the remainder does not depend on whether it is calculated from the sum (product) or from each term (factor), then the corresponding partial remainders can be summed (multiplied) and the modulo remainder is calculated from the result.

Based on the foregoing, expression (12) can be calculated as follows.

First, on the first cycle, the value is calculated

On the second cycle, the value is calculated

On the third cycle, the value is calculated

On the last n /2-th cycle, the value is calculated

which is the required remainder R of the number A modulo P .

The operation of reduction modulo P at each stage of the transformation is performed on the basis of the following considerations.

By definition, the value of t _{i -1} lies in the range 0≤ t _{i -1} ≤ P -1, therefore, in accordance with expressions (13)-(15), the value

before bringing it modulo can take values in the range from 0 to 4 P -1. Modulo reduction of the value t _i is carried out according to the following rules

The digits of the partial quotient Q at each stage of the calculations take values in accordance with Table 1.

Table 1.

senior rank junior rank Value t _i 0 0 0 ≤ t _i < P 0 1 P ≤ t _i < 2 P 1 0 2 P ≤ t _i < 3 P 1 1 3 P ≤ t _i < 4 P

The conditions for the value t _i to fall into one of the intervals indicated in Table 1 are determined by the values of the transfer signals at the transfer outputs of the adders that perform the subtraction operation ( t _i - kP ), where k =1, 2, 3 in accordance with Table 2.

Table 2.

t _i t _i – P t _i – 2 P t _i – 3 P 0 ≤ t _i < P 0 0 0 P ≤ t _i < 2 P 1 0 0 2 P ≤ t _i < 3 P 1 1 0 3 P ≤ t _i < 4 P 1 1 1

Thus, if the value of the carry signals is "1" at the carry outputs of all three adders, thent _i (modP)=t _i - 3P, if the value of the carry signals is "1" at the carry outputs of two adders, then
t _i (modP)=t _i - 2P, if the value of the carry signal is "1" at the carry outputs of one adder, thent _i (modP)=t _i -P. If the value of the carry signals is "0" at the carry outputs of all three adders, then
t _i (modP)=t _i , i.e. subtraction operation is not performed.

In FIG. 1 shows a diagram of a computing device.

The computing device contains the first n /2 - bit shift register 1.1, the second n /2 - bit shift register 1.2, the unit for generating the quotient and remainder 2, the inputs of the device number code 3, the inputs of the inverse code of the device module 4, the inputs of the inverse doubled code of the device module 5 , inputs of the inverse tripled code of the device module 6, outputs of the remainder code of the device 7, outputs of the code of an incomplete private device 8, input of the beginning of the calculation of the device 9, input of the clock pulses of the device 10.

The even bits of the input of the device number code 3 are connected to the information inputs of the first n /2 - bit shift register 1.1, the odd bits are connected to the information inputs of the second n /2 - bit shift register 1.2.

The inputs of the inverse code of the device module 4, the inputs of the inverse doubled code of the device module 5 and the inputs of the inverse tripled code of the device module 6 are connected respectively to the first, second and third information inputs of the quotient and remainder 2 generation unit.

The input of the beginning of the calculation of the device 9 is connected to the second control inputs of the first 1.1 and second 1.2 n /2 - bit shift registers and to the second control input of the block for forming the quotient and the remainder 2. The clock input of the device 10 is connected to the first control inputs 1.1 and the second 1.2 n /2 - bit shift registers and with the first control input of the block for the formation of quotient and remainder 2.

The first information outputs of the quotient and remainder 2 generation unit are connected to the device 7 remainder code outputs, the second information outputs are connected to the incomplete private device 8 code outputs.

The output of the most significant bit of the first n /2 - bit shift register 1.1 is connected to the fourth information input of the quotient and remainder formation unit 2, and the output of the most significant bit of the second n /2 - bit shift register 1.2 is connected to the fifth information input of the quotient and remainder formation unit 2.

In FIG. 2 shows a block diagram for the formation of quotient and remainder 2.

The quotient and remainder forming unit 2 contains three adders 11.1, 11.2 and 11.3, a four-input multiplexer 12, a remainder code register 13, two n /2 bit shift registers 14.1 and 14.2.

The second information inputs of the first 11.1, second 11.2 and third 11.3 adders are connected respectively to the first, second and third information inputs of the quotient and remainder 2 generation unit.

The outputs of the remainder code register 13 are connected to the first information output of the quotient and remainder 2 generation unit and with a two-bit shift towards the older one with the first information inputs of the four-input multiplexer 12 and the first 11.1, the second 11.2 and the third 11.3 adders, the information outputs of which are connected respectively to the second , third and fourth information inputs of the four-input multiplexer 12, and the transfer outputs are connected to its first, second and third control inputs, respectively.

The transfer inputs of the first 11.1, second 11.2 and third 11.3 adders are fed a logical unit signal.

The first two least significant bits of the first information inputs of the four-input multiplexer 12, the first information inputs of the first 11.1, the second 11.2 and the third 11.3 adders are connected to the fourth and fifth information inputs of the quotient and remainder 2 generation unit.

The first information outputs of the four-input multiplexer 12 are connected to the information inputs of the remainder code register 13, the second and third information outputs are connected to the lower bits of the information inputs of the third 14.1 and fourth 14.2 n /2 bit shift registers, respectively, the first control inputs of which are connected to the first control input of the block quotient and remainder 2 formation and the first control input of the remainder code register 13, and the second control inputs are connected to the second control input of the quotient and remainder 2 generation unit and the second control input of the remainder code register 13.

The information outputs of the third n /2 - bit shift register 14.1 are connected by even bits of the second information outputs of the quotient and remainder 2 generation unit, and the information outputs of the fourth n /2 - bit shift register 14.2 are connected to the odd bits of its second information output.

In FIG. 3 shows a diagram of a four-input multiplexer 12.

The four-way multiplexer 12 contains three inverters 15.1, 15.2 and 15.3, three AND elements 16, 17 and 18, four keys 19.1, 19.2, 19.3 and 19.4, a block of OR elements 20, two OR elements 21.1 and 21.2.

The first control input of the four-input multiplexer 12 is connected to the input of the first inverter 15.1 and the first input of the second element And 17, the second control input is connected to the input of the second inverter 15.2 and the first input of the third element And 18, the third control input is connected to the input of the third inverter 15.3, with the control input of the fourth key 19.4 and with the first inputs of the first 21.1 and second 21.2 elements OR.

The output of the first inverter 15.1 is connected to the first input of the first element And 16, the output of the second inverter 15.2 is connected to the second inputs of the first 16 and second 17 elements And, the output of the third inverter 15.3 is connected to the third inputs of the first 16 and second 17 elements And, as well as to the second input third element AND 18.

The output of the first element And 16 is connected to the control input of the first key 19.1, the output of the second element And 17 is connected to the control input of the second key 19.2 and to the second input of the first element OR 21.1, the output of the third element And 18 is connected to the control input of the third key 19.3 and to the second input second element OR 21.2.

The information inputs of the first 19.1, second 19.2, third 19.3 and fourth 19.4 keys are connected to the first, second, third and fourth information inputs of the four-input multiplexer 12, respectively, and the outputs are connected to the first, second, third and fourth inputs, respectively, of the block of elements OR 20, the outputs of which are connected with the first information outputs of the four-input multiplexer 12.

The output of the first element OR 21.1 is connected to the second information output of the four-input multiplexer 12, and the output of the second element OR 21.2 is connected to its third information output.

The computing device operates as follows (see Fig. 1).

, поступая далее на первые информационные входы блока 2 формирования частного и остатка. На входы инверсного удвоенного кода модуля 5 устройства подается инверсный удвоенный код модуля

, поступая далее на вторые информационные входы блока 2 формирования частного и остатка. На входы инверсного утроенного кода модуля 6 устройства подается инверсный утроенный код модуля

, поступая далее на третьи информационные входы блока 2 формирования частного и остатка.The binary code of the number 3 is fed to the inputs of the number 3 code of the deviceA, from which it is necessary to form the remainderRand incomplete quotientQ moduloP. The inverse code of the module is fed to the inputs of the inverse code of module 4 of the device

, proceeding further to the first information inputs of block 2 for the formation of the quotient and the remainder. The inverse doubled code of the module 5 of the device is fed to the inputs of the inverse doubled code of the module

, proceeding further to the second information inputs of the block 2 forming the quotient and the remainder. The inverse triple code of the module 6 of the device is fed to the inputs of the inverse triple code of the module

, proceeding further to the third information inputs of block 2 for the formation of the quotient and the remainder.

Then, a signal is applied to the input of the beginning of the calculation of the device 9, under the influence of which even bits of the binary code of the number A are written to the first n /2 - bit shift register 1.1, and odd bits of the binary code of the number A are written to the second n /2 - bit shift register 1.2. Under the influence of the same signal, the remainder code register 13, the third 14.1 and the fourth 14.2 n /2 - the bit shift registers of the block 2 for the formation of the quotient and the remainder are set to the zero state.

First, on the first cycle of the device operation, the fourth information input of block 2 for forming the quotient and the remainder from the output of the highest digit of the first n /2 - bit shift register 1.1 receives the value of the ( a _{n -1} )-th digit of the number A , and the fifth information input from the output the most significant bit of the second n /2 - bit shift register 1.2 receives the value of ( a _{n -2} )-th bit of the number A . In block 2 of forming the quotient and the remainder, the value t ₁ =( a _{n -1} 2+ a _{n -2} ) mod P and bits q _{n -1} and q _{n -2} of the partial quotient are formed, which are written in the lower digits of the third 14.1 and fourth 14.2 n /2 - bit shift registers, respectively.

On the second cycle of operation of the device, the value of the ( a _{n -3} )-th bit of the number A arrives at the fourth information input of block 2 for forming the quotient and the remainder from the output of the highest digit of the first n /2 - bit shift register 1.1 , and the fifth information input from the output of the highest bit of the second n /2 - bit shift register 1.2 receives the value of ( a _{n -4} )-th bit of the number A . In block 2 of forming the quotient and the remainder, the value is formed
t ₂ =(2 ² t ₁ +( a _{n -3} 2+ a _{n -4} )) mod P and digits q _{n -3} and q _{n -4} of the incomplete quotient. In this case, the bits q _{n -1} and q _{n -2} of the incomplete quotient are shifted by one bit towards the older ones in the third 14.1 and fourth 14.2 n / 2 - bit shift registers, respectively, and the bits q _{n -3} and q _{n -4} incomplete quotient.

On the last n /2-th cycle of the device operation, the fourth information input of the block 2 for forming the quotient and the remainder from the output of the most significant bit of the first n /2 - bit shift register 1.1 receives the value a of the _1st bit of the number A , and the fifth information input from the output the most significant bit of the second n /2 - bit shift register 1.2 receives the value a of _{the 0} -th bit of the number A . In block 2 of forming the quotient and the remainder, the value t _{n /2} =(2 ² t _{n /2-1} +( a ₁ 2+ a ₀ )) mod P is formed, which is the desired remainder R of the number A modulo P , and bits q ₁ and q ₀ of the incomplete quotient are also formed. In this case, the value t _{n /2} will be written to the register 13 of the remainder code and will go to the outputs 7 of the remainder code of the device, the even bits of the partial quotient will be written to the third 14.1 n /2 - bit shift register, and the odd bits of the incomplete quotient will be written to the fourth 14.2 n /2 is a bit shift register and will go to the outputs 8 of the incomplete private device code.

Block 2 of the formation of the private and the remainder works as follows (see Fig. 2).

, инверсный удвоенный код модуля

и инверсный утроенный код модуля

. На входы переноса первого 11.1, второго 11.2 и третьего 11.3 сумматоров подается сигнал логической единицы. В результате первый 11.1, второй 11.2 и третий 11.3 сумматоры выполняют фактически операцию арифметического вычитания из числа, подаваемого на их первые информационные входы, модуля P, 2P или 3P соответственно. В случае, если число на первых информационных входах сумматоров 11.1, 11.2 и 11.3 больше или равно чем число на их вторых информационных входах, то на выходе переноса соответствующего сумматора появляется сигнал логической единицы.The second information inputs of the first 11.1, second 11.2 and third 11.3 adders during the entire cycle of calculating the remainder R and partial quotient Q from the number A modulo P from the first, second and third information inputs of the block 2 forming the quotient and the remainder are fed, respectively, the inverse code of the module

, inverse double module code

and inverse triple module code

. The transfer inputs of the first 11.1, second 11.2 and third 11.3 adders are fed a logical unit signal. As a result, the first 11.1, second 11.2 and third 11.3 adders actually perform the operation of arithmetic subtraction from the number supplied to their first information inputs, module P , 2 P or 3 P respectively. If the number at the first information inputs of the adders 11.1, 11.2 and 11.3 is greater than or equal to the number at their second information inputs, then a logical one signal appears at the transfer output of the corresponding adder.

On the first cycle of operation of the device from the fourth and fifth information inputs of the block 2 for forming the quotient and the remainder of the value of the ( a _{n -1} )-th and ( a _{n -2} )-th digit of the number A are fed to the lower digits of the first information inputs of the four-input multiplexer 12, the first 11.1, second 11.2 and third 11.3 adders. The second, third and fourth information inputs of the four-input multiplexer 12, from the information outputs of the first 11.1, the second 11.2 and the third 11.3 adders, respectively, receive the values ( a _{n -1} 2+ a _{n -2} ) - P , ( a _{n -1} 2+ a _{n -2} )-2 P and ( a _{n -1} 2+ a _{n -2} )-3 P , and the first, second and third control inputs from the transfer outputs of the first 11.1, second 11.2 and third 11.3 adders receive respectively the values of the transfer signals . The first information outputs of the four-input multiplexer 12 will be the value
t ₁ =( a _{n -1} 2+ a _{n -2} ) mod P , which, under the influence of a clock pulse from the first control input of the block 2 for forming the quotient and the remainder, will be written to the remainder code register 13, and the second and third information outputs will bits q _{n -1} and q _{n -2} of the incomplete quotient are formed, which, under the influence of the same clock pulse, will be written to the lower digits of the third 14.1 and fourth 14.2 n /2 - bit shift registers.

On the second cycle of operation of the device on the first information inputs of the four-input multiplexer 12, the first 11.1, the second 11.2 and the third 11.3 adders, the value 2 ² t ₁ +( a _{n -3} 2+ a _{n -4} ) will be generated, and the value t ₁ will come from the output of the register code of the remainder 13 with a shift of two bits in the direction of the senior, and the values of a _{n -3} ·and a _{n -4} go to the low bits from the fourth and fifth information inputs of the block 2 of the formation of private and remainder. As a result of summation on the second, third and fourth information inputs of the four-input multiplexer 12 will be the values 2 ² t ₁ +( a _{n -3} 2+ a _{n -4} )- P , 2 ² t ₁ +( a _{n -3} 2+ a _{n -4} )-2 P and
2 ² t ₁ +( a _{n -3} 2+ a _{n -4} )-3 P respectively, and the first, second and third control inputs will be the transfer signals from the transfer outputs of the first 11.1, second 11.2 and third 11.3 adders. The four-input multiplexer 12, in accordance with the logic of its operation, will generate at its first information outputs the value t ₂ =(2 ² t ₁ +( a _{n -3} 2+ a _{n -4} )) mod P , which, under the influence of a clock pulse from the first control input block 2 forming the private and the remainder will be written to the remainder code register 13, and the second and third information outputs will generate digits q _{n -3} and q _{n -4} of the incomplete quotient, which, under the influence of the same clock pulse, will be written to the lower digits of the third 14.1 and fourth 14.2 n /2 - bit shift registers. In this case, the bits q _{n -1} and q _{n -2} of the incomplete quotient in the third 14.1 and fourth 14.2 n /2 - bit shift registers, respectively, will be shifted by one towards the older ones.

On the last n /2-th cycle of operation of the device on the first information inputs of the four-input multiplexer 12, the first 11.1, the second 11.2 and the third 11.3 adders will generate the value
2 ² t _{n /2-1} +( a ₁ 2+ a ₀ ), moreover, the value t _{n /2-1} will come from the output of the remainder code register 13 with a two-digit shift towards higher ones, and the values a ₁ and a ₀ will go to the least significant digits from the fourth and fifth information inputs of the block 2 for the formation of the quotient and the remainder. As a result of summation on the second, third and fourth information inputs of the four-input multiplexer 12, there will be values 2 ² t _{n /2-1} +( a ₁ 2+ a ₀ )- P , 2 ² t _{n /2-1} +( a ₁ 2+ a ₀ )-2 P and 2 ² t _{n /2-1} +( a ₁ 2+ a ₀ )-3 P respectively, and the first, second and third control inputs will contain the transfer signals from the transfer outputs of the first 11.1 , second 11.2 and third 11.3 adders. The four-input multiplexer 12, in accordance with the logic of its operation, will generate at its first information outputs the value t _{n /2} =(2 ² t _{n /2-1} +( a ₁ 2+ a ₀ ))mod P , which, under the influence of a clock pulse from the first of the control input of block 2 for the formation of a private and the remainder will be written to the register of the remainder code 13, and on the second and third information outputs bits q ₁ and q ₀ of an incomplete private will be generated, which, under the influence of the same clock pulse, will be written to the lower digits of the third 14.1 and fourth 14.2 n /2 - bit shift registers with a simultaneous shift of previously recorded bits by one in the direction of the older ones.

As a result, after the n /2th cycle of operation, at the first information outputs of block 2 for the formation of the quotient and the remainder, the remainder code R from the number A modulo P will be generated, and at the second information outputs, the incomplete quotient Q .

Four-input multiplexer 12 operates as follows (see Fig. 3).

, на первом информационном входе четырехвходового мультиплексора 12 образуется значение t _i =2² t _{i -1}+(a _{n -2 i -1} ·2+a _{n -2 i} ), на втором, третьем и четвертом информационных входах образуются значения t _i -P, t _i -2P и t _i -3P соответственно, при этом t ₀=0.On the i -th cycle of the device, where

, at the first information input of the four-input multiplexer 12 the value t _i =2 ² t _{i -1} +( a _{n -2 i -1} 2+ a _{n -2 i} ) is formed, at the second, third and fourth information inputs the values t _i - P , t _i -2 P and t _i -3 P respectively, while t ₀ =0.

The control signals of the four-input multiplexer 12 open one of the keys 19.1-19.4.

If the control signal appears on all three control inputs of the four-input multiplexer 12, then the fourth key 19.4 will be open. The control signal from the third control input will open the fourth key 19.4 and through the third inverter 15.3 in the form of a logical zero will go to the third inputs of the elements 16 and 17 And, as well as to the second input of the element And 18, prohibiting the passage of control signals from their first inputs to their outputs. As a result, the first 19.1, the second 19.2 and the third 19.3 keys will be closed and the output of the four-input multiplexer 12 will receive the value t _i -3 P from its fourth information inputs.

If the control signal appears on the first and second control inputs of the four-input multiplexer 12, then in the same way only the third 19.3 will be open, and the first 19.1, the second 19.2 and the fourth keys 19.4 will be closed. As a result, the output of the four-input multiplexer 12 will receive the value t _i -2 P from its third information inputs.

If the control signal appears only on the first control input of the four-input multiplexer 12, then in the same way only the second key 19.2 will be open, and the first 19.1, third 19.3 and fourth 19.4 keys will be closed. As a result, the output of the four-input multiplexer 12 will receive the value t _i - P from its second information inputs.

If there are only zero signals at the control inputs of the four-input multiplexer 12, then they, coming through the inverters 15.1-15.3 and the first element And 16, open the first key 19.1 and the output of the four-input multiplexer 12 will receive the value t _i from its first information inputs.

The values from the outputs of the keys 19.1-19.4 are fed through the block of elements OR 20 to the first information outputs of the four-input multiplexer 12.

As a result, the value (2 ² t _{i -1} +( a _{n -2 i -1} · 2+ a _{n -2 i} )) mod P is always formed at the first information output of the four-input multiplexer 12 .

The digits of the partial partial Q are formed on the second and third information outputs of the four-input multiplexer 12 using the first 21.1 and second 21.2 OR elements in accordance with the logic of tables 1 and 2.

Technical and economic efficiency of the invention is to increase the speed of the formation of the remainder of the number modulo and partial quotient. So the prototype device calculates the remainder of the n - bit number for an arbitrary n - bit module for n cycles of work. The invention performs a similar calculation for n /2 cycles of work due to the parallel processing of even and odd digits of the input number. In this case, the speed increase will occur in 2 times.

Information sources

1. Petrenko V.I., Sidorchuk A.V. Computing device // Patent of Russia No. 2348965. Published 03/10/2009. Bull. No. 7.

2. Petrenko V.I., Chipiga A.F. A device for forming the remainder modulo an arbitrary number. Russian patent No. 2012137. Published 04/30/1994.

3. Petrenko V.I. Computing device // Patent of Russia No. 2661797. Published 07/19/2018. Bull. No. 20.

Claims (1)

A computing device containing a number code register, a quotient and remainder generating unit, containing a first adder, a remainder code register, an incomplete quotient code register, number code inputs, module inverse code inputs, remainder code outputs, partial quotient code outputs, calculation start input, input supply of clock pulses, moreover, the number code inputs are connected to the information inputs of the number code register, the first information inputs of the quotient and remainder generation unit are connected to the module inverse code inputs, the first information outputs are connected to the device remainder code outputs, the second information outputs are connected to the partial quotient code outputs device, the first control input is connected to the clock input of the device, the outputs of the remainder code register are connected to the first information outputs of the quotient and remainder generation unit, the outputs of the partial quotient register are connected to the second information outputs of the quotient and remainder formation unit, the second information inputs of the first adder are connected to the first information inputs of the quotient and remainder formation block, a logical unit signal is applied to the transfer input, the first control input of the remainder code register is connected to the first control input of the quotient and remainder formation block, characterized in that the number code register is made in the form of two n / 2 - bit shift registers, two adders, a four-input multiplexer are introduced into the quotient and remainder formation unit, and the remainder code register is made in the form of two n / 2 - bit shift registers, and the four-input multiplexer contains three inverters, three AND elements, four keys, a block of OR elements, two OR elements, while the even bits of the device number code input are connected to the information inputs of the first n/2 bit shift register, and the odd bits are connected to the information inputs of the second n/2 bit shift register, the device clock input is connected to the first control inputs of the first and second n/2 - bit shift registers, the input of the beginning of the calculation of the device is connected to the second control inputs of the first and second n/2 - bit shift registers and to the second control input of the quotient and remainder formation unit, the second and third information inputs of which are connected respectively with the inputs of the inverse doubled code of the device module and with the inputs of the inverse tripled code of the device module, the output of the high order bit of the first n/2 bit shift register is connected to the fourth information input of the quotient and remainder formation unit, and the high bit output of the second n/2 bit shift register is connected to the fifth information input of the quotient and remainder generation unit, the second information inputs of the second and third adders are connected to the second and third information inputs of the quotient and remainder formation unit, respectively, the outputs of the remainder code register are connected to the first information output of the quotient and remainder formation unit and with a shift by two digits in the direction of the senior with the first information inputs of the four-input multiplexer and the first, second and third adders, the information outputs of which are connected respectively to the second, third and fourth information inputs of the four-input multiplexer, and the transfer outputs are connected respectively to its first, second and third control inputs, a logical one signal is applied to the transfer inputs of the second and third adders, the first two least significant bits of the first information inputs of the four-input multiplexer, the first information inputs of the first, second and third adders are connected to the fourth and fifth information inputs of the quotient and remainder formation unit, the first information outputs of the four-input multiplexer are connected with the information inputs of the remainder code register, the second and third information outputs are connected to the lower bits of the information inputs of the third and fourth n/2-bit shift registers, respectively, the first control inputs of which are connected to the first control input of the quotient and remainder formation unit, and the second control inputs are connected with the second control input of the quotient and remainder formation block and the second control input of the remainder code register, the information outputs of the third n / 2 - bit shift register are connected by even bits of the second information outputs of the quotient and remainder formation block, and the information outputs of the fourth n / 2 - bit shift register connected to the odd bits of its second information output, the first control input of the four-input multiplexer is connected to the input of the first inverter and the first input of the second AND element, the second control input is connected to the input of the second inverter and to the first input of the third AND element, the third control input is connected to the input of the third inverter , with the control input of the fourth key and with the first inputs of the first and second OR elements, the output of the first inverter is connected to the first input of the first AND element, the output of the second inverter is connected to the second inputs of the first and second AND elements, the output of the third inverter is connected to the third inputs of the first and second elements AND and with the second input of the third element AND, the output of the first element AND is connected to the control input of the first key, the output of the second element AND is connected to the control input of the second key and to the second input of the first element OR, the output of the third element AND is connected to the control input of the third key and with the second input of the second OR element, the information inputs of the first, second, third and fourth keys are connected to the first, second, third and fourth information inputs of the four-input multiplexer, respectively, and the outputs are connected to the first, second, third and fourth inputs, respectively, of the block of OR elements, the outputs which are connected to the first information outputs of the four-input multiplexer, the output of the first OR element is connected to the second information output of the four-input multiplexer, and the output of the second OR element is connected to its third information output.

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