JPH02114324A - Multiplier - Google Patents

Abstract

PURPOSE:To probabilisticly accelerate multiplication by omitting operation for finding out the m-th partial multiplication result when the m-th partial multiplier is decided as all '0's, and shifting the added result up to the (m-1) th partial multiplication to the light only by the number of bits uniformly determined from the bit length of the partial multiplier through an added result shifter. CONSTITUTION:When the m-th partial multiplier inputted from the output of a 1st operand check circuit 5 or a 2nd operand check circuit 14 to partial multiplier registers 3, 4 is decided as all '0's, operation for finding out the m-th partial multiplication result is omitted and the added result up to the (m-1)th partial multiplicand to the right only by the number of bits uniformly determined from the bit length of the partial multiplier through an added result shifter 9 to obtain the added result up to the m-th partial multiplier. Consequently, operation can be probabilisticly accelerated only by the slight increment of hardware.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to multipliers.

[Prior Art] Conventionally, as a configuration of a multiplier, a configuration as shown in FIG. 2, for example, has been used. In FIG. 2, a multiplicand register 16 is a register that stores a multiplicand used in an operation, and a multiplicand register 17 is a register that stores a multiplier. Here, the multiplier stored in the multiplier register 17 is divided into first to first partial multipliers, and sequentially stored in one partial multiplier register from the lower side through the partial multiplier selector 18. The partial product generation circuit 20 generates a required number of partial products using the multiplicand stored in the multiplicand register 16 and the first (1=m≦n) partial multiplier stored in the partial multiplier register 19. By adding them in the partial product addition circuit 21, a partial multiplication result for the first partial multiplier is obtained. At this time, assuming that the cumulative sum register 22 contains the cumulative sum of the partial multiplication results for the first to (m-1)th partial multipliers, the partial multiplication results for the first partial multiplier are Some partial product addition circuit 21
By adding the output of the cumulative sum register 22 output to the right in the shifter 23 (the number of shifts is uniquely determined by the bit width of the partial multiplier) in the cumulative sum circuit 24, the partial multiplication results up to the first are obtained. The cumulative sum result is obtained.

Hereafter, this cumulative sum result is stored in the cumulative sum register 22 again,
At the same time, the operation of storing the next (m+1)th partial multiplier in the partial multiplier register 19 and performing the (m+1)th partial multiplication is repeated. The final multiplication result is the value output from the cumulative sum circuit 24 when the first @th partial multiplier is stored in the partial multiplier register 19. Note that the cumulative sum register 22 must be cleared to zero before starting the calculation.

Further, in each partial multiplier, the upper one bit overlaps with the upper partial multiplier, and the lower one bit overlaps with the lower partial multiplier, and the partial products are generated, for example, as follows. First, if the partial multiplier is MP and MP is 9 bits, then MP can be expressed as follows.

MP” (ao al a2 al aa aq a
6at as )...(1) Here a. overlaps with the least significant bit of the upper partial multiplier,
a8 overlaps with the most significant bit of the lower partial multiplier. If this MP is divided into groups of 3 bits each as shown below...(2) The product of the multiplicand X and MP can be found as the sum of four partial products as shown below.

X-MP-X・((a,+a2-2ao)・2
-'+ (at +aa-2a2)・2-1+ (a
g + 862 a 4) ・24+ (at +a
B -2ab) ・2-1= (a+ + ax
-2ao) ・2-'-X+ (a, +a, -2
a,)-2-j-X+ (a,+a,-2a4),/)
-5,X+ (a, 10as-2a,,)* 2-'e
X...(3) By calculating the partial products using the above method, the formula (3
), when the partial multipliers are all "0" or all "1", the partial multiplication result is always '0'.

In the above example, the bit length of the multiplicand is an odd number, but in the case of an even number of bits, the angle is not necessarily '0° in the case of all "1"s.

[Problems to be Solved by the Invention] When the conventional multiplier described above is used, no matter what the value of the multiplier is, it is possible to divide the multiplier to obtain partial multiplication results for the number of partial multipliers and sum them. The disadvantage is that an arithmetic loop must be executed. However, for example, when the data handled by the multiplier in Figure 2 is integer data, there are relatively many cases where the valid bits of the multiplier data do not exist in the bit width of the multiplier, and in such cases, the upper side of the multiplier is a continuous "0" or "1". Furthermore, when the data handled by the multiplier in Figure 2 is normal floating point data in two's complement format, the lower side of the multiplier is often a continuous 0°. All “Oo” data is in partial multiplier register 1
9, the partial multiplication result output from the partial product addition circuit 21 is always “0” as shown in the conventional example.
I know it will be. Therefore, calculations for all "0" partial multipliers can be omitted.

An object of the present invention is to focus on this point and to speed up multiplication stochastically.

[Means to solve the problem]

Divide into partial multipliers, store these partial multipliers in the partial multiplier register in order from the lower side, and divide the required number of parts from the multiplicand used in the operation and the m-th (1≦m≦n) partial multiplier stored in the partial multiplier register. Generating products and adding the m-th partial multiplication result obtained by adding these partial products to the cumulative sum result of the partial multiplication results obtained from the first to (m-1)th partial multipliers. A multiplier that obtains the product of the multiplier and the multiplicand divides each of the first and second operands used in the operation into n pieces of divided data, and checks whether the divided data are all "0°" or not. The first and second operand check circuits for determination and the outputs of the first and second operand check circuits output the operand with fewer divided data of all "0" among the divided data as the multiplicand. From the outputs of the multiplicand selector and the first and second operand check circuits, all of the divided data are "0".
a partial multiplier selector that selects the operand with more divided data as the multiplier and sequentially selects it as the partial multiplier starting from the lower divided data of the multiplier and outputs it to the partial multiplier register; a sum result shifter, and the m-th partial multiplier input to the partial multiplier register from the output of the first operand check circuit or the second operand check circuit is all "0".
If it is determined that it is not, the m-th partial multiplication result is obtained from the multiplicand selector output and the partial multiplier register output, and is added to the cumulative sum result up to the (m-1)th partial multiplier. The m-th partial multiplier inputted into the partial multiplier register from the output of the first operand check circuit or the second operand check circuit, which is the cumulative sum result up to the m-th partial multiplier, is all "0". If it is determined that It is characterized in that it is shifted to the right by a uniquely determined number of bits from the bit length to obtain the cumulative sum result up to the m-th partial multiplier.

- [Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a multiplier according to an embodiment of the present invention. In FIG. 1, operand input register 1 and operand register 2 each store one of two operands used in an operation. Operand A register 1. The two operands stored in the operand B register 2 are each divided into n pieces of data, and the divided data in the operand input register 1 is sent to the operand A check circuit 5. The divided data of the operand B register 2 are each judged in the operand check circuit 14 to see if they are all "0°" and are reported to the control circuit 6.

The control circuit 6 includes an operand A check circuit 5. It receives the output of the operand B check circuit 14 and gives set instructions to various registers in the multiplier, select signals to various selectors, and shift numbers to various shifters.

The multiplicand selector 15 is controlled by the control circuit 6, and selects the output of the operand A register 1 and the operand register 2, whichever has less divided data of all "0" (if they are equal, the output of the operand A register 1) as the multiplicand. Output. The partial multiplier selector 3 is controlled by the control circuit 6, and selects the output of the operand A register 1 and the operand register 2 which has more divided data of all "0 degrees" (if they are equal, the output of the operand register 2) as the multiplier. Assuming that, the divided data of the selected operand is output to the partial multiplier register 4 in order from the lower-order side.

The partial product generation circuit 7 generates a required number of partial products from the outputs of the multiplicand selector 15 and the partial multiplier register 4, and the partial product addition circuit 8 adds the partial products output from the partial product generation circuit 7 to generate partial products. Output the multiplication result.

The cumulative sum register 10 stores the cumulative sum result of partial multiplication results,
The shifter 11 shifts the output of the accumulation register 10 to the right (the number of shifts is uniquely determined by the bit length of the partial multiplier), and the accumulation circuit 12 adds the output of the partial product addition circuit 8 and the output of the shifter 11. Furthermore, the cumulative sum result selector 9 is connected to the cumulative sum circuit 12.
and the output of the shifter 11, the data to be stored in the cumulative sum register 10 is selected. Note that the cumulative sum register 10
must be cleared to zero before starting the operation.

The operation of the multiplier shown in FIG. 1 will be described below with reference to time charts for various examples of multipliers shown in FIG.

FIG. 3 (1) shows an example in which each partial multiplier is not all "0", partial multipliers are sequentially supplied to the partial multiplier register 4 from the lower side of the multiplier, and the cumulative sum result of the partial multiplication results is stored in the cumulative sum register. 10 is stored. In this example, the cumulative sum result selector 9 always selects the cumulative sum circuit 12 output, and the shifter 1
1, the right shift is performed by the number of shifts for the calculation loop, which is uniquely determined by the bit length of the partial multiplier. Further, the cumulative sum result shifter 13 is in a through state.

FIG. 3 (2) shows an example in which the top two partial multipliers among the multipliers are all "0", and the cumulative sum result selector 9 always selects the output of the cumulative sum circuit 12, and the first partial multiplier When the result is stored in the cumulative sum register 10, the shifter 11 shifts by the number of shifts for one calculation loop, and the cumulative sum result shifter 13 performs a right shift for two calculation loops.
The multiplication result is obtained.

Figure 3 (3) shows an example in which the lower two partial multipliers of the multipliers are all ", 0". ).

Figure 3 (4) is an example where there is a partial multiplier that is all "0" as part of the multiplier, and the calculations up to the second partial multiplier are the same as in Figure 3 (1), but the third The operation for the partial multiplier is omitted, and the cumulative sum result to be added to the partial multiplication result for the fourth partial multiplier is data obtained by shifting the output of the cumulative sum register 10 to the right by the shift number for two calculation loops in the shifter 11. .

[Effects of the Invention] As described above, according to the present invention, multiplication can be stochastically accelerated with only a slight increase in the amount of metal objects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a multiplier according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional multiplier, and FIG. 3 explains the operation of an embodiment of the present invention. This is a time chart for DESCRIPTION OF SYMBOLS 1... Operand A register, 2... Operandro register, 3... Partial multiplier selector, 4... Partial multiplier register, 5... Operand A check circuit, 6...
...Control circuit, 7.. Partial product generation circuit, 8.. Partial product addition circuit, 9.. Accumulation result selector, 10.. Accumulation register, 11.. Shifter, 12.. cumulative sum circuit,
13... Accumulation result shifter, 14... Operand B check circuit, 15... Multiplicand selector. 1st Figure 3rd picture (1) Multiplicand register X============= Square number register Partial multiplier register cumulative sum register operation result Fig. 3 (2) 2 Figure 2 Figure 3 (3) Multiplier Number Clock Multiplicand Register Multiplier Register Partial Multiplier Register Cumulative Sum Register Operation ==2■9C]= [][D entrance T= [= Figure 3 (4) Multiplier clock Multiplicand register Multiplier register Partial multiplier register Cumulative sum register Operation result box]] T Ding B mouth L "L" ``L ℃======2[222222241= Carrying X Ding= [=

Claims (1)

[Claims] 1. Divide the multiplier into first to nth partial multipliers (n is an integer of 2 or more), and store the first to nth partial multipliers in a partial multiplier register sequentially from the lower side. , the required number of partial products are generated from the multiplicand used in the operation and the m-th (1≦m≦n) partial multiplier stored in the partial multiplier register, and the m-th partial multiplication result obtained by adding these partial products. from the first to the (m-1
) in a multiplier that obtains the product of the multiplier and the multiplicand by adding it to the cumulative sum result of the partial multiplier obtained from the partial multiplier number n. first and second operand check circuits that divide the divided data into divided data and determine whether or not the divided data are all "0"; and a multiplicand selector that outputs the operand with fewer all "0" divided data as the multiplicand; and a multiplicand selector that outputs the operand with less all "0" divided data as the multiplicand; a partial multiplier selector that takes the larger operand as the multiplier and sequentially selects the lower divided data of the multiplier as the partial multiplier and outputs it to the partial multiplier register; and a cumulative sum result shifter that shifts the cumulative sum result. and if it is determined from the output of the first operand check circuit or the second operand check circuit that the first partial multiplier input to the partial multiplier register is not all "0", Obtain the m-th partial multiplication result from the multiplicand selector output and the partial multiplier register output, and add it to the cumulative sum result up to the (m-1)th partial multiplier to obtain the cumulative sum up to the first partial multiplier. As a result, if it is determined that the m-th partial multiplier input to the partial multiplier register from the output of the first operand check circuit or the second operand check circuit is all "0", the The operation for obtaining the m-th partial multiplication result is omitted, and the cumulative sum result up to the (m-1)th partial multiplier is moved by the number of bits uniquely determined from the bit length of the partial multiplier using the cumulative sum result shifter. A multiplier, characterized in that the multiplier performs a right shift to produce a cumulative sum result up to the m-th partial multiplier.