JPH03196712A - Digital arithmetic circuit - Google Patents

Abstract

PURPOSE:To obtain the result of addition of partial product of a number being a half the bit number of a multiplier in time division by using a full adder and a pipe line FF for input and output side of the adder. CONSTITUTION:A selector 13 is controlled by a 3-bit control signal and outputs a signal being 0 time, + or -1 time, + or - twice of an input data selectively in response to a control signal given to each of 2 bits of a coefficient. A low-order carry via a carry connection circuit 14 and an input data (a) in 2 bits are fed to the selector 13 and a double output is generated. In the case of a code of 2' complement, the polarity inversion is realized by inverting '0' and '1' and by adding '1' to the least significant bit. An output of the selector 13 is fed to a full adder 16 via an FF 15. A carry (c) and a sum (s) in two bits of the full adder 16 are outputted via the FF 17 and fed back to the input of the full adder 16 to constitute an accumulator. The addition of the partial product is implemented in the time division processing. The selector 13, the FFs 15, 17 and the full adder 16 are operated by using a clock whose frequency is 4 times the sampling frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital arithmetic circuit that can be applied to a product-sum operation such as a digital filter.

[Summary of the invention]

The invention of claim (1) provides a full adder to which a first input of a binary number, a second input that is a carry, and a third input that is a sum are provided, and a full adder that is provided for the second input. carry connection means for supplying the carry from the lower order to the full adder and passing the carry to the upper order, means for holding the carry and sum outputted from the full adder in synchronization with a clock, and holding means. It is comprised of a feedback path that supplies the carry from the input terminal to the upper level via the carry connection means and returns the output of the sum to the full adder, allowing for a configuration with a small number of gates.

The invention of claim (2) provides at least two first and second
A digital arithmetic circuit comprising a multiplier and an adder that adds the outputs of the first and second multipliers, wherein the first and second multipliers add the multiplicand and the divided data of the multiplier. The adder has a selector that sequentially selects the sum and carry of each of the first and second multipliers; It is configured to cumulatively add the output signals of the selector, and can be configured as a product-sum calculation circuit with a small number of gates.

[Conventional technology]

An n-tap FIR digital filter converts the input sequence to
, the output series is y, and the impulse response is h0~
When h7-1 is set, the following calculation is performed. Digital filter processing of audio signals uses one multiplier and one accumulator,
A configuration in which the above calculations are controlled by a program (so-called DSP)
is used. However, in real-time processing of image data with a high sampling frequency, there is not enough time to perform time-sharing processing in multipliers and accumulators. Therefore, as shown in FIG. A configuration with . Figure 5 shows (n=4
) is an example. The configuration shown in FIG. 5 can be expressed as shown in FIG. That is, it consists of a shift register section 31, a multiplication section 32, and an addition section 33.

As a multiplier used in the digital filter mentioned above,
A parallel multiplier in which partial product adder circuits are arranged in parallel is usually used. FIG. 7 shows an example of a parallel multiplier using the Booth multiplication algorithm proposed by the applicant (see Japanese Patent Laid-Open No. 86270/1986). However, Figure 7 shows the circuit configuration for 1 bit.
The configuration is such that five partial products are added assuming a multiplier (coefficient) of IO bits.

One bit of the input data taken out from the tap of the shift register section is sent to the selector 3 via the flip-flop 34.
5.36.37.38.39 and bit connection circuit 40.4
1.42.43.44 respectively. Selector 35
.about.39 are supplied with a 3-bit control signal formed for every 2 bits of the coefficient, that is, the multiplier, from a Booth decoder (not shown). This decoder is supplied with a total of 3 bits, including the 2 bits of the coefficient of interest and the lower 1 bit.

The selectors 35 to 39 select ±2 times, ±1 times, and 0 times the input 1 bit based on the second-order Booth algorithm. Data that is ±2 times human power is bit connection circuit 4
This is achieved by selecting the lower bits from 0 to 44. That is, a one-bit shift forms a double value.

45, 46, 47, and 48 are 1-bit full adders, which are supplied with three inputs and output two bits: carry c and sum S. Carries from the lower order are supplied to full adders 46, 47 and 48 via bit connection circuits 49, 50 and 51, respectively. Carry connection circuit 49.50.51 connects a carry for a carry to the circuit of the upper bit plane and accepts a carry from the circuit of the lower bit plane. ing.

In a normal parallel multiplier, the carry is also added at the end, but in the configuration shown in Figure 7, the carry is added after the addition tree, and the carry and sum are in the form of 2-bit redundant binary numbers. The outputs are outputted from flip-flops 52 and 53. In this case, as part of the addition circuit, as shown in FIG.
A 4-stage full adder 55.56.5
7. Sequential addition at 58, output side flip-flop 59
and 60 can be used. FIG. 8 also shows the configuration for only one bit. As is clear from FIG. 8, the configuration differs from the normal configuration in that all 1-bit data is handled by two wires, carry C and sum S.

FIG. 8 is an example of addition of partial products of three taps of an FIR digital filter.

In the case of a 1-bit full adder, as shown in FIG. 9, the normal configuration is that inputs A and B and carry input ci from the lower order are supplied, and the addition output S and the carry output co to the upper order are supplied. This means that this occurs. On the other hand, the configuration shown in FIG.
It is based on the idea of converting it into a base number. That is, as shown in FIG. 9B, three inputs of the same bit digits A, B, and C are added and two outputs S1 and S2 of the same bit digit are output. In this way of thinking, the human effort required for a large number of the same bit digits can be reduced to two outputs per bit in the end, but
I can't make it into one. Therefore, as shown in FIG. 9C, a large number of full adders are connected in series, and one
It is necessary to form the normal binary output of the book.

However, the configuration shown in FIG. 9C is a slow arithmetic circuit in which carries propagate through multiple stages.

Carry lookahead and carry select are known as methods for increasing the speed of such adder circuits. However, these methods have the disadvantage of increasing the number of gates.

Therefore, providing such an adder circuit for each multiplier or each adder tree constituting the digital filter in FIG. 5 becomes an obstacle to speeding up. Therefore, in the previous application, in each multiplier and each adder, two operations per bit are stopped in the middle, the next operation is started, and after all operations are completed, the speed is increased as shown in FIG. Converts redundant binary numbers to normal binary numbers.

FIG. 8 shows one bit brane of the multiplication section, and in order to make an n-bit multiplier, it is necessary to overlap the n-branes as shown in FIG. 10.

In FIG. 10, for the sake of simplicity, the fact that the word length increases due to multiplication is not taken into consideration. FIG. 9 also shows a 1-bit plane of a part of the addition tree, and in order to have n bits, it is necessary to overlap them to form n planes as shown in FIG. In FIG. 10, MPY corresponds to the configuration in FIG. 7, and AT corresponds to the configuration in FIG. 8. Further, in FIG. 10, connection lines are shown only for the most significant bit brain for simplicity, but the other bit brains are connected in the same way.

[Problem to be solved by the invention]

In the previously proposed configuration, as shown in FIGS. 7 and 8, a large number of gate circuits such as full adders are sandwiched between flip-flops. In other words, it has a configuration in which multiple stages of gate circuits connected in series are sandwiched between pipeline registers. Such a configuration can be said to be an inefficient circuit because each gate circuit works only for a short time and rests for most of the clock cycle.

If such inefficiency is not improved, a high-speed arithmetic circuit for image signal processing will become large-scale, resulting in increased power consumption and cost.

In order to solve this problem of inefficiency, the gate circuit should be sandwiched between the pipeline registers in a form as small as possible, so as shown in FIG. Flip-flops 62 and 63 are provided. However, as shown in Figure 11, pipelining in full adder units or Booth selector units can triple the clock frequency, but there is a problem in that the number of flip-flops increases and the number of gates increases. occurs.

Therefore, an object of the present invention is to reduce the number of gates, and
An object of the present invention is to provide an improved digital arithmetic circuit so that gates do not play unnecessarily.

[Means to solve the problem]

The invention of claim (1) provides a full adder (16) to which a first input of a binary number, a second input that is a carry, and a third input that is a sum are supplied; carry connection means (18) for supplying carry from the lower order to the full adder (16) and passing the carry to the upper order; Means for holding in synchronization with the clock (17), supplying the carry from the hold means (17) to the upper side via the carry connection means (18), and feeding back the output of the sum to the full adder (16) This is a digital arithmetic circuit consisting of a feedback path.

The invention of claim (2) provides at least two first and second
multipliers (8A, 8B) and first and second multipliers (8
A, 8B) is a digital arithmetic circuit consisting of an adder (9) that adds the outputs of the first and second multipliers (8B).
A, 8B) is configured to form a partial product of the divided data of the multiplicand and the multiplier, and accumulate the partial products in the form of a carry and a sum. Second multiplier (8A, 8B)
A selector (2) that sequentially selects each sum and carry of
0), and is a digital arithmetic circuit configured to cumulatively add the output signals of the selector (20).

[Effect]

In the invention of claim (1), one full adder 16 and flip-flops 15 and 17 for pipelines on its input and output sides add the result of addition of partial products whose number is 2, which is the number of bits of the multiplier. It can be obtained by time division operation.

In the invention of claim (2), when performing a product-sum operation such as a digital filter, the multipliers 8A and 8B and the addition tree 9 both perform processing in the form of two signals, carry and sum. 9 is 4 from the multipliers 8A and 8B.
The book inputs are sequentially selected by the selector 20 and cumulative addition is performed.

Therefore, the number of gates can be reduced, and circuits such as full adders can be prevented from being idle.

〔Example〕

An embodiment in which the present invention is applied to a four-tap FIR digital filter will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of this embodiment. The input data is a two-complement code in which one sample is, for example, 8 bits in parallel. However, in Figure 1, 1
Only the configuration with respect to the bitplane is shown.

In FIG. 1, 2, 2.3, and 4 are unit delay elements, such as flip-flops, each having a delay time equal to the sampling period of input data. Output data a of flip-flop 1 (first tap) is supplied to multiplier 8A. The output data of flip-flop 2 (second tap) and the output data of flip-flop 3 (third tap) are supplied to delay circuits 5 and 6 with a delay amount of 2τ (τ: clock period), respectively. 6 output data b'
and C' are supplied to multipliers 8B and 8C, respectively. Output data d of the flip-flop 4 (fourth tap) is supplied to a 4τ delay circuit 7, and output data d' of the delay circuit 7 is supplied to a multiplier 8D.

The multipliers 8A to 8D are for multiplying the coefficients by the data of each tap using the second-order Booth algorithm. That is, when performing multiplication of (XxY) (X: multiplicand (data), Y: multiplier (coefficient)), depending on the pattern of successive signs of the multiplier, (0, +X, -X, +2X, or -2X
) is used to perform multiplication. Therefore, the Booth selector provided in each of the multipliers 8A to 8D is supplied with a control signal formed by supplying successive three bits of the coefficient to the Booth decoder. These O1−X, ±2X are called partial products.

Furthermore, the multipliers 8A to 8D include flip-flops l, 2.
Regarding the input data from the shift register section consisting of 3 and 4, a number of partial products corresponding to the coefficient word length η are cross-producted every clock cycle. This partial product must have a 2-bit shift. Therefore, the output of the shift register section is not only shifted to the right every four clock cycles, but also shifted two bits every clock cycle. This shifting method includes providing a selector on the input side of each of the multipliers 88 to 8D, or providing a shift register that stores the inputs of each of the multipliers 8A to 8D and can shift the bit digits upward. can be adopted.

The output e of the multiplier 8A and the output f of the multiplier 8B are supplied to the addition tree 9A. The output g of the 0 multiplier 8C and the multiplier 8D
The output of is supplied to the addition tree 9B. The respective outputs i and j of adder trees 9A and 9B are supplied to adder tree 10, respectively. These addition trees 9A, 9B and 1
At 0, two sets of 4 bits, carry and sum, are cumulatively added.

The output (carry and sum) k of the adder tree 10 is supplied to flip-flops 11 and 12, from which an output l is obtained. Although not shown, this output l is a redundant binary number, and due to the configuration of the accumulator,
One bit is converted to one ordinary binary number.

FIG. 2 is a timing chart showing the operation of the circuit shown in FIG.
The operating clock of B, 10 has a frequency four times the sampling frequency of input data. That is, if the sampling period of input data is T and the period of the clock is represented by τ, there is a relationship of (T−4τ). xLx2,... are the same digits (MSB, LSB, etc.) of the parallelized input data
Each bit represents one bit of .

For output data a of flip-flop 1, output data b of flip-flop 2, output data C of flip-flop 3, and output data d of flip-flop 4 are T,
Both 2T and 3T are delayed.

Delayed episode! The output data b' of the delay circuit 5 has a delay of 2τ with respect to b, the output data C' of the delay circuit 6 has a delay of 2τ with respect to C, and the output data d' of the delay circuit 7 is as follows.
It has a delay of 4τ with respect to d.

Output e to multiplication section 8, output f of multiplication section 8B, multiplication section 8C
In each of the output g of , and the output of the multiplier 8D, Ln indicates the timing at which the multiplication result of the input data xn and the coefficient is obtained. For example, in the output e of the multiplier 8A, t4 is the timing at which the multiplication result of x4 and the coefficient of the first tap is obtained.

In the output i of the addition tree 9A and the output j of the addition tree 9B, tmn indicates the timing at which the sum of the product of the coefficient and xm and the product of the coefficient and xn is obtained. For example, in the output i of the addition tree 9A, t54 is the product of x5 and the coefficient of the first tap (obtained at the timing indicated by t5 in the multiplication output e) and the product of x4 and the coefficient of the second tap (obtained at t4 in the multiplication f). (obtained at the timing indicated by) is obtained.

Furthermore, at the output k of the addition tree 10, t+++no
p indicates the timing at which the sum of the sum outputs obtained at tmn and top is obtained, respectively.For example, t4321 is the addition output generated at the timing t43 at the output l of the addition tree 9A, and the output j of the addition tree 9B. shows the timing at which the sum with the addition output generated at timing t21 is obtained. In the flip-flops 11 and 12, the output of the addition tree 10 is sampled with a clock having the original sampling frequency, and a filter operation output l is obtained from the flip-flops 11 and 12.

The multiplication section 8A described above has the configuration shown in FIG. 3.

In FIG. 3, 13 indicates a Booth selector, and the selector 13 is controlled by a 3-bit control signal obtained by supplying the coefficient for the first tap to the Booth decoder. The selector 13 selectively outputs signals that are 0 times, ±1 times, and ±2 times the input data in accordance with control signals for every two bits of the coefficient. This selector 13 receives carry and input data a from the lower level via the carry connection circuit 14.
Two bits are supplied. This means that when the lower carry from the carry connection circuit 14 is selected, twice the output is generated. Furthermore, in the case of a two-complement code, polarity inversion is achieved by inverting "0" and "1" and adding "l#" to the least significant bit.

The output of selector 13 is supplied to full adder 16 via flip-flop 15. The carry C and sum S bits of the full adder 16 are outputted via the flip-flop 17 and fed back to the input side of the full adder 16.

This feedback path constitutes an accumulator. With this accumulator configuration, partial products are added by time-sharing processing. As mentioned above, the sampling frequency of 4
The selector 13, flip-flops 15 and 17, and full adder 16 operate with the doubled clock.

When one bit of input data a, for example x4, is supplied, a partial product is generated from the selector 13 for every two bits of the coefficient (8 bits) of the first tap. A total of 4 partial products are added to full adder 1
6, the cumulative addition is performed in four clock cycles, and at the output e of the multiplier 8A in FIG.
The multiplication output of the coefficient is obtained. Flip-flop 17 is cleared prior to each accumulation, or AN
Initialization is performed by inserting a D gate. The carry generated during this cumulative addition is supplied to the full adder of the higher digits via the carry connection circuit 18, and the carry of the lower digit is supplied to the full adder 15 via the carry connection circuit 18. .

The multiplier 8A described above performs cumulative addition in such a way that one bit of input is represented by two bits, carry C and sum S. The multipliers 8B and 8C18D also have the same configuration as the multiplier 8A shown in FIG.

The details of the addition tree 9A are shown in FIG. 4. Since the 0 multipliers 8A and 8B generate 2-bit outputs e and f, carry and sum, as described above, it is possible to perform addition of these 2 bits. A configuration that can do this is required.

In FIG. 4, 20 is a selector for switching inputs e and r (four inputs in total) from multipliers 8A and 8B. Since the delay circuit 5 is inserted, there is a delay of two clock periods between the inputs e and f to be added. Regarding the carry of these inputs, carry connection circuits 21 and 22 are inserted. Further, flip-flops 23 and 24 are inserted only for the sum input, and the sum is supplied to the selector 20 with a delay of one clock period relative to the carry at the respective inputs e and r. Therefore, the carry of input e, the sum of input e, and the sum of carry human power f of input f are sequentially supplied to the selector 20 in four clock cycles, and the selector 20 receives these one
Select and output bits in order.

One input selected by the selector 20 is supplied to the flip-flop 25. Flip-flop 25, full adder 26, and flip-flop 27 constitute an accumulative adder similar to multipliers 8A to 8D. This accumulator accumulates the four inputs passed through the flip-flop 25. Therefore, from the timing when input C is supplied, (4+1+1
=6) After a clock period, the output i of the adder tree 9A is obtained from the flip-flop 27. For example, the timing t43, which is six clock cycles after the timing L4 of the input e in FIG. 2, is the timing at which the output i of the addition tree 9A is obtained.

Addition tree 9B and IO also have the same configuration as in FIG. 4. Addition processing can be performed using only one addition tree 10 without providing addition trees 9A and 9B. However, in that case, the selector sequentially selects one of the eight inputs, and the number of repeated additions increases to eight, so the calculation speed of the circuit needs to be twice that of the configuration shown in FIG.

Further, the number of taps of the filter, the word length, the word length of the accumulator, etc. are not limited to the above-mentioned embodiments. In particular, the word length of the accumulator is 1 bit, which is the fastest, but n
It may be expanded to a word length of bits. Furthermore, the present invention is applicable not only to digital filters but also to product-sum operations such as FFT and cosine transform.

〔Effect of the invention〕

In this invention, an accumulator consisting of a full adder and a feedback path has a pipeline configuration, so that addition or multiplier operation can be performed with a small number of gates, and it is possible to prevent the gates from being idle. In addition, when performing a product-sum operation such as a filter operation, processing in the multiplication section and addition tree can be performed using redundant binary numbers, and it is not necessary to perform carry carry addition in each of the multiplication section and addition tree. This prevents the calculation speed from decreasing. Furthermore, in this invention, many of the circuit configurations are the same, such as the accumulator, so
Suitable for IC implementation.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram of one embodiment of the present invention, and FIG.
FIG. 3 is a timing chart showing the operation of this embodiment, FIG. 3 is a block diagram showing an example of the configuration of a multiplication section, FIG. 4 is a block diagram showing an example of the configuration of an addition tree, and FIGS. 5 and 6. is a block diagram used to explain the FIR digital filter, FIGS. 7 and 8 are block diagrams showing the previously proposed multiplier and addition tree, respectively, and FIG. 9 is a route diagram used to explain the addition process. FIG. 1O is a route diagram showing the connection relationship between bit brains, and FIG. 11 is a block diagram showing a configuration in which each full adder is pipelined. Explanation of main symbols in the drawings 8A to 8D: Multiplier, 9A, 9B, 10: Addition tree 13: Booth's selector, 16.26: Full adder, 20: Selector.

Claims (2)

[Claims] (1) A full adder to which a first input of a binary number, a second input which is a carry, and a third input which is a sum are supplied; carry connection means for supplying the carry to the full adder and passing the carry to the upper level; means for holding the carry and sum outputted from the full adder in synchronization with a clock; A digital arithmetic circuit comprising a return path for supplying a carry to an upper level via the carry connection means and for feeding back the output of the sum to the full adder. (2) A digital arithmetic circuit comprising at least two first and second multipliers and an adder that adds the outputs of the first and second multipliers, the first and second multipliers The adder is configured to form a partial product of the divided data of the multiplicand and the multiplier, and accumulate the partial products in the form of a carry and a sum. 1. A digital arithmetic circuit comprising a selector that sequentially selects the sum and carry of each multiplier, and is configured to cumulatively add the output signals of the selector.