JPH0541632A - Fir digital filter device - Google Patents

Abstract

PURPOSE:To realize the FIR (Finite Impulse Response) digital filter device in which the system clock frequency independently of a bit length of a filter system is obtained, and the increase in the system clock frequency and the improvement of the processing performance are attained. CONSTITUTION:The device is provided with a multiplier recorder 7, a partial product generating circuit 8 generating a partial product in redundant binary expression, a redundant binary addition tree 9 connecting to a redundancy adder on an array, and the multiplication is implemented based on the 2 bit booth algorithm. Furthermore, an accumulated value latched in a register 3 is allocated to one input of the redundant binary adder tree 9 and the multiplication and the addition are processed in the lump. The components above are provided by a number equivalent to the number of taps for the FIR digital filter device. Since the multiplication and the addition are implemented by the redundant binary adder, a carry attended with the addition is propagated at most by one digit. According to the feature, the time of the addition operation is constant independently of the bit length.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to real-time processing of a digital filter, which is one method of digital signal processing for extracting an original signal from a measurement signal to which noise or distortion has been added, and more particularly to high speed and high accuracy. Is.

[0002]

2. Description of the Related Art Non-recursive N-tap FIR (Fini)
te Impulse Response) Digital filter device Input / output relational expression of filter and transfer function H
(Z) is generally represented by the following equations, respectively.

[0003]

[Equation 1]

[0004]

[Equation 2]

A block diagram of this filter is shown in FIG.
The signal processing of this filter is expressed by the following equation.

[0006]

[Equation 3]

When performing this signal processing in real time, it is necessary to perform the signal processing faster than the sampling rate or supply rate of the input signal sequence.

Conventionally, this processing has been performed by the hardware shown in FIG. In the figure, (1 ₀ ) to (1 _N-1 ) are, for example, cell array type multipliers that handle 2's complement data as input / output, and (2 ₁ ) to (2 _N-1 ) are input / output of 2's complement data. treat, for example, as a digit fried foresight instrument with the adder, (3 ₀₎ to
(3 _N-1 ) is a register, (4) is a system clock input terminal, (5) is an input port where input data is input every system clock, and (6) is output where output data is output every system clock. It is a port.

Next, the operation will be described. Input data X
(N) is input to the input port in synchronization with the system clock, and X (0), X (1), X are input to the input port.
(2) ... X (n-1), X (n), X (n + 1)
・ And time series data appears. Multipliers (1 ₀ ) to (1
_N-1 ), one of the operands of which is expressed in 2's complement notation B ₀ ~
B _N-1 is input, and the input signal X (n) appearing at the input port is input to the other operand. The registers (3 ₀ ) to (3 _N-1 ) hold the cumulative values of the product terms calculated by the multipliers up to the preceding stage, and the adder (2 ₁ ) to handle the data of the two's complement representation
The outputs of the multipliers are added by (2 _N-1 ), and the result is taken in the registers (3 ₀ ) to (3 _N-1 ) of the next stage in synchronization with the system clock. In this way, the cumulative value of the N product terms finally becomes the N-th stage register (3 _N-1 )
Is held in the output port, and the output port responds to X (n) Y
(N) is output with a delay of N clocks as shown in the timing chart of FIG.

[0010]

Since the conventional FIR digital filter device is configured as described above, it is attempted to increase the number of bits of the filter coefficient and improve the calculation accuracy without increasing the pipeline latency. In this case, since the cell array type multiplier and the adder with the carry look-ahead which handle the data of 2's complement expression are used, the system clock frequency must be lowered by the carry propagation accompanying the multiplication and addition. However, there was a problem that the throughput performance of was decreased.

The present invention has been made to solve the above problems, and maintains the system clock frequency without increasing the pipeline latency even if the bit length of the filter coefficient is arbitrarily increased. It is an object of the present invention to obtain an FIR digital filter device capable of improving the calculation accuracy.

[0012]

A FIR digital filter device according to the present invention is a multiplication recorder and partial product generating circuit for generating partial products of redundant binary representation for all multiplications, and a redundant binary for adding the partial products. This is realized by an addition tree, and the cumulative value of the product terms up to the preceding stage is input as one of the partial product inputs of the redundant binary addition tree, and multiplication and addition are collectively calculated.

[0013]

In the FIR digital filter device according to the present invention, the partial product generation circuit for generating the partial product of the redundant binary representation and the redundant 2 for adding the cumulative value of the partial product and the product term up to the preceding stage are added.
A binary addition tree is used to process multiplication and addition operations in a redundant binary representation.

[0014]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to FIG.
Shown in. In the figure, (3 ₀ ) to (3 _N-1 ) are registers for holding the cumulative value of the redundant binary representation up to the preceding stage, (4) is the system clock input terminal, and (5) is the input data of the two's complement representation. X (n) is an input port for each system clock, (6) is an output port for outputting redundant binary representation output data Y (n) for each system clock, and (7) is a two's complement representation. multiplying decodes the input data X (n) _{recorder, (8 00) ~ (8} n-1 m) the multiplication recorder converts the number filter system of 2's complement representations in redundant binary representation of the data (7) The partial product generation code (1
Partial product generation circuit for generating a partial product from 0), (9 ₀₎ -
(9 _N-1 ) is the partial product generated by the partial product generation circuits ( ₈₀₀ ) to (8 _{N-1 m} ) and the previous products held in the registers (3 ₀ ) to (3 _N-1 ). It is a redundant binary addition tree that adds cumulative values of redundant binary expressions.

First, the 2-bit Booth algorithm will be described. In general, Booth's algorithm is known as one of the methods for reducing the number of partial products and processing multiplications at high speed. Let X be the multiplication number and Y be the multiplication number, and k
It is represented as follows in the form of data in the 2's complement representation of bits.

[0016]

[Equation 4]

[0017]

[Equation 5]

Now, assuming that k is an even number and y _-1 is 0, Y
Can also be expressed as:

[0019]

[Equation 6]

That is, the product P represented in the two's complement representation format can be represented as follows.

[0021]

[Equation 7]

Therefore, (y _2j-1 + y _2j -2.
y _{2j + 1} ), 0, ± 1
The k / 2 partial products having any of X and ± 2X are obtained.

Next, the redundant binary representation will be described. In the redundant binary representation, one digit is represented by using three values of 1, 0 and -1. Therefore, in order to represent in binary, 2 bits are required for 1 digit, and, for example, 1, 0, -1 correspond to "01", "00", "10", respectively. In this case, "11" is an unused bit pattern.

Next, the operation will be described. Similar to the conventional apparatus, k-bit two-complement input data X (n), where k is an even number, is input to the input port in synchronization with the system clock, and the input port receives X (0), X (X). (1) X
(2) ... X (n-1), X (n), X (n + 1)
・ And time series data appears. The input data X (n) is simultaneously multiplied by each filter coefficient by Booth's algorithm every system clock cycle. First, the input data X (n) is input to the multiplication recorder (7) shown in FIG. 2, and m (= k / 2) pieces of the partial product generation code (10) shown in FIG. 3 are generated for every three consecutive bits. , The partial product generation code (10) is N × m partial product generation circuits ( ₈₀₀ ) to (8).
_{N-1 m} ). On the other hand, the N number of j-bit filter coefficients B _{0 to} B _N−1 given in the two's complement representation form are N × m number of partial product generation circuits ( ₈₀₀ ) to
It is input to (8 _{N-1 m} ). Here, the configuration of the partial product generation circuit (8) is shown in FIG. In the figure, (12) is an AND element, (13) is an OR element, and (14) is an inverter element. In the partial product generation circuit (8), conversion operation from 2's complement expression to redundant binary expression, shift up operation and digit inversion operation are performed. First, in the conversion operation, the filter coefficient B
_{If 0 to} BN _-1 is positive, the binary value is directly associated with each bit. That is, "0" is changed to "0" for the value "0".
Corresponds to the value “1”. If negative, the sign bit is
The other bits correspond to the binary values as they are to 1 ". Next, the partial product generation code (10) generated by the multiplication recorder (7) for the shift up operation and the digit inversion operation.
0, ± 1B _X , ± 2B _X (X = 0, 1, 2 ...
Generate any output value of N-1). The operation of × 2 is a shift operation, and the positive / negative inversion operation changes “−1” to “1”,
A partial product is generated by converting each digit into "0" for "0" and "-1" for "1". N × m generated
The number of partial products is N redundant binary addition trees (9 ₀ ) for every m.
(9 _N-1 ) are added. The structure of the redundant binary addition tree is shown in FIG. In the figure, U _{0 to} U _m-1 are m partial products generated by the Booth shifter, and V is a cumulative result up to the previous stage held in the previous stage register (3). W
Is the sum of the redundant binary representation, if the stage is an intermediate stage in the pipeline stages of N-stage, W is a register (3 ₀₎ to retain data in the redundant binary representation - (3 _N-2 )
, And becomes the input V of the redundant binary addition tree of the next stage. If the stage is the final stage, it is taken into the register (3 _N-1 ) and then connected to the output port of the FIR digital filter, and the response Y (n) corresponding to X (n) is redundant 2
Similar to the conventional apparatus, it is output as N-clock delayed data by N clocks, as in the conventional apparatus. In FIG. 5, (15) is a redundant binary adder, whose internal configuration is shown in FIG.
Shown in. In the figure, (16) is a sum carry generator, (17) is a redundant binary half adder, and P _{1 to} P ₁ P _1-1 to
P ₁ , Q _{1 to} Q ₁ Q _{1-1 to} Q ₁ are redundant binary representations of 2
Two input operands, C _{1 to} C ₁ C _{1-1 to} C ₁ , S ₁ to
S ₁ S _{1-1 to} S ₁ are the outputs of the sum carry generator (17), and the intermediate sum and the intermediate carry of the redundant binary representation, respectively, O _{1 to} O ₁ O _{1-1 to} O ₁ are the redundant binary. It is the result of addition of expressions. The above P ₁ , Q ₁ , C ₁ , S ₁ , O ₁
Is the first digit, and the value is "1",
It has a value of either "0" or "-1". This redundancy 2
When the addition is performed by the binary adder (15), the sum carry generator (16) is based on the truth value shown in FIG. 7 and is based on the truth sums S _{1 to} S ₁ S _{1-1 to} S ₁ and the middle carry C. ₁ ~
Generate C ₁ C _{1-1 to} C ₁ . Further, the redundant binary half adder (17) at each place performs addition with the intermediate sum of the same place as the intermediate carry of one place below, and the addition results O _{1 to} O ₁ O _1-1 to
Generate O ₁ . Here, each of the sum carry generators (16) has an intermediate sum S _{1 to} S ₁ S ₁ so that carry does not occur in the addition operation performed in the redundant binary half adder (17) of the same rank. _{-1 to} S ₁ and intermediate carries C _{1 to} C ₁ C _{1-1 to} C ₁ are generated. Therefore, in the addition operation by the redundant binary adder, the carry propagates only to the place one digit higher. That is, in this digital filter, since carry propagation from the least significant bit direction to the most significant bit direction in multiplication and addition is at most one digit, the maximum delay between pipeline stages is fixed. ..

[0025]

Since the present invention is configured as described above, since carry propagation from the least significant bit direction to the most significant bit direction in multiplication and addition is at most one digit, the bit of the filter coefficient is Even if the length is increased to improve the calculation accuracy, the maximum delay time between the number of pipeline stages is always fixed, and the system clock frequency can be kept constant.

The FIR digital filter device of the present invention is a conventional FIR digital filter device having a long bit length of the input X (n) and the filter coefficient and using a cell array type multiplier and an adder with a carry look-ahead. It is possible to increase the system clock frequency and improve the processing performance.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a multiplication recorder.

FIG. 3 is a diagram showing a truth value of a multiplication recorder.

FIG. 4 is a block diagram of a partial product generation circuit.

FIG. 5 is a block diagram of a redundant binary addition tree.

FIG. 6 is a block diagram of a redundant binary adder.

FIG. 7 is a diagram showing a truth value of a sum carry generator.

FIG. 8 is a system block diagram of a FIR digital filter device.

FIG. 9 is a block diagram of a conventional FIR digital filter device.

FIG. 10 is a diagram showing a processing timing of the FIR digital filter device of the related art and the present invention.

[Explanation of symbols]

 1 Multiplier 2 Adder 3 Register 4 Clock Input Terminal 5 Input Port 6 Output Port 7 Multiply Recorder 8 Partial Product Generation Circuit 9 Redundant Binary Addition Tree 10 Partial Product Generation Code 11 Recorder 12 AND Element 13 OR Element 14 Inverter Element 15 Redundant Binary adder 16 Sum carry generator 17 Redundant binary half adder

Claims (1)

[Claims] 1. An N-tap F for generating an output signal sequence by performing conversion represented by a transfer function in a k-bit input signal sequence, where k is an arbitrary positive even number and N is an arbitrary positive integer.
IR (Finite Impulse Responses)
e) In the digital filter device, one multiplication recorder based on a 2-bit Booth algorithm for calculating the product of the filter coefficient and the input signal, and the accumulation of the product,
N × k / 2 partial product generation circuit groups, N redundant binary addition trees, and N that holds the accumulation of products represented by the redundant binary representation.
Non-recursive FIR having a number of registers
Digital filter device.