JP3695561B2 - Accumulator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a product-sum device, and more particularly to a product-sum device that performs high-speed product-sum processing.
In recent years, DSPs (Digital Signal Processors) have been applied in a wide range of fields.
DSPs are required to perform product-sum processing that often appears in signal processing operations at high speed. For this reason, high-speed operation of a product-sum machine that performs product-sum processing in the DSP is desired.
[0002]
[Prior art]
FIG. 7 shows a configuration diagram of the parallel multiplier. In the figure, a multiplier 10 creates partial products of inputs A and B, and adds the partial products to obtain a multiplication result. The addition of the partial products is performed by an adder circuit (Walesa tree) having a tree-like structure so that carry propagation does not occur. Specifically, the partial product is half-added to reduce the number of bits.
[0003]
For example, if Boot's algorithm is used to generate a partial product, a 16 × 8-bit multiplication results in a 16 × 8-bit partial product. By calculating each digit of this 128 bits (16 × 8) with a half-adder with 3 inputs and 2 outputs, two (sum, carry) data are finally obtained. The final result is obtained by adding these two data by the full adder 12 having carry propagation.
[0004]
Using this multiplier, a sum of products is also made. The accumulator is configured to continue adding the multiplication results as ΣAi · Bi. FIG. 8 shows a configuration diagram of the sum of products. The product-sum multiplier has almost the same configuration as that of the multiplier. However, the multiplication result of the multiplier 14 is obtained by summing up two data, which are stored in the sum (S) and carry (C), and the result Acc of the previous product-sum processing. Since it is necessary to add, here, the half sum adder 16 with 3 inputs and 2 outputs once again performs sum + carry + the previous product-sum result to calculate the final sum and carry. Finally, this is fully added by the full adder 18 to obtain a product-sum result. In this product-sumer, the product-sum cycle time TS shown in FIG. 9 is determined by a time T1 for generating a partial product and narrowing down by a half adder, and a time T2 for adding the obtained result and the previous product-sum result. The
[0005]
Pipelining has been conventionally performed as a method of reducing the product-sum cycle time by shortening the cycle time of the product-sum. In this method, as shown in FIG. 10, by dividing the processing by the registers 19 and 20 in the partial product generation / narrowing part and the full addition part, the latency increases, but the processing cycle becomes shorter. The processing time can be shortened. As shown in FIG. 11, the longer one of the partial product generation / narrowing time T1 and the final result calculation time T2 can be pipelined as a cycle. That is, when the partial product narrowing time is equal to the final result adding time, the product-sum processing cycle time is halved.
[0006]
As another method, as shown in FIG. 12, there is a configuration in which two multipliers / summers are simply provided to make dual. In this configuration, registers 22A and 22B for storing product-sum results are provided in each product-sum unit, and the product-sum operation is obtained by dividing into two product-sum units 14A, 16A, 18A and 14B, 16B, 18B. At the end of each product-sum process, the two product-sum results are added by the full adder 24 to obtain the final result and stored in the register 26. In this method, the time required for the product sum can be halved regardless of the time for partial product generation and final result addition.
[0007]
[Problems to be solved by the invention]
In the pipelining of the configuration shown in FIG. 8, in general, the time T1 for narrowing the partial product and the time T2 for adding the final result do not coincide with each other, and the longer time becomes the cycle time. The cycle time cannot be halved due to line formation.
[0008]
In the dual configuration shown in FIG. 12, the cycle time can be halved, but it is necessary to provide the registers 22A and 22B and the full adder 24 in order to obtain the final result. In addition, there is a problem that an addition process is required after the product-sum process is completed. In addition, the sum of products is controlled by a DSP instruction, and changing the register configuration of the sum of products (increasing the registers 22A and 22B) means changing the instruction set, causing a problem that firmware assets cannot be utilized.
[0009]
The present invention has been made in view of the above points, and an object of the present invention is to provide a accumulator that can halve the cycle time, suppress an increase in hardware scale, and does not change the register configuration.
[0010]
[Means for Solving the Problems]
The invention according to claim 1 is a first multiplication unit that half-adds a partial product of two-input multiplication and outputs a sum and carry;
A second multiplication unit that half-adds a partial product of two-input multiplication and outputs a sum and a carry;
A first final result adding unit that inputs the output of the first multiplying unit, the output of the second multiplying unit, and the output of the second final result adding unit and outputs a product-sum result; ,
A second final result adder that inputs the output of the second multiplier, the output of the first multiplier, and the output of the first final result adder, adds the result, and outputs the product-sum result. And
Prepare.
[0011]
Thus, the sum and carry for the current input from the first and second multipliers in the first and second final result adders, and the sum and carry for the previous input from the second and first multipliers, Carry and the product-sum result for the previous input from the second and first final result adders can be added to obtain the product-sum result for the current input. Can be halved, half adders can be reduced compared to the conventional dual configuration, an increase in hardware scale can be suppressed, and no change in register configuration occurs.
[0012]
According to a fourth aspect of the present invention, there is provided the sum of products according to the first aspect,
Instead of the first multiplier and the second multiplier, a single multiplier is used in a time division manner.
For this reason, a single multiplication unit is sufficient, and the hardware scale can be further reduced.
The invention as set forth in claim 5 is the sum of the multipliers according to claim 1,
Instead of the first final result adding unit and the second final result adding unit, a single final result adding unit is used in a time division manner.
[0013]
Therefore, a single final result adding unit is sufficient, and the hardware scale can be further reduced.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a block diagram of a first embodiment of the present invention. In FIG. 2, inputs A and B are supplied at the timing shown in FIG. 2A. Among them, odd-numbered inputs A and B are latched by registers 30A and 32A and supplied to multiplier 34A, and even-numbered inputs. A and B are latched by the registers 30B and 32B and supplied to the multiplier 34B.
[0015]
Each of the multipliers (multipliers) 34A and 34B creates partial products of inputs A and B, adds the partial products, narrows down, and generates two data of a sum (S) and a carry (C). 2B and 2C show the output timings of the data S and C of the multipliers 34A and 34B, respectively. The output data S and C of the multiplier 34A are supplied to the half adder 36A and the register 38B, and the output data S and C of the multiplier 34B are supplied to the half adder 36B and the register 38A.
[0016]
When the multiplication data S and C for the (n + 1) th input are supplied from the multiplier 34A to the half adder 36A, the multiplication data S and C for the nth input shown in FIG. 2 (E) are supplied from the register 38A. The product sum data for the (n-1) th input shown in FIG. 2G is supplied from the register 40A, and two data of the sum (S) and carry (C) for these data are output. In the full adder 42A, the above data S and C are added, and the final result, that is, the product-sum data for the (n + 1) th input is obtained. The product-sum data is selected by the selector 44 and stored in the registers 46 and 40B. FIG. 2 (H) shows the contents of the register 46.
[0017]
When the multiplication data S and C for the (n + 2) th input are supplied from the multiplier 34B to the half adder 36B, the multiplication data S and C for the (n + 1) th input shown in FIG. 2D are supplied from the register 38B. The product sum data for the nth input shown in FIG. 2F is supplied from the register 40B, and two data of the sum (S) and carry (C) for these data are output. In the full adder 42B, the above-described data S and C are added to obtain the final result, that is, the product-sum data for the (n + 2) th input. The product-sum data is selected by the selector 44 and stored in the registers 46 and 40A. FIG. 2 (H) shows the contents of the register 46.
[0018]
The multiplier 34A corresponds to the first multiplier, the multiplier 34B corresponds to the second multiplier, the half adder 36A, the full adder 42A, and the registers 40A and 38A are the first final result adder. The half adder 36B, the full adder 42B, and the registers 40B and 38B correspond to the second final result adder.
FIG. 3 shows a configuration diagram of a 4-bit 5-input half adder used as the half adders 36A and 36B. The product-sum data is input from the register 40A to the terminal 50, and the two data S and C are input from the register 38A to the terminals 51 and 52. These data are added by the half adders 54a to 54d. The data S obtained in the above is supplied to the half adders 56a to 56d, and the data C is supplied to the half adders 58a and 56a to 56c. Data S output from the multiplier 34A is supplied from the terminal 53 to the half adders 56a to 56d and added. Data S output from the half adders 56a to 56d is supplied to the half adders 58b to 58e, and data C output from the half adders 58a to 58d is supplied to the half adders 58a to 58d. Further, the data C output from the multiplier 34A is supplied from the terminal 55 to the half adders 58b to 58e and added. Data C and S output from the half adders 58a to 58e are supplied to the full adder 42A.
[0019]
Here, the addition of data input to the terminals 50 to 52 is considered to have a large number of stages and a large delay time. However, the values of the data of the registers 40A and 38A have already been determined at the start of the addition cycle. Considering that the addition of the output data S and C of 34A starts later than this, the delay in the half adders 58a to 58d has no influence on the whole.
[0020]
As described above, the two product-sum circuits composed of the multipliers 34A and 34B, the half adders 36A and 36B, and the full adders 42A and 42B are alternately operated with a phase difference of 180 degrees, which is necessary for the product-sum processing. Cycle time can be halved as with dualization. Further, since the extra registers 22A and 22B and the full adder 24 are not required unlike the dual configuration, the hardware is not enlarged and the register configuration is not changed.
[0021]
FIG. 4 shows a block diagram of the second embodiment of the present invention. In the figure, inputs A and B are supplied at the timing shown in FIG. 5A and supplied to the multiplier 33. The multiplier 33 creates partial products of the inputs A and B, adds the partial products, narrows down, and generates two data of a sum (S) and a carry (C). FIG. 5B shows the output timing of the data S and C of the multiplier 33. Output data S and C of the multiplier 33 are supplied to the registers 35A and 35B.
[0022]
The register 35A stores the outputs 33 and S of the multiplier 33 for odd-numbered inputs as shown in FIG. 5D during the low level period of the latch clock shown in FIG. 5C, and the register 35B stores the high level of the latch clock. Multiplier 33 outputs S and C for even-numbered inputs are stored as shown in FIG. The odd-numbered two data S and C stored in the register 35A are supplied to the half adder 36A and the register 38B, and the even-numbered two data stored in the register 35B are supplied to the half adder 36B and the register 38A. The
[0023]
When the multiplication data S and C for the (n + 1) th input are supplied from the register 35A to the half adder 36A, the multiplication data S and C for the nth input shown in FIG. The product-sum data for the (n-1) th input shown in FIG. 5F is supplied from 40A, and two data, sum (S) and carry (C), for these data are output. In the full adder 42A, the above data S and C are added, and the final result, that is, the product-sum data for the (n + 1) th input is obtained. The product-sum data is selected by the selector 44 and stored in the registers 46 and 40B. FIG. 5J shows the contents of the register 46.
[0024]
When the multiplication data S and C for the (n + 2) th input are supplied from the register 35B to the half adder 36B, the multiplication data S and C for the (n + 1) th input shown in FIG. 5 (H) are supplied from the register 38B. The product-sum data for the nth input shown in FIG. 5 (I) is supplied from 40B, and two data of sum (S) and carry (C) for these data are output. In the full adder 42B, the above-described data S and C are added to obtain the final result, that is, the product-sum data for the (n + 2) th input. The product-sum data is selected by the selector 44 and stored in the registers 46 and 40A. FIG. 5J shows the contents of the register 46.
[0025]
If the time for narrowing down the partial product is shorter than the addition time of the final result, the multiplier 33 operates in a time that is less than half of the product-sum cycle. In this embodiment, the multiplier 33 is used in a time division manner. By doing so, one multiplier can be eliminated, and the circuit scale is reduced. In this embodiment as well, the cycle time required for the product-sum processing can be halved as in the conventional dual configuration.
[0026]
On the contrary, if the time for narrowing down the partial product is longer than the addition time of the final result, the circuit configuration of the third embodiment shown in FIG. 6 is adopted. In FIG. 6, odd-numbered inputs A and B of inputs A and B are latched by registers 30A and 32A and supplied to multiplier 34A, and even-numbered inputs A and B are latched and multiplied by registers 30B and 32B. Is supplied to the vessel 34B.
[0027]
Each of the multipliers 34A and 34B creates partial products of the inputs A and B, adds the partial products, narrows down, and generates two data of a sum (S) and a carry (C). The output data S and C of the multiplier 34A are supplied to the selectors 37 and 39, respectively, and the output data S and C of the multiplier 34B are supplied to the selectors 37 and 39, respectively.
The selectors 37 and 39 sequentially select the two data S and C in odd and even numbers and supply them to the half adder 41. The product-sum data obtained in the previous cycle is supplied from the register 45 to the half adder 41, and the half adder 41 outputs two data of S and C for these data. The full adder 43 adds the data S and C, and the final product-sum data is stored in the register 45.
[0028]
In this case, since the addition time of the final result is short, time division multiplexing is performed and processing is performed by one half adder 41 and one full adder 43. On the contrary, since the time for narrowing the partial product is long, the cycle time is shortened by using two multipliers 34A and 34B. In this embodiment as well, the cycle time required for the product-sum processing can be halved as in the conventional dual configuration.
[0029]
【The invention's effect】
As described above , according to the first aspect of the present invention , the first and second final result adder units perform the sum and carry for the current input from the first and second multiplier units, and the second and first units. The sum and carry for the previous input from the multiplication unit and the product-sum result for the previous previous input from the second and first final result addition units may be added to obtain the product-sum result for the current input. The cycle time can be halved in the same way as in the conventional dual configuration, half adders can be reduced compared to the conventional dual configuration, the increase in hardware scale can be suppressed, and the register configuration can be changed. Does not occur.
[0031]
In addition, according to the fourth aspect of the present invention , a single multiplication unit is sufficient, and the hardware scale can be further reduced.
Further , according to the invention described in claim 5 , a single final result adding unit is sufficient, and the hardware scale can be further reduced.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of the present invention.
FIG. 2 is a signal timing chart of FIG. 1;
FIG. 3 is a configuration diagram of a half adder.
FIG. 4 is a configuration diagram of the present invention.
FIG. 5 is a signal timing chart of FIG. 4;
FIG. 6 is a configuration diagram of the present invention.
FIG. 7 is a configuration diagram of a conventional multiplier.
FIG. 8 is a configuration diagram of a conventional sum of products.
9 is a diagram for explaining a multiplication cycle in FIG. 7; FIG.
FIG. 10 is a configuration diagram of a conventional sum of products.
11 is a diagram for explaining a multiplication cycle in FIG. 10; FIG.
FIG. 12 is a block diagram of a conventional sum of products.
[Explanation of symbols]
30A, 30B, 32A, 32B, 35A, 35B, 38A, 38B, 40A, 40B, 45, 46 Registers 33, 34A, 34B Multipliers 36A, 36B, 41 Half adders 42A, 42B, 43 Full adders

Claims (5)

A first multiplier that half-adds a partial product of two-input multiplication and outputs a sum and a carry;
A second multiplication unit that half-adds a partial product of two-input multiplication and outputs a sum and a carry;
A first final result adding unit that inputs the output of the first multiplying unit, the output of the second multiplying unit, and the output of the second final result adding unit and outputs a product-sum result; ,
A second final result adder that inputs the output of the second multiplier, the output of the first multiplier, and the output of the first final result adder, adds the result, and outputs the product-sum result. And
Product-sum unit, characterized in that it includes. The accumulator according to claim 1, wherein
The first multiplier and the second multiplier alternately take in two inputs and perform multiplication . The accumulator according to claim 1, wherein
In the first final result adder, the output of the second final result adder with respect to the input of the previous cycle, the output of the second multiplier with respect to the input of the previous cycle, and the first with respect to the input of the current cycle A sum of products summed with the output of the multiplication unit and output as a product sum result for the input of the current cycle . The accumulator according to claim 1, wherein
  Instead of the first multiplier and the second multiplier, a single multiplier is used in a time division manner. The accumulator according to claim 1, wherein
  Instead of the first final result addition unit and the second final result addition unit, a single product finalizer is used in a time division manner.

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