JP2529890B2 - Multiplicative remainder calculator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field to which the Invention belongs) The present invention relates to a remainder (when divided by N) modulo another positive number N of multiplication values A and B of two positive numbers (A, B). Remainder, [A ・
B] _modN ) (hereinafter, this operation is referred to as a modular multiplication operation).

(Prior Art and Its Deficiencies) The above-mentioned modular multiplication unit is used for elemental operations in code decoding processing of code theory and encryption theory. In the conventional method of realizing such a modular multiplication operator, the binary value expression of A out of two positive numbers A and B provided for multiplication is expressed by the following formula. (L is the number of bits in the binary value representation of A), the multiplication residue value [A · B] _modN of A and B is Focusing on that, the calculation is executed according to the following processing procedure.

Stores Procedure B to shift register, (2) by treatment of reducing the N only if the result is greater than the positive N of law for each shifted by one bit to the left (2 times operation) the right side of equation [2 ⁱ B] _modN is sequentially calculated.

Step _ai = "1", past accumulated value On the other hand, by newly accumulating the [2 ^j · B] _{mod N} obtained in Ask for.

Procedure N is subtracted only when the result obtained above is larger than the modulo positive number N Ask for.

The above processes ( ₁ ) to ( ₄ ) are carried out in order from the least significant bit (LSB = a _o ) in the binary representation of the positive number A (MSB = a _l-1 ).
It is possible to obtain the [A / B] _{mod N} by executing the process up to 1 times. FIG. 3 shows an example of the configuration of a conventional multiplication residue calculator that executes these procedures.

In the figure, 301 is an auxiliary register for storing the [2 ⁱ · B] _{mod N} , 302 is an adder, and the auxiliary register 301
The output of is shifted to the left by 1 bit and the value equivalently doubled by adding "0" as the least significant digit is used as one input, and the two's complement value (- By inputting N) to the other input, a value obtained by subtracting N from the double value of the output value of the auxiliary register 301 is output. 303 is a switch, and the output of 302 is negative due to the MSB of the output of adder 302 (MSB =
In case of "1", double the output value of 301 above and positive (M
When SB = "0"), adder 30 is obtained by subtracting N from the above doubled value.
The outputs of 2 are switched and input to the auxiliary register 301.

304 is the accumulated value shown in the above procedure according to each digit a _{i of the} binary value of A. 305 and 306 are adders, 305 adds the output value of the accumulated value register 304 and the output value of the auxiliary register 301, and outputs a new accumulated value shown in the procedure. To do. On the other hand, 306, like the adder 302, uses the output of 305 as one input and modulo the positive two N's complement value (-N).
Is input to the other input to output a value obtained by subtracting N from the output value of 305. 307 is a switching device similar to 303,
The MSB of the adder 306 output causes the 306 output to be negative (MSB =
When it is “1”, the output value of the adder 305 is positive (MSB =
When it is "0", the output of 306 obtained by subtracting N from the output of the adder 305 is switched and input to the accumulated value register 304. Note that 304 inputs a _i for each loop operation of the above 305, 307, 304, and stores the output of 307 only when a _i = “1”.

In the above-mentioned configuration, the block 308 surrounded by the one-dot chain line in FIG. 3 executes the processing of the above procedure, and the block 309 executes the procedure and, and the execution is repeated l times. At this time, the calculated multiplication remainder value [A · B] mod _N is stored in the cumulative value register 304.

The above is an example of the configuration based on the conventional method. However, in such a configuration, three adder / subtractor of the same scale, two switchers, two auxiliary registers and an accumulated value are used. There is a drawback that the circuit scale becomes large because one register is required for each register.

(Object of the Invention) An object of the present invention is to alleviate the problem of enlargement of the circuit scale that occurs in the above-mentioned conventional method, and to provide a relatively small multiplication residue calculator having a simple configuration.

(Structure and Action of the Invention) [Structure] FIG. 1 is a structural example showing an embodiment of the present invention.

Reference numeral 101 denotes a first switch, which inputs the other positive number B used for multiplication and the two's complement (-N) of the modulo positive number N, and alternately switches and outputs them.

An adder 102 receives the output of the first switch 101 as one input, performs addition operation with the other input, and outputs the result.

Reference numeral 103 denotes an inverter, which inputs the most significant digit (MSB) of the output of the adder 102, performs inversion logic processing, and outputs an inverted output (▲
▼) is output.

104 designates each digit a _i (i = 1 to 0) on the binary value representation of one positive number A used for multiplication as one input, and the inverted output ▲ ▼ of the inverter 103 as the other input. It is a switching device that alternately switches for each digit and outputs as a parallel load signal PL.

105 is a cumulative value register, which temporarily stores the output of the adder 102 when PL = “1” and the adder when PL = “0” depending on the polarity of the parallel load signal PL output from the switch 104. The output of 102 is rejected, the already stored data is retained, and the temporarily stored data or twice the data temporarily stored only when ▲ ▼ = "0" and i ≠ 0. The value is output and used as the other input of the adder 102. The scale of the accumulated value register 105 is sufficient to be (m + 1) bits when the number of significant digits in the binary value representation of the positive number B is m (m is a natural number). Also, the double value of the temporarily stored data supplied from the accumulated value register 105 to the adder 102 is shifted by 1 bit to the left (MSB side) of the output arrangement of the accumulated value register 105 and is set to “0” on the LSB side. "(Zero) is obtained by adding the array, it is obvious that the circuit responsible for the multiplication process does not need to be specially installed.

[Action]

The operation of the present invention based on the configuration example of FIG. 1 will be described below by using mathematical expressions and FIG.

Multiplication residue value [A / B] which is the calculation target in the present invention
_modN can be generally expressed by the following equation by the equation (2).

Therefore, when the sequence c _l-1 , c _l-2 , ..., c _i , ..., c ₁ , c ₀ is defined by the following equation, By the equation (3) and the equations (4-1) to (4-5),
The following equation holds.

c ₀ = [A · B] _modN (5) From the above, first of all the sequence c _l-1 , c _l-2 , ..., C _i , ..., c ₁ , c ₀ , c _l-1 is initialized. It is found by the setting equation (4-1), and then by the accumulation by the recurrence equation (4-3), c _l-2 , ...
_1, the target value c ₀ That by sequentially calculating the c ₀ [A ·
B] It can be seen that _modN is required.

FIG. 2 is a flowchart showing the operation of the modular multiplication operator according to the present invention shown in FIG. 201-210 show each step number. Here, it is assumed that the initial value of the accumulated value register 105 is set to "0" (zero).

First, in the calculation, the value of i is i = 1-1 by initialization.
It starts from the state of (the most significant digit = MSB) (step 201).
Next, in step 202, the switch 101 first selects a positive number B as an input and supplies it to one input of the adder 102, and the addition operation with the other input from the accumulated value register 105 is performed by the adder. Performed by 102.

At the same time, each digit a _i of the binary representation of the positive number A is selected as the input of the switch 104, and in step 203, if a _i = “1”, the output of the adder 102 is stored in the accumulated value register in step 204. Load parallel to 105. If a _i = “0”, adder 1
The process proceeds to step 205 without performing parallel loading of the output of 02. By the above operation, ( _al-1 · B) is calculated.

Next, in step 205, the switch 101 selects (-N) as an input, and the switch 104 selects ▲ ▼ as an input. A value obtained by subtracting N from the output of the accumulated value register 105 by supplying (-N) to one input of the adder 102 and the output of the accumulated value register 105 to the other input. Is output from the adder 102.

Table 1 shows the switching operation of the switch,
The outputs of the first switching device 101 and the second switching device 104 are simultaneously switched in step 202 and step 205 so that the output is always a combination of B, a _i , (-N) and ▲ ▼ as shown in Table 1.

Next, in step 206, the output of the adder 102 is positive (▲ ▼) due to the output ▲ ▼ of the adder 102.
= “1”), the process proceeds to step 207, the output of the adder 102 obtained by subtracting N from the output of the accumulated value register 105 is newly stored in the accumulated value register, and the newly stored value is It is supplied to the other input of the adder 102, and this is repeated until the output of the adder 102 becomes negative (▲ ▼ = "0") by the loop processing of steps 206 and 207.

When ▲ ▼ = “0”, the output of the adder 102 is not stored in the accumulated value register 105 and the past accumulated value is held.

By the above operation, the remainder [a _l-1 B] _modN = c _l-1 modulo N of the calculated (a _l-1 B) is calculated and stored in the accumulated value register 105.

When ▲ ▼ = “0”, the process proceeds to step 208. Next, if the value of i is i = 0, the operation is terminated, and if i ≠ 0, the accumulated value register 105 is stored in step 209. A value twice the value is output and supplied to the other input of the adder 102, and the value of i is decremented by 1 in step 210.
Return to the selection of B of the switching supply 101 in step 202, 2
Enter the round calculation.

In the second round of calculation, similarly, c _l-2 = [2c _l-1 + a _l-2
· B] _modN is calculated, following a new c _i based on the above-mentioned recurrence formula every time the one-round (4-3) is calculated.

From the above, when the above-mentioned series of operations is repeated l times from i = 1 to i = 0, the residual value obtained when i = 0 in step 208 is c ₀ = [A · B] _modN
Is stored in the accumulated value register 105.

(Effects of the Invention) As described in detail above, according to the present invention, two switchers (one of which is a 1-bit switcher), one adder,
Since a desired arithmetic unit can be realized by one accumulation value register, there is a remarkable effect that the circuit scale becomes about 1/2 or less as compared with the conventional configuration.

[Brief description of drawings]

FIG. 1 is a configuration example diagram showing an embodiment of the present invention, FIG. 2 is a flow chart showing the operation of the present invention, and FIG. 3 is a configuration example diagram of a conventional modular multiplication operator. 101,104 ... Switcher, 102 ... Adder, 103 ... Inverter, 105 ... Accumulation value register, 201 ... 210 ... Step number, 301 ... Auxiliary register, 302,305,306 ... Adder, 30
3,307 ... Switch, 304 ... Accumulated value register, 308,309 ...
… Computation block.

Claims (1)

(57) [Claims] 1. When obtaining a remainder modulo another positive number N with respect to a multiplication value A · B of two positive numbers A and B, two of the positive number B and the positive number N expressed in binary value are used. A first switching device that alternately switches between and outputs the complementary value of the first switching device, an adder that outputs the addition value of the input of the first switching device to the other input, and an output of the adder An inverter that obtains an inverted output by inputting the most significant digit of the positive number A, and the number of significant digits in the binary value representation of the positive number A is 1 (l is a natural number), and the binary number of the positive number A is Each digit in the value representation is a _i (i = 1
-1 (highest) to 0 (lowest)), the highest digit
Second switching for alternately switching and outputting each digit a _{i in the} binary value representation of the positive number A sequentially given from a _l-1 to the least significant digit a ₀ and the output of the inverter And an input of the output of the adder and the output of the second switch, and whether or not to store the output of the adder input at the same time depending on the polarity of the output of the second switch, An accumulated value register for outputting the stored value or a doubled value of the stored value as the other input of the adder according to the output of the second switch, Each digit a _{i in the} decimal notation is i = 1
-1 (the most significant digit) is sequentially operated i times for each digit until i = 0 (the least significant digit), and the remainder modulo N of the obtained multiplication values A and B is stored in the accumulated value register. A modular multiplication operator, which is configured to obtain