JPH05738B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> This invention is applicable to input data having a long word length and one
This invention relates to an improvement in an accumulator that quickly accumulates data that is shifted one bit higher than the previous data.

<Prior Art> When performing arithmetic processing on a large amount of data, it is often necessary to add input data at high speed. FIG. 4 shows the configuration of an adder used for such calculations. In FIG. 4, 1 and 2 are registers, and input data A,
B is input and temporarily stored. This stored input data is divided into two parts, an upper bit part and a lower bit part, and input to adders 3 and 4, respectively. The outputs of adders 3 and 4 are input to registers 5 and 6, respectively, and are temporarily held. The data held in registers 5 and 6 are added by adder 7, and the addition result is sent to register 8.
is input and retained. The data held in this register 8 becomes the addition result. That is, in general, the calculation speed of an adder becomes slower as the word length to be calculated becomes longer, so the data is divided into its upper bit part and lower bit part and the adders 3 and 4 calculate them separately.
The adder 7 is used to combine the signals. Further, a register is inserted between each adder, and adders 3 and 4 and adder 7 are operated simultaneously to perform so-called pipeline processing in which processing is performed successively to improve processing speed. When performing accumulation, register 2 is removed and the output of register 8 is input to adders 3 and 4.

<Problems to be Solved by the Invention> However, when such an adder performs accumulation, there is a problem that the processing speed decreases.
That is, when performing addition of two input data A and B, adder 7 can perform the synthesis of the data in registers 5 and 6, and in parallel, adder 3 and 4 can perform partial addition of the next data. However, since the accumulation involves adding new data to the previous accumulation result, the operation of the adder 7 must be completed before the adders 3 and 4 execute the partial addition. Therefore, pipeline processing in which adders 3 and 4 and adder 7 operate simultaneously cannot be executed.

Also, since the order of addition does not affect the addition result, it is possible to perform pipeline processing by adding the two previous accumulation results and the input data. Between a series of data to be accumulated, it is necessary to allow time from holding the data in register 1 until the calculation result appears in register 8, so the process of accumulating the series of data is repeated many times. In such arithmetic processing, it is difficult to improve the operating speed.

<Objective of the Invention> An object of the present invention is to provide an accumulator that can quickly accumulate data in which input data is shifted one bit higher than the previous input data.

<Means for Solving the Problems> In order to solve the above problems, the present invention includes first and second adders into which input data is divided and upper part data and lower part data thereof are input;
a third adder which receives the least significant bit of the output of the first adder and the carry output of the second adder and adds these data;
and a fourth addition section into which the output of the addition section and the carry output of the second addition section are input, and the data obtained by shifting the output of the first addition section downward by one bit and the third addition section are provided. The carry output of the section is input to the first adding section, and these data and the upper part of the divided input data are added together, and the output data of the second adding section is added downward by 1.
Data obtained by adding the output of the third adder to the most significant bit of the bit-shifted data is input to the second adder, and this data and the lower part data of the divided input data are added. It is something.

<Embodiment> FIG. 1 shows an embodiment of an accumulator according to the present invention. In Figure 1, 10 and 11 are the first
adders 101 and 111 and a register 10.
Contains 2,112. The input data has a length of N bits, and the lower M bits are input to the adder 11.
The upper N-M bits are input to one input terminal A of the adder 101. The outputs of adders 101 and 111 are respectively registered in register 1.
02,112 and is held. 12 is a third adder, which includes an adder 121 and a register 122. Adder 121
is a 1-bit adder, and the least significant bit of the output of adder 101 and the carry output Co of adder 111 are input to its input terminals A and B, respectively. Carry output Co and output Y of adder 121 are input to register 122 and held there. The carry output held in the register 122 is input to the carry input terminal Ci of the adder 101. Further, N-M-1 bit data obtained by shifting the output of the register 102 downward by 1 bit is sent to the adder 101.
is input to the other input terminal B of the . Further, M-bit data obtained by adding the output of the adder 121 held in the register 122 to the most significant bit of the data obtained by shifting the output of the register 112 downward by one bit is input to the input terminal B of the adder 111. 13
is the fourth adder, and an adder 131 is installed inside it.
and register 132 are included. Adder 1
31 is an N-M bit adder, one input terminal A of which receives the output of the register 102, and the other input terminal B of which data "0" is input. Moreover, the register 132 is connected to the carry input terminal Ci.
The output of is input. The carry output Co of the adder 111 is input to the register 132 . The lower part of the output data becomes the output of the register 112, and the upper part becomes the output of the adder 131.

Next, the operation of this embodiment will be explained. The entire operation is pipelined and executed in synchronization with input data generation. That is, adder 10
The operations of register 1, 111 and register 122 and the operations of adder 121 and registers 102, 112 are executed simultaneously, and these operations are successively repeated. In such a configuration, the first adder 10 performs the accumulation of the upper NM bits of the input data. That is, one input terminal A of the adder 101 receives partial data of the upper NM bits of the input data, and the other input terminal B receives the accumulated data up to the previous time held in the register 102. is input. Adder 101 performs addition of these two partial data. Note that since the input data is shifted one bit higher than the previous data, the adder 101 receives data obtained by shifting the output data of the register 102 downward by one bit and performing digit alignment. Further, the second addition section 11 executes the accumulation of the lower M bits of the input data. Second
The adder 11 is basically the same as the first adder 10, and an adder 111 adds the lower M bits of the input data and the accumulated results up to that point. In order to perform digit alignment with the input data, the output of the register 112 is shifted downward by one bit and input to the adder 111.

The least significant bit of adder 101 and adder 11
The third adder 12 processes the carry output Co of 1. Input terminal A of adder 121,
The least significant bit of the output of adder 101 input to B and the carry output Co of adder 111 are of the same digit as the M+1 bit of input data, but the operation of the third adder is different from that of the first and second additions. Since the input data is shifted one cycle higher than the previous data, the output of the register 122 ends up being of the same digit as the most significant bit of the data input to the adder 111. , its carry output Co corresponds to the least significant bit of the data input to adder 101. Therefore, the output of register 122 is set to 1, and the output of register 112 is set to 1.
It can be processed by shifting the bits downward to the most significant bit of the data and applying its carry output to the carry input terminal Ci of the adder 101. The fourth adder is operated when the input of a series of data to be accumulated is finished and the input of the next data to be accumulated is started, and the carry of the adder 111 is set to the least significant bit of the upper part data of the output data. Try to add it. Thereby, partial accumulation of a series of continuously input data can be performed in synchronization with the input data.

FIG. 2 shows another embodiment. Note that the same elements as in FIG. 1 are denoted by the same reference numerals, and explanations thereof will be omitted. In FIG. 2, multiplexers 14, 15, and 16 are used to select one of the data at two input terminals. Data 0 is input to one input terminal of the multiplexers 14, 15, and 16, and the value obtained by shifting the output of the register 102 downward by 1 bit and the value of the adder 121 held in the register 122 are input to the other input terminals, respectively. As a carry output, data obtained by shifting the output of register 112 downward by one bit and adding the output of adder 121 held in register 122 to the most significant bit is input. Multiplexers 14, 15, and 16 select data 0 at the beginning of the data to be accumulated, and thereafter select data from registers 102, 122, and 112, respectively. This eliminates the need to clear registers 102, 122, and 112 at the beginning of an accumulation, making it easier to perform multiple accumulations in succession.

FIG. 3 shows yet another embodiment. In the embodiments shown in Figures 1 and 2, the input data is divided into two and accumulated, but as the word length of the input data becomes longer, the operation speed of the adder becomes slower when the input data is divided into two, so it is necessary to divide the input data into three or more. There is. In the example shown in Fig. 3, the input data is 3.
It is divided into individual parts. Note that the same elements as in FIG. 1 are given the same reference numerals and their explanations will be omitted. In FIG. 3, input data is divided into three parts, the upper part of which is input to the first adder 10, the middle part to the adder 17, and the lower part to the second adder 11. The third adders 20 and 21 have the same configuration as the third adder 12. The configuration of the adder 17 is almost the same as the first adder 10, but the adder 171 inside it has a carry output.
There is an adder 201 in the third adder 20
is input to input terminal B of . 18 and 19 correspond to the fourth adder 13 and have almost the same configuration, but the adder 191 in the adder 19 has a carry output Co, and the input terminal of the adder 181 in the adder 18 Connected to B. The operation is almost the same as that of the embodiment shown in FIG. Processing of the least significant bit and the carry output of the second adder 11 is performed by the third adder 21. Furthermore, at the end of the accumulation, the carry outputs of adders 171 and 111 are processed by adders 18 and 19, respectively. Note that the embodiment in FIG. 3 is an example in which the input data is divided into three parts;
By adding an adder 20, it is possible to divide into an arbitrary number. In this case, the carry output of the adder corresponding to the fourth adder is the adder 1
As shown in 8, it is connected to the input terminal B of the adder in the adder on the upper side.

Furthermore, in these embodiments, when shifting the output of the second adder section downward by one bit, the least significant bit is discarded, but this bit is held in the shift register and finally added to the lower part of the output data. You can do it like this. Further, the adder 111 in the second adder 11 may be provided with a carry input, and "1" may be input to the carry terminal to perform "rounding" processing on this bit.

In addition, in the embodiment of FIG. 3, if the number of divisions of input data is increased, the calculation time of the adder 18 corresponding to the fourth adder in the most significant part may become longer than the accumulation cycle. All you have to do is insert registers at appropriate locations and create a pipeline.

<Effects of the Invention> As described above in detail based on the embodiments, in the present invention, in an accumulator that accumulates data whose input data is shifted one bit higher than the previous input data, , the upper bit part of the input data is accumulated by the first adder and the lower bit part by the second adder, and the process such as carry output of the first and second adder is performed by the third adder. The fourth addition unit processes the carry output at the end of the accumulation. Therefore, the processing of the carry output can be executed at the same time as the accumulation, and the processing of the last carry output of the accumulation is carried out in the dedicated fourth adder, so it is possible to increase the speed and to accumulate a series of input data. Processing of the carry output at the end of the calculation can be performed when the next data is input, so multiple accumulations can be performed in real time.

Further, it is easy to expand, and even if input data is divided into three or more parts and accumulated, the processing speed does not decrease, and it is possible to further increase the accumulation speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the structure of an accumulator according to the present invention, FIGS. 2 and 3 are block diagrams showing other embodiments, and FIG. 4 is a block diagram showing the structure of a conventional adder. be. 10...First addition section, 11...Second addition section, 1
2, 20, 21...Third adder, 13...Fourth adder, 14-16...Multiplexer, 17-19
... Addition section, 101, 111, 121, 131, 1
71, 181, 191...Adder, 102, 11
2,122,132...Register.

Claims (1)

[Claims] 1. In an accumulator that accumulates data in which input data is shifted one bit higher than the previous input data, the input data is divided into a plurality of parts, and the upper part data is A first adder to which the input data is input, a second adder to which the lower part data of the input data is input, the least significant bit of the output of the first adder, and a carry output of the second adder. a third addition section into which is input, and a fourth addition section into which the output of the first addition section and the carry output of the second addition section are input; The data whose output is shifted downward by 1 bit and the carry output of the third adder are input to the first adder, and the most significant of the data whose output is shifted downward by 1 bit is input to the first adder. An accumulator characterized in that data obtained by adding the output of the third adder to the bits is input to the second adder.