SU1654814A2 - Multiplier - Google Patents

Abstract

The invention relates to computing, can be used in the development of high-speed devices multiplying numbers, convenient for manufacturing in the composition of large integrated circuits, and is an improvement of the device along. 888109. The purpose of the invention is to increase the reliability of the result of the device calculations. The goal is achieved using intermediate result registers 6.7, adder 8, delay element 9, comparison node 10, element 11 and switch 5. They are used to control the operation of the multiplier, which includes multiplica register 1, n blocks for calculating bit values product and groups of buffer registers 3,4 „2 ill.

Description

The invention relates to computing, can be used in the development of high-speed devices multiplying numbers, convenient for manufacturing as part of large integrated circuits (LSI), and is an improvement of the device according to aut. No. 888109

The purpose of the invention is to increase the reliability of the calculation result of the device.

Figure 1 shows the functional diagram of the device; Fig. 2 shows the algorithms for the operation of the device when multiplying with the control of two factors and when calculating the product of the four factors of the device.

The device (Fig. 1) contains n-bit register 1 of multiplicable, n blocks 2 for calculating discharge product values, buffer registers 3 and 4 of the first and second groups, switch 5, registers 6 and 7 of the intermediate result, one-bit adder 8, the delay element 9, the comparison node 10, the AND element 11, the first installation input 12 of the device, the first input 13 of the device record feature, the second installation input 14 and the second input 15 of the device recording, the device gating input 16, the mode setting input 17

operation of the device, inputs 18 and 19 of the multiplier and multiplier of the device, respectively, input 20 of the device correction, information outputs 21 and 22 of the device, output 23 of the device control, group of outputs 24 n-bit d-legs of register 1, outputs 25, 26 of blocks 2 o

Register 1 is designed to store the n-bit multiplier value, in which recording is made using clock signals in the presence of a resolving potential at their recording inputs and can be performed on synchronous push-pull DV triggers. Re (L

05 O1

-U

00

1H

Gistrs 3 and 4 are designed for storing "the high and low bits of the bit products generated by blocks 2, respectively. Registers 6 and 7 are for storing the higher bits of the factors in a two-bit code and are shift registers in which under the control of the potential at the inputs of the shift control, either information is received from the information inputs, or overwritten from the highest to the lowest bits. Registers 6 and 7 can be implemented on synchronous push-pull DV triggers, which are recorded in the presence of a resolving potential at their recording inputs, like register 6 is equal to (n-1), and register-7 is equal to n Figure 1 conventionally does not show the synchronization chains of all device registers, however, the common synchronization chain of all device registers is used, forming the general synchronization chain of the device.

Blocks 2 are designed to calculate the values of bits of products using the formula

F x "Y + A +

where X9 Y - the corresponding bits

factors;

A, B - bit terms, appearing at the inputs of the first and second terms of block 2.

Blocks 2 can be implemented,

a variety of methods and means depending on the requirements for speed, regularity of the structure, etc., in particular, it can be performed in the form of a ROM (persistent storage device) or in the form of combinational circuits, the synthesis of which can be produced by any of the known methods according to the table

the truth of the functioning of the block.

The one-bit transfer memory adder 8 is designed to convert a two-row multiplication product code into a one-way code. Thereby, the most important work bits are calculated from the information stored in registers 6 and 7. A one-bit adder 8 can be implemented on the basis of a combination of parameters.

Q 5 0 5

0

five

five

0

0

a totalizer and a synchronous DV trigger for storing a transfer having inputs of zeroing and recording. Entry to this trigger is made when there is a resolving potential at the V input. The sync input of the transfer memory trigger is connected to the common synchronization circuit of the device.

The delay element 9 is intended to form the necessary delay of the values of the product bits required when calculating the product of several factors, as well as when performing the check of the formed result. The delay element 9 can be implemented on the basis of a one-bit register built on synchronous push-pull DV triggers, which are recorded in the presence of a resolving potential on their V inputs (recording entry of element 9), and synchronous inputs (not shown) are connected to the shared synchronization circuit of the device.

The device works as follows.

Consider the operation of the device for the following cases:

multiplication of two factors with control (the main operation mode of the device);

function calculation, П А - product of several factors with control.

To clarify the operation of the device, FIG. 2 shows the flowcharts of the algorithm of operation of the device for the main multiplication mode of two n-bit factors with control (a) and when calculating the functions

.P A-s control (where A: is the p-raster of d1 factors) for the case m 4 (6).

In Figure 2, the following symbols are accepted: Y12-Y17 are the signals at the inputs 12-17 of the device, respectively.

It is assumed that with the presence of signals Y15 and Y14, recording from outputs 25 and 26 of block 2 to registers 7 and 6, respectively, and in the absence of Y15 and presence of Y14, information is shifted in registers 6 and 7. It is also assumed that in the presence of potential on Y17,, B, switch 5 is transmitted from the output of delay element 9, and

51

its absence - transmission from the input 18 of the device multiplier

The device in the main mode (Fig „2a) works as follows.

In the initial state (vertex 0, fig. 2a), registers 3 and 4 are reset to zero, register 1 holds the value of the multiplicand without the sign n, switch 5 is configured to transmit information from the input 18 of the device multiplier.

In each of (p-1) the first cycles of operation of the device, the input of the input 18 receives one multiplier value one by one, starting with the least significant number. At the same time, in the i-th block 2, the multiplier of the multiplier arrives at its input multiplier from the output of switch 5, multiplied by the multiplicator’s multiplicated input of the multiplicator 24 of the 24-th register and adds 1 to it. to the younger bit of the resulting two-bit product through the inputs of the first and second components of the 1st block 2, respectively, the highest bit of the product of the 1st block 2, formed in the previous clock cycle and stored in the i-th register 3, and the low-order bit of the product (i + 1) - th block 2, formed In the previous clock cycle stored in the (i-H) -M register 4.5, the highest and the lowest bits of the product generated by the i-th block 2 from its outputs 25 and 26 are written by the signal Y13 to the i-e register 3 and 4, respectively.

In the n-th cycle of operation of the device in blocks 2, a similar multiplication of the multiplicand by the n-th bit is performed.

multiplier, however, at the end of this cycle, simultaneously with recording information from outputs 25 and 26 of blocks 2 (which is the value of the highest n bit of the product of the two factors of the two-way code) in registers 3 and 4, they are recorded in registers 7 and 6, respectively The signals Y14 and Y15, as well as the resetting trigger of transfer of the one-digit adder 8 (vertex n, Fig.2), are zeroed out. At the same time, during the first n cycles from the device, through its information output 21, one bit is output in each cycle and the low bits of the product.

Over the next p cycles to the input 18 of the multiplier device under 14-6

The eiCH is null information, while at the same time, at the first input of the comparison node 10, one bit arrives, starting with the younger ones, the highest n work bits, generated by a one-bit adder 8, from the information stored in registers 6 and 7, and the second input Comparison node 10 receives the same product bits from register 4 output, forming block 2 from information stored in registers 3 and 4. By giving a signal Y16, the error information from the comparison node 10 output passes to the device control output 23.

The output from the device of the value of the highest n bits of the product production during the last n cycles through its first information output 21 or through its second information output 22 — one bit each time. Moreover, when outputting the result through the second output 22 of the device, it is possible immediately after the end of the first n cycles of operation of the device to begin calculating the product of a new pair of factors. In this case, at the end of the nth clock cycle, a signal is sent to the setup input 12 of the device, which is used to reset registers 3 and 4, as well as to record a new multiplicative value in register 1. This device prepares for calculating the product of a new pair of factors, the multiplier value of which is given PA Input device 18, one bit in each of the subsequent n cycles, during which the device operates similarly to the first multiplication. The value of the lowest n bits of the new product is output from the device through its first information output 21 one bit in each clock cycle, simultaneously with the output of the high bits of the previous product through the second information output 22. In this case, control over the operation of the device is impossible.

Until now, it has been assumed that zero information is supplied to the input 20 of the device correction in all the cycles of its operation. In the same cases, when a rounded product is required to be obtained, it is necessary in the first step of the device operation to submit its correction information to its input 20.

(to round the 2n-bit product of n-bit factors multiplicatively represented in the binary-coded hexadecimal number system, it is necessary to submit the binary code 1000 to the input 20 in the first operation cycle J). In order to round up the multiplier pairs, when calculating them sequentially, it is necessary to submit corrective information to the input 20 of the device simultaneously with the input to the input 18 of the multiplier of the first bit of each multiplier. This allows rounding of the result without additional time costs. In addition, the device input 20 can be used to enter the resulting correction to the multiplicand and multiplier characters in the case of multiplying numbers in the additional code.

When calculating the function .PA-

) i J

The device additionally uses a switch 5 to feed the inputs of a multiplier of 2 bits of intermediate work calculated by adder 8 from the information obtained in the previous cycle and stored in registers b and 7. The total operation time of the device can be divided into three stages: in the first stage, the first two factors are multiplied; in the second, the product is multiplied with the other factors, and the third stage carries out the obtained result with the control. The first stage includes n cycles, the second stage consists of () cycles, each of which includes (n + 1) cycles, and the third stage consists of n cycles. Thus, the total time

calculation function P is

} (

(t-2) (n + 1) + 2-n cycles.

Consider the operation of the device, use for the explanation of FIG. In the initial state, registers 3 and 4 are zeroed out. Register 1 is stored without the sign of the n-bit value of the first factor. Switch 5 is configured to transmit information from input 18 of the device multiplier (signal Y17 is missing).

In each of the first n cycles of operation of the device (the first stage), and its input 18 of the multiplier is supplied by the same bit as the second factor, and the same operations are performed as in the main multiplication mode of the two factors, i.e. calculation is performed

the products of the first two factors and the recording of its higher n bits in the form of a two-bit code into registers b and 7. However, in the n-th cycle, the signal Y12 is applied, under the action of which registers 3 and k are set to zero state and the next (third) factor is written to register 1.

At the second stage of the device operation, (t-2) similar cycles are performed.

Before the start of each of the (t-2) cycles, registers 3 and 4 are zeroed, register 1 stores the value of the next multiplier without a sign, registers b and 7 store the value n of the higher digits of the previous cycle in registers b and 7, and transfer accumulation trigger 8 cleared.

Then, in each of the (t-2) cycles in the device, two functions are implemented in parallel: calculating one bit in each clock cycle of the highest n bits of the previous cycle using a one-bit adder 8 from the information stored in registers b and 7, and calculating The new product using blocks 2, using as multiplier the value of the next multiplier stored in register t, and as a multiplier - the highest n bits of the previous and previous cycle output from the output 30 of delay element 9 through switch 5 are configured signal Y17) to the inputs of the multiplier of blocks 2 "Thus, starting from the second cycle of each of (t-2) cycles., in blocks 2, operations similar to the first steps of the device are performed, and to the inputs of the multiplier of blocks 2 bit, starting from the lowest value of the product of the previous cycle, calculated by a one-bit adder 8 of the information stored in registers b and 7 (in the first cycle of each of (t-2) cycles, the least significant bit of this product is recorded in delay element 9), and the inputs of the multiplicand block 2 receive the value the next multiplier from the outputs of the 24 register 1 multiplicand.

In (n + 1) m cycle of each of (t-2) cyclvs, the value of the higher n bits of the new product in the two-row code is written from the outputs 25 and 26 of blocks 2 to registers 7

and 6, respectively, and also (except for (n + 1) -th cycle of the last (t-2) -th cycle), the registers 3 and 4 are reset and the value of the next factor is loaded into register 1. In (n + 1) -th cycle (t-2) -th cycle, recording of the higher n digits of the production of n A is made in a two-dvr code

i "r J

from outputs 25 and 26 of block 2 to registers 7 and 6, and also to corresponding registers 3 and 4. In the third stage, n more cycles are performed, during which the higher n bits of the result are output from the device with control, like the last cycles basically multiply two multiplier mode

The output of the 2-n bit value of product A is carried out in

 J

device as follows: the low-order n bits are output through the first information output 21 of the device, one bit in each cycle (t-2) -th cycle, starting with the second, cycle, and the major n bits either through the first 21 or through the second information outputs of the device, one bit in each of the n last cycles of operation of the device (in the third stage of operation of the device). At the same time, simultaneously with the output of the higher-order bits of the result, it is possible to monitor the operability of the nodes and units of the device by comparing in the node 10 values of each of the higher-order bits of the result, formed in parallel by one-bit adders 8 and blocks 2 independently of each other. The output of the error signal at the device control output 23 is enabled by applying the control signal Y16. The device correction input 20 can also be used in this mode of operation to round the result and enter the necessary correction by the signs when multiplying numbers in the additional

code.

Claims (1)

Invention Formula Device for multiplying by aut. St. No. 888109, differing 0 0 By the fact that, in order to increase the reliability of the calculation result of the device, two intermediate result registers, a switch, a one-bit adder, a delay element, a comparison node and an AND element are entered into it, and the low-level output of each of the n blocks for calculating the group values , except for the first one, is connected to the corresponding bit of the information input of the first register of the intermediate result, the output of the high bit is , the corresponding bit of the information input of the second register of the intermediate result, the information outputs of the first and second registers of the intermediate result are connected respectively to the inputs of the first and second operands of a one-bit adder, the output of which is connected to the information input of the delay element whose output is connected to the first information inputs of the comparison node and the switch, the output of the comparison node is connected to the first input of the AND element, the output of which is the control output of the device the output of the first buffer register of the second group is connected to the second information input of the comparison node, the second information input of the switch is connected to the input of the device multiplier, the control input of the switch is connected to the input of the device operation mode, the output of the switch is connected to the second inputs of the units for calculating bit values  group, the output of the delay element is, respectively, the second information output of the device, the setup inputs and the write inputs of the first and second registers of the intermediate result are connected respectively to the second 0 five five 0 the installation input and the second input of the device record, the installation input and the write input of the counter, respectively, to the second installation input and the second input of the device record, the second input of the I element - to the input of the sc. quoting, devices.