JPH0330905B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic computing device that performs vector arithmetic processing. In particular, the present invention relates to a vector calculation parallel processing method in which processing is performed using a plurality of vector calculation pipeline sets.

[Conventional technology]

Conventionally, in this type of vector arithmetic processing device, as shown in FIG. 3, a plurality of vector registers each including a plurality of vector elements are arranged in a plurality of banks as indicated by reference numerals 2a to 2d in the drawing. Circuits for sequentially reading vector elements from these vector registers are constituted by operand selection circuits as shown in figures 3a to 3d. The operands selected in this crossbar circuit are shown in drawing numbers 4a to 4d, 5a to 5d, and 6.
The signals are supplied to vector arithmetic units indicated by a to 6d, 7a to 7d, etc. This vector arithmetic unit is a floating point adder, a floating point multiplier, a logical arithmetic unit, a shift arithmetic unit, a floating point divider, etc. The output of the vector calculator is input to input circuits 1a to 1d.

These input circuits 1a to 1d are connected to a memory read bus 10 through which vector data is read out from a main memory (not shown) in which vector data is stored.
0 and the output of the vector arithmetic unit.

Reference numeral 9 in the drawing is a scalar register in which scalar data is stored. The parts 11, 12, and 13 in the drawing constitute a scalar arithmetic unit that processes scalar data, and include a floating-point adder, a multiplier, a divider,
Includes fixed-point shifters, etc. Reference numeral 10 in the drawing is a distributor that supplies the output of the scalar register 9 to the input of the scalar arithmetic unit. Reference numeral 8 in the drawings denotes an input circuit that switches between the output of the scalar arithmetic unit and a memory read path 200 for scalar data from a main storage device (not shown).

[Problem that the invention seeks to solve]

In such conventional vector arithmetic processing devices,
The vector arithmetic unit in the vector arithmetic pipeline set and the scalar arithmetic unit have the same function, resulting in an increase in the amount of hardware.

The present invention pipelines the scalar data arithmetic unit, eliminates the need for the vector arithmetic unit conventionally provided in the vector arithmetic pipeline set, and shares vector arithmetic operations with the scalar arithmetic unit in the vector arithmetic pipeline set for execution control. It is an object of the present invention to provide a vector arithmetic processing device that solves the above-mentioned drawbacks and reduces the required amount of hardware by having a rational configuration.

[Means for solving problems]

The present invention consists of a vector operation that interleaves and arranges vector elements in correspondence with a vector operation pipeline set, reads the vector elements simultaneously and processes the vector operations in parallel, and a scalar operation processing circuit that processes scalar data in a scalar register. In the vector arithmetic processing device, the vector arithmetic pipeline set includes a plurality of vector registers, a plurality of in-set vector arithmetic units, an operand selection circuit that sequentially extracts vector elements from the vector registers, and an operand selection circuit. A circuit for supplying the output of the circuit to the vector arithmetic unit in the set, and a means for writing the output of the vector arithmetic unit in the set to the vector register, a vector scalar selection circuit that switches the output of the vector scalar selection circuit and the output of the scalar register; a vector scalar shared arithmetic unit that uses the output of the vector scalar selection circuit as an operand; It is characterized by a structure in which the vector calculation pipeline set and the vector scalar shared calculation unit perform calculations and control in a manner that distinguishes between the vector calculation pipeline set and the vector scalar shared calculation unit depending on the type of calculation.

[Effect]

The present invention uses a pipeline configuration for scalar data dividers, eliminates the need for vector dividers that are conventionally provided in a vector calculation pipeline set for the number of vector calculation pipeline sets, and shares the dividers for all vector calculation pipeline sets. By configuring this to be executed and controlled in common with the scalar arithmetic unit, processing time can be rationalized and shortened, and the amount of metal required can be significantly reduced.

〔Example〕

Next, the present invention will be explained using an embodiment of the apparatus shown in FIG. Input circuit 1 to which the memory transfer bus 300 inputs
The outputs of a to 1d are sent to vector register groups 2a to 2.
Enter in d. These are vector registers consisting of eight vector registers each containing 64 words of 8-byte (64-bit) vector elements. Further, each of the parts 3a to 3d connected to these is an 8B wide operand selection circuit that selects a vector register to be subjected to a vector operation from among eight vector registers. Portions 4a to 4d connected to this circuit are intra-set floating point adders that process 8B wide two-input floating point addition in a pipeline manner. Similarly connected parts 5a to 5d are
This is an in-set floating point multiplier that processes 8B wide 2-input floating point multiplication in a pipeline manner. Further, similarly connected portions 6a to 6d are intra-set shift computing units that process the function of shifting 8B wide fixed point data in a pipeline manner.

Input circuits 1a to 1d include a memory transfer bus 100 for vector data read from a storage device storing vector data (not shown), vector floating point adders 4a to 4d, multipliers 5a to 5d, This circuit switches between the outputs of the intra-set shift calculation units 6a to 6d. A scalar data read bus 200 is input via the input circuit 8 . Reference numeral 9 in the drawing is a scalar register that stores scalar data. Reference numeral 28 is a vector scalar selection circuit connected to switch between the output of the scalar register 9 and the output of the operand selection circuits 3a to 3d in the vector operation pipeline set. This vector scalar selection circuit 28
The output of is supplied to a vector-scalar shared divider 29. The output of this vector scalar shared divider 29 is connected back to the input circuit 8. This input circuit 8
is a scalar data read bus 40 from main memory.
This circuit switches between 0 and the output of the vector scalar shared divider 29. Vector calculation control circuit 3
5 controls each of the arithmetic pipelines and scalar arithmetic processing circuits.

FIG. 2 is a block diagram of the vector-scalar shared divider 29. Reference numeral 30 in the figure is a preprocessing circuit for floating point division, which searches for an approximate reciprocal of the divisor from the reciprocal table. Reference numeral 31 in the figure is a quotient generating circuit that processes the intermediate quotient four times in units of 14 bits to calculate a 56-bit quotient. Also, drawing code 33
is a floating point exponent processing circuit. The vector elements in the vector register of each of these vector operation pipeline sets are interleaved corresponding to each vector operation pipeline, and N+θ,
Control is performed during vector loading so that the N+1, N+2, and N+3 (N is an integer including θ) vector elements are arranged in vector registers 2a, 2b, 2c, and 2d, respectively. Among vector operations, for vector addition, multiplication, and shift operations, four vector elements are simultaneously selected by operand selection circuits 3a to 3d from vector registers 2a to 2d specified by vector instructions, and in the case of vector addition, four vector elements are selected at the same time from vector registers 2a to 2d specified by vector instructions. Internal floating point adder 4a~
4d, in the case of vector multiplication, the intra-set floating point multipliers 5a to 5d process vector operations for one vector element in one machine cycle, and in the case of vector shift selection, the intra-set shift calculation units 6a to 6d process vector operations.

These results are written into vector registers 2a-2d via input circuits 1a-1d. For vector division, the vector scalar sharing selection circuit 28 selects the N+θth vector element in the vector register 2a, the N+1th vector element in the vector register 2b, and the Nth vector element in the vector register 2c.
+3rd vector element, vector register 2
The N+3rd vector element in ad is sequentially read out and the vector scalar shared divider 29 processes the vector division. Regarding scalar division, scalar data is read from the scalar register 27, the scalar data is selected by the vector scalar sharing selection circuit 28, and the scalar division is executed by the vector scalar sharing divider 29.

As described above, the scalar data divider is configured in a pipeline, eliminating the need for the vector dividers that were provided in the conventional vector calculation pipeline set for the number of vector calculation pipeline sets, and sharing them among all vector calculation pipeline sets. In addition, by having a configuration in which execution control is shared with a scalar arithmetic unit, it is possible to provide a vector arithmetic processing device that can significantly reduce the amount of hardware. .

〔Effect of the invention〕

As explained above, the present invention makes it possible to rationalize and shorten the processing time and to significantly reduce the required amount of hardware by pipelineizing the scalar divider and sharing the configuration with the shared vector divider in the vector operation pipeline set. effective.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of the present invention, and FIG. 2 is a detailed block configuration diagram of a portion of FIG. 1. FIG. 3 is a block diagram showing a conventional device. 1a to 1d...input circuit, 2a to 2d...vector register, 3a to 3d...operand selection circuit, 4a to 4d...internal floating point adder,
5a to 5d... in-set floating point multiplier, 6a
~6d...Intra-set shift calculator, 7a~7d...
...Vector arithmetic unit in set, 8...Input circuit, 9
...Scalar register, 10...Distributor, 11...
Scalar adder, 12... Scalar multiplier, 13...
Scalar divider, 28...Vector scalar sharing selection circuit, 29...Vector scalar sharing divider, 30
...Division preprocessing circuit, 31...Division quotient generation circuit,
32...Division post-processing circuit, 33...Floating point exponent part processing circuit, 34...Vector division control circuit,
35...Vector calculation control circuit.

Claims (1)

[Claims] 1. A vector calculation pipeline is provided for each interleaved vector element to be input, a scalar calculation processing circuit is provided for each input scalar amount, and each of the vector calculation pipelines takes in an input signal. an input circuit; a multi-stage vector register connected to this input circuit; an operand selection circuit that sequentially extracts vector elements from this vector register; a first vector arithmetic unit connected to this operand selection circuit; circuit means for connecting the output of the arithmetic unit to the input circuit, the scalar arithmetic processing circuit comprising: an input circuit that takes in an input signal; a plurality of stages of scalar registers connected to this input circuit; In a vector arithmetic processing device that includes a scalar arithmetic unit that operates on output data, and is equipped with a vector arithmetic control circuit that controls the arithmetic pipeline and the scalar arithmetic processing circuit, the output of the operand selection circuit is sequentially extracted. A selection means common to each pipeline is provided, the output of the scalar register is connected to the input of the selection means, the output of the selection means is input, and the operation common to the vector operation pipeline and the scalar operation processing circuit is performed. and circuit means for connecting the output of the arithmetic unit to the input circuit of the vector arithmetic pipeline and the scalar arithmetic processing circuit, and the vector arithmetic control circuit includes the vector arithmetic unit that corresponds to the type of arithmetic operation. A vector arithmetic processing device characterized by comprising means for separately executing arithmetic operations between the common arithmetic unit and the common arithmetic unit.