JPS6125274A - Vector arithmetic processor - Google Patents

Abstract

PURPOSE:To shorten and rationalize the processing time and furthermore to reduce hardware quantity by converting a scalar divider into a pipeline and sharing the constitution of said pipeline with a set shared vector divider for pipeline. CONSTITUTION:For vector division, the (N+theta)-th vector element in a vector register 2a, the (N+1)-th vector element in a vector register 2b, the (N+2)-th vector element in a vector register 2c and the (N+3)-th vector element in a vector register 2d are read out successively by a scalar shared selection circuit 28. Then a vector scalar shared divider 29 performs the vector divisions. For scalar division, the scalar data are read out of a scalar register 27 and then selected by the circuit 28. Then the divider 29 executes the scalar divisions.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic computing device that performs vector arithmetic processing. In particular, the present invention relates to a vector calculation parallel processing method in which processing is performed using a plurality of vector calculation pipeline cents.

[Conventional technology]

Conventionally, in this type of vector arithmetic processing device, as shown in FIG. 3, a plurality of vector registers each including a plurality of vector elements are arranged in a plurality of banks as indicated by reference numerals 28 to 2d in the drawing. Circuits for sequentially reading vector elements from these vector registers are constituted by operand selection circuits as indicated by reference numerals 38 to 3d in the drawing. The operands selected by this crossbar circuit are shown in the figure with reference numerals 4a to 4d and 5a.
~5d, 6a~6d, 7a~7d, etc. are supplied to vector computing units. This vector arithmetic unit is a floating point adder, a floating point multiplier, a logical arithmetic unit, a shift arithmetic unit, a floating point divider, etc. The output of the vector calculator is input to input circuits 18-1d.

The input circuits 18 to 1d read vector data from a main memory (not shown) in which vector data is stored, and switch between the memory read bus 100 shown and the output of the vector arithmetic unit.

Reference numeral 9 in the drawing is a scalar register in which scalar data is stored. Each part indicated by reference numerals 1112 and 13 constitutes a scalar arithmetic unit that processes scalar data, and includes a floating point adder, a multiplier, a divider, a fixed point shifter, and the like. Reference numeral 10 in the drawing is a distributor that supplies the output of the scalar register 9 to the input of the scalar arithmetic unit. Reference numeral 8 in the figure is an input circuit that switches between the output of the scalar arithmetic unit and a memory read bus 200 for scalar data from a main storage device (not shown).

[Problem that the invention seeks to solve]

In such a conventional vector arithmetic processing device, the in-set vector arithmetic unit in the vector arithmetic pipeline set and the scalar arithmetic unit have the same function, resulting in an increase in the amount of hardware. There was a drawback that led to

The present invention pipelines a scalar data arithmetic unit,
The above drawbacks are solved by eliminating the need for the vector arithmetic unit provided in the conventional vector arithmetic pipeline set, and adopting a rational configuration in which vector arithmetic is shared by a scalar arithmetic unit with the vector arithmetic pipeline center for execution control. Providing a vector calculation processing device that reduces the amount of hardware required.
The purpose is to

[Means for solving problems]

The present invention provides a vector arithmetic circuit that interleaves and arranges vector elements in correspondence with a vector arithmetic pipeline set, reads the vector elements simultaneously and processes vector arithmetic operations in parallel, and a scalar arithmetic processing circuit that processes scalar data in a scalar register. In the vector arithmetic processing device, the vector arithmetic pipeline set includes a plurality of vector registers i, a plurality of in-set vector arithmetic units, an operand selection circuit that sequentially extracts vector elements from the vector data, and an operand The operand selection circuit in the vector calculation pipeline center is comprised of a circuit for supplying the output of the selection circuit to the vector calculation unit in the set, and means for writing the output of the vector calculation unit in the set to the vector register. a vector scalar selection circuit that switches between the output of the vector scalar selection circuit and the output of the scalar register; a vector scalar shared arithmetic unit that uses the output of the vector scalar selection circuit as an operand;・
and a means for writing into the scalar register, and is characterized in that the vector calculation pipeline cent and the vector scalar shared calculation unit are configured to perform calculations and control in a manner that distinguishes between the vector calculation pipeline center and the vector scalar shared calculation unit depending on the type of calculation.

[For production]

The present invention uses a pipeline configuration for the divider for NUCARRA data, eliminates the need for vector dividers that are provided for the number of vector operation pipeline sets in the conventional vector operation pipeline center, and shares the dividers for all vector operation pipeline sets. , and is configured to be executed and controlled in common with a scalar arithmetic unit, thereby streamlining and shortening the processing time, and in turn realizing a significant reduction in the amount of metal required.

〔Example〕

Next, the present invention will be explained using an embodiment of the apparatus shown in FIG. The outputs of input circuits 1a-1d to which memory transfer bus 300 is input are input to vector register groups 28-2d. These are vector registers consisting of eight vector registers each containing 64 words of 8-byte (64-bit) vector elements. Also, each part 3 connected to these
8 to 3d are 8B wide operand selection circuits that select a vector register to be subjected to a vector operation from among eight vector registers. Portions 4a-4 connected to this circuit
d is an intra-cent floating point adder that processes 8B wide two-input floating point addition in a pipeline manner.

Similarly connected portions 5a to 5d are intra-cent floating point multipliers that process 8B width two-input floating point multiplication in a pipeline manner. Further, similarly connected portions 6a~
6d is an intra-set shift calculator that processes the function of shifting 8B wide fixed-point data in a pipeline manner.

Input circuits 1a to 1d include a memory transfer bus 100 for vector data read from a main storage device in which vector data (not shown) is stored, the in-set vector floating point adders 48 to 4d, multipliers 5a to 5d, This circuit switches between the outputs of the intra-set shift calculation units 08 to 6d. The scalar data successive bus 200 is inputted via the input circuit 8 . Reference numeral 9 in the drawing is a scalar register that stores scalar data. Reference numeral 28 is a vector scalar selection circuit connected to switch between the output of the scalar register 9 and the output of the operand selection circuits 3a to 3d in the vector operation pipeline center. The output of this vector-scalar selection circuit 28 is supplied to a vector-scalar shared divider 29. This vector scalar shared divider 2
The output of 9 is connected back to the input circuit 8. This input circuit 8 is a circuit that switches between the scalar data read bus 400 from the main memory and the output of the vector calculation and shared divider 29. The vector arithmetic control circuit 35 controls each arithmetic pipeline and the scalar arithmetic processing circuit.

FIG. 2 is a block diagram of the vector-scalar shared divider 29. Reference numeral 30 in the figure is a preprocessing circuit for floating point division, which searches the reciprocal table for the transmitted reciprocal of the divisor. Reference numeral 31 in the figure is a high generation circuit that processes the intermediate direction four times in units of 14 bits and calculates the quotient of 56 bits.

Further, reference numeral 32 in the drawing is a post-normalization circuit for post-processing of division. Reference numeral 33 is a floating point exponent processing circuit. The vector elements in the vector register of each vector operation pipeline set are interleaved corresponding to each vector operation pipeline, and are N+θ, N−).
1. Control is performed during vector loading so that vector elements numbered N+2 and N+3 (N is an integer including θ) are arranged in vector registers 2a, 2b, 2c, and jd, respectively. Among vector operations, for vector addition, multiplication, and shift operations, four vector elements are simultaneously selected by operand selection circuits 38 to 3d from the vector registers 28 to 2d designated by the vector instruction;
For vector addition, in-set floating point adders 48-4
At d, in the case of vector multiplication, the intra-cent floating point multipliers 58 to 5d process vector operations for one vector element in one machine cycle, and in the case of vector shift operations, the intra-set shift arithmetic units 68 to 6d process.

These results are written to vector registers 28-2d via input circuits 18-1d. For vector division, the vector scalar sharing selection circuit 28 selects the N+θth vector element in the vector register 2a, the N+1st vector element in the vector register 2b, the N+2nd vector element in the vector register 2c, and the N+θth vector element in the vector register 2d. The N+3rd vector element is sequentially read out and vector division is processed by the vector scalar shared divider 29.

For scalar division, scalar data is stored in scalar register 2.
7, the scalar data is selected by the vector scalar sharing selection circuit 28, and the scalar data is read out from the vector scalar sharing divider 2.
A scalar division is performed at 9.

As described above, the Scala Dake divider is configured in a pipeline, eliminating the need for the vector dividers that were provided in the conventional vector calculation pipeline set for the number of vector calculation biplins, and sharing them with all vector calculation pipeline sets. By adopting a configuration that performs shared execution control with a scalar arithmetic unit, it is possible to provide a vector arithmetic processing device that significantly reduces the amount of hardware required.

〔Effect of the invention〕

As explained above, the present invention makes it possible to rationalize and shorten the processing time and to significantly reduce the amount of hardware required by pipelineizing the scalar divider and sharing the configuration with the vector arithmetic pipeline center shared vector divider. effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a detailed block diagram of a portion of FIG. 1. FIG. 3 is a block diagram showing a conventional device. 18-1d... Input circuit, 2a-2d... Vector register, 3a-3d... Operand selection circuit, 4a
. ~4d... floating point adder in cents, 5a~5d・
... Floating point multiplier in set, 68-6d... Shift operator in set, 78-7d... Vector operator in cent, 8... Input circuit, 9... Scalar register,
10...Distributor, 11...Scalar adder, 12...
・Scalar multiplier, 13... Scalar divider, 28...
Vector scalar sharing selection circuit, 29... Vector scalar sharing divider, 30... Division preprocessing circuit, 31...
Division quotient generation circuit, 32... Division post-processing circuit, 33...
- Floating point exponent part processing circuit 14...Vector division control circuit, 35...Vector calculation control circuit. Oni 1 RoO ¥-) 3 prefectures

Claims (1)

[Claims] (1) A vector calculation pipeline is provided corresponding to the input interleaved vector elements, a scalar calculation processing circuit is provided corresponding to the input scalar amount, and each of the vector calculation pipelines has an input circuit that takes in the input signal, A multi-stage vector register connected to this input circuit, an operand selection circuit that sequentially extracts vector elements from this vector register, a first vector calculation unit connected to this operand selection circuit, and an output of this calculation unit. The scalar arithmetic processing circuit includes: an input circuit that takes in an input signal; a multi-stage scalar register connected to the input circuit; and a circuit that connects the input signal to the input circuit. a scalar arithmetic unit that operates, and a vector arithmetic control circuit that controls the arithmetic pipeline and the scalar arithmetic processing circuit; A common selection means is provided, the output of the scalar register is connected to the input of the selection means, the output of the selection means is input, and the arithmetic unit is common to the vector operation pipeline and the scalar operation processing circuit; circuit means for connecting the output of the arithmetic unit to the vector arithmetic pipeline and the input circuit of the scalar arithmetic processing circuit; A vector arithmetic processing device characterized by comprising means for executing arithmetic operations separately from arithmetic units.