JPH0149973B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a circuit for calculating the absolute value of a difference between binary numbers.

[Description of prior art]

Conventionally, in a circuit for calculating the absolute value of the difference between two binary numbers X and Y, the one's complement of Y, the X, and an auxiliary input to the least significant bit are input to one or more full adders, It is determined whether X≧Y or X≦Y by the carry output from the top of the full adder, and when X≧Y, X-Y=X++1, and when X≦Y, Y-
By calculating X=X+ (one's complement of X+), the absolute value |X-Y| of the difference between the two numbers X and Y is output.

The configuration of this absolute value arithmetic circuit is basically divided into two parts: one is a feedback circuit from the most significant carry output of the full adder to the least significant auxiliary input, so that when X≧Y; One method uses the same full adder for calculations when X≦Y, and the other method separates calculations when X≧Y and X≦Y and uses multiple full adders. It's a method.

FIG. 1 shows an example of an absolute value calculation circuit using the former method, and FIG. 2 shows an example of an absolute value calculation circuit using the latter method. In FIG. 1, two binary numbers X and Y are input directly to the full adder 120 through the signal line 10, and after inputting Y to each bit inversion circuit 110 through the signal line 11, It is input to the full adder 120 through the signal line 12. The most significant carry output C0 of the full adder 120 is input to the selection circuit 130 through the signal line 13 and at the same time is input to the full adder 1 through the signal line 14.
It serves as an auxiliary input for the 20 least significant bits. The sum S of the full adder 120 passes through the signal line 15 to the selection circuit 130.
At the same time, it passes through each bit inversion circuit 140, becomes the one's complement of the sum S, and becomes an input to the selection circuit 130 through the signal line 16. The selection circuit 130 selects the sum S, its one's complement,
The above carry output C0 is input, and the carry output C0
When is 1, select sum S, and carry output
When C0 is 0, the one's complement of the sum S is selected as Z, and is output from the signal line 17. Here Z is 2
This is the absolute value of the difference between the numbers X and Y.

Also, in Figure 2, the two binary numbers X and Y are
X passes through signal line 20 to full adders 220 and 2
Y is input to each bit inversion circuit 210 through a signal line 21, and then input to full adders 220 and 221 through a signal line 22. The auxiliary input of the least significant bit of full adder 220 is set to 0. The sum S0 of the full adder 220 is passed through each bit inversion circuit 240 from the signal line 25, and is added to the sum S0.
The one's complement of S0 is 0, which passes through the signal line 26 and is input to the selection circuit 230. The most significant carry output C0 of the full adder 220 passes through the signal line 23 and becomes an input to the selection circuit 230. The auxiliary input of the least significant bit of full adder 221 is set to 1. This full adder 221
The sum S1 is input to the selection circuit 230 through the signal line 28. The selection circuit 230 selects the sum S1 and
The one's complement 0 of the sum S0 and the carry output C0 are input, and when the carry output C0 is 1, the sum S1
When the carry output C0 is 0, the sum is 0.
Select the side and set it to Z, and output from the signal line 27.
Here, Z is the absolute value of the difference between the two numbers X and Y.

In these circuits shown in FIGS. 1 and 2, even if input X and input Y are M-bit binary numbers, and it is known that all of the lower N bits of Y are 0, , all M bits of the 1's complement of Y are used in calculations, so the full adder used has M bits of digits, and the carry propagation time is long until the sum is determined. was a major factor in lowering the arithmetic performance of the entire absolute value arithmetic circuit.

[Purpose of the invention]

An object of the present invention is to input two M-bit binary inputs in which, when it is known that the lower N bits of one of the inputs are 0, the lower N bits and upper M-N bits of that input are
The object of the present invention is to provide an absolute value calculation circuit which solves the above-mentioned drawbacks by performing calculations separately from bits, shortens calculation time, and reduces the amount of hardware.

[Features of the invention]

The absolute value calculation circuit of the present invention calculates the binary number X2 of the lower N bits of the binary number It includes a logical sum circuit that creates a logical sum C1 of all bits, and the binary number X1 of the upper M-N bit part of the M-bit binary number X and this logical sum C1
, that is, X1 + C1, and the binary number Y1 of the upper MN bit part of the M-bit binary number Y is determined, and when X1 + C1 > Y1, X1 - Y1
is calculated and output as the upper MN bit part of the absolute value Z, and the judgment signal C0=1 is output, and X1+
When C1≦Y1, an auxiliary input absolute value calculation circuit calculates X1+C1−Y1 and outputs it as the upper M−N bit part of the absolute value Z, and also outputs a judgment signal C0=0, and the two's complement of the binary number X2. A complement generation circuit that calculates and outputs X3 receives the binary number X2 and the complement X3 as input, selects either the binary number X2 or the complement X3 according to the judgment signal C0, and calculates the absolute value Z. The present invention is characterized in that it includes a selection circuit that outputs the lower N bits of the data.

[Explanation based on examples]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 3 is a block diagram of an absolute value calculation circuit according to an embodiment of the present invention, and FIG. 4 is a diagram showing the bit configuration of binary numbers X and Y to be calculated and the calculation output Z. As shown in FIG. 4, binary numbers X and Y consist of M bits, and it is known that the lower N bits of the M bits of binary number Y are 0, and the upper M−N bits are the binary number. Represented by Y1. Furthermore, the lower N bits of the binary number X are expressed as the binary number X2, and the upper M-
The N bit part is represented by a binary number X1. Furthermore, the lower N bits of the binary number Z are represented by the binary number Z2, and the higher M−N bits are represented by the binary number Z1.

In Figure 3, the above binary numbers Y1, X1 and X2
The respective outputs are connected to signal lines 30, 31 and 3, respectively.
2 to the input of the absolute value calculation circuit 300 with auxiliary input. This signal line 32 branches into signal lines 34 and 35, and the signal line 34 is connected to the complement generation circuit 3.
10, and the signal line 35 is connected to the selection circuit 3.
Connected to 20 inputs. Also, the complement generation circuit 31
The output of 0 is connected to the input of selection circuit 320 through signal line 36. The determination output of the arithmetic circuit 300 is connected to the input of a selection circuit 320 through a signal line 37. This arithmetic circuit 300 is connected to the signal line 38 and outputs a binary number Z1, and the selection circuit 320
is connected to the signal line 39 and outputs the binary number Z2.

In a circuit configured like this, binary numbers X and Y
is input, the binary number Y1 of the upper M−N bits of the binary number Y passes through the signal line 30, and the binary number Y1 of the upper M−N bits of the binary number Y passes through the signal line
The binary number X1 of the upper M−N bits of the base number X is inputted to the absolute value calculation circuit 300 with auxiliary input through the signal line 31. Binary number of the lower N bits of the binary number X
X2 is inputted to the absolute value calculation circuit 300 with auxiliary input through the signal line 32, inputted to the complement generation circuit 310 through the signal line 34, and inputted to the selection circuit 320 through the signal line 35. The auxiliary input absolute value calculation circuit 300 receives the binary number Y1 and the binary number Y1.
When X1 and the binary number X2 are input, the logical sum C1 of all bits of the binary number
It determines whether X1+C1≦Y1 and outputs the determination signal C0 to the selection circuit 320 through the signal line 37, and when X1+C1>Y1, calculates X1−Y1,
When X1+C1≦Y1, Y1-X1-C1 is calculated and the binary number Z1 resulting from the calculation is outputted through the signal line 37. Here, the binary number Z1 is the upper M-N bits of the absolute value |X-Y| of the difference between the two M-bit binary numbers X and Y.

When the complement generating circuit 310 receives the binary number X2, it outputs the two's complement X3 of X2 to the selection circuit 320 through the signal line 36. The selection circuit 320 selects the binary number X2, the complement X3, and the determination signal C0.
When this is input, either the binary number X2 or its complement X3 is selected depending on whether the determination signal C0 is 1 or 0, and the binary number Z2 is outputted through the signal line 39.
Here, the binary number Z2 is the lower N bits of the absolute value |X-Y| of the difference between the two M-bit binary numbers X and Y.

Next, the detailed block configuration of the absolute value calculation circuit 300 with auxiliary input shown in FIG. 3 will be explained with reference to FIG. In FIG. 5, signal line 32 is connected to the input of OR circuit 400. In FIG. Further, the signal line 31 is connected to the input of a full adder 420. Further, the signal line 30 is connected to each bit inversion circuit 410 and the signal line 40.
is connected to the input of full adder 420 via . The output of the OR circuit 400 is connected to one input of the OR 430 via a signal line 41, and the determination signal output of the full adder 420 is connected to the other input via a signal line 42. The output of this OR circuit 430 is connected to the auxiliary input of the full adder 420 via a signal line 43. The output of the full adder 420 is directly connected to the input of the selection circuit 440 via a signal line 45, and is also connected to the input of the selection circuit 440 via each bit inversion circuit 450 and a signal line 46. Further, the determination output of the full adder 420 is connected to the signal line 37. This signal line 37 is the signal line 47
and branches into the signal line 42, and the signal line 47 is connected to the input of a selection circuit 440. The output of this selection circuit 440 is connected to the signal line 38 .

In a circuit with such a configuration, the binary number
10 and when the binary number X1 is input to the full adder 420 through the signal line 31, the OR circuit 4
00 sets the OR signal C1 to 0 only when all bits of the binary number
Set C1 to 1. This OR signal C1 is the signal line 41
It is input to the OR circuit 430 through. When the binary number Y1 is input to each bit inversion circuit 410,
Invert each bit of binary number Y1 and convert it to 1 of binary number Y1.
The complement 1 of 1 is passed through the signal line 40 to the full adder 420
Output to. The full adder 420 receives the binary number X1
, the binary number 1, and the auxiliary input C2 to the least significant bit which is the output of the OR circuit 430,
The sum S=X1+1+C2 is calculated and outputted to the selection circuit 440 and each bit inversion circuit 450 through the signal line 45. Here, when the carry output from the most significant adder 420 is 1, X1+C2>Y1
, and when it is 0, it indicates X1+C2≦Y1.
Full adder 420 outputs this determination result as determination signal C0 through signal line 37, outputs it through signal line 47 to selection circuit 440, and outputs it through signal line 42 to OR circuit 430.

When the logical sum circuit 430 receives the logical sum signal C1 and the judgment signal C0, it calculates the logical sum of the logical sum signal C1 and the judgment signal C0, and outputs the logical sum signal.
C2 is led to the auxiliary input of the full adder 420 through a signal line 43. As a result, the full adder 42
0 sets the OR signal C2 to 1 when the judgment signal C0 is 1, and sets the OR signal C2 to 1 when the judgment signal C0 is 0.
C2 will be changed to C1, and each will be used as an auxiliary input. Each bit inverter 450 receives the sum S, inverts each bit of the sum S, and outputs the one's complement S of the sum S to the selection circuit 440 through the signal line 46. When the selection circuit 440 receives the sum S, its one's complement, and the judgment signal line C0, it selects the sum S when the judgment signal C0 is 1, and selects the sum S when the judgment signal C0 is 0. The one's complement number is selected and made into a binary number Z1, which is output through the signal line 38. Here, the binary number Z1 becomes Z1=S=X1-Y1 when the judgment signal C0 is 1, and becomes Z1==Y1-X1-C1 when the judgment signal C0 is 0.

Next, another embodiment of the absolute value calculation circuit 300 with auxiliary input will be described in detail with reference to FIG. In FIG. 6, signal line 32 is connected to the input of OR circuit 500. In FIG. Further, the signal line 31 is connected to the full adder 520
and 521. Further, the signal line 30 is connected to each bit inversion circuit 510 and the signal line 50.
is connected to each input of full adders 520 and 521 via. The output of the OR circuit 500 is the signal line 5
1 to the auxiliary input of full adder 520. Further, 1 is given to the auxiliary input of the full adder 521. The output of full adder 520 is connected to the input of selection circuit 540 via signal line 52, each bit inversion circuit 530, and signal line 53. Further, the output of the full adder 521 is sent to the selection circuit 5 via the signal line 54.
Connected to 40 inputs. Furthermore, full adder 520
The determination output of is connected to the signal line 37. This signal line 37 branches into a signal line 55 and a selection circuit 54
Connected to the 0 input. The output of this selection circuit 540 is connected to the signal line 38 .

In a circuit with such a configuration, the binary number
10 and the binary number X1 is input to the full adders 520 and 521 through the signal line 31,
The OR circuit 500 sets the OR signal C1 to 0 only when all bits of the binary number X2 are 0;
If even one bit is 1 among all the bits, the OR signal C1 is set to 1. This OR signal C1 passes through the signal line 51 and becomes an auxiliary input to the lowest level of the full adder 520. When each bit inverting circuit 510 receives the binary number Y1, it inverts each bit of the binary number Y1 and transfers the one's complement 1 of the binary number Y1 to the signal line 50.
It is output to full adders 520 and 521 through.

The full adder 520 inputs the binary number X1 and the binary number
Y1 is input, and the logical sum signal C1 is used as an auxiliary input to the least significant bit to calculate the sum S0=X1+1+C1, and each bit inversion circuit 53 is
Output to 0. Here, when the carry output from the most significant adder 520 is 1, it indicates X1+C1>Y1, and when it is 0, it indicates X1+C1≦Y1. The full adder 520 outputs this judgment result as a judgment signal C0 through the signal line 37, and also outputs the judgment result through the signal line 5.
5 to the selection circuit 540. On the other hand, the full adder 521 receives the binary number X1 and the binary number 1, sets the auxiliary input to the least significant bit as 1, calculates the sum S1=X1+1+1, and outputs it to the selection circuit 540 through the signal line 54. When each bit inversion circuit 530 receives the sum S0, it inverts each bit of the sum S0 and outputs the one's complement 0 of the sum S0 to the signal line 53.
It is output to the selection circuit 540 through.

The selection circuit 540 selects the sum S1 and the complement 0.
and the judgment signal C0 are input, the judgment signal
When C0 is 1, the sum S1 is selected, and when the determination signal C0 is 0, the 1's complement 0 of the sum S0 is selected and output as a binary number Z1 through the signal line 38. Here, when the judgment signal C0 is 1, the binary number Z1 is Z1=
S1=X1-Y1, and when the determination signal C0 is 0, Z1=0=Y1-X1-C1.

In the present invention, the upper M−N of the absolute value |X−Y|
The bit binary number Z1 is determined only by the calculation time of the absolute value calculation circuit with auxiliary input 300, and is not affected by the calculation time of the lower N bits of the binary number Z2. Therefore, in the conventional technology, the lower N bits are determined. Compared to the case where the upper MN bits were determined after the calculation, the overall calculation time can be shortened.
Furthermore, the lower N bits do not require a circuit that functions as an absolute value calculation circuit, and by configuring the lower N bit calculation circuit only with a complement generation circuit and a selection circuit, the overall amount of hardware can be reduced. .

〔Effect of the invention〕

As explained above, when it is known that the lower N bits of one of two M-bit binary inputs are 0, the present invention performs an operation on the lower N bits and the upper M−N bits. The separate configuration has the advantage of shortening calculation time and reducing the amount of hardware.

[Brief explanation of drawings]

1 and 2 are block diagrams of a conventional absolute value calculation circuit. FIG. 3 is a block diagram of an absolute value calculation circuit according to an embodiment of the present invention. FIG. 4 is a diagram showing the bit configuration of the binary numbers X and Y to be operated and the operation output Z. FIG. 5 is a block diagram showing an example of the absolute value calculation circuit with auxiliary input shown in FIG. 3. FIG. 6 is a block diagram showing another example of the absolute value calculation circuit with auxiliary input shown in FIG. 3. 300... Absolute value calculation circuit with auxiliary input, 310...
Complement generation circuit, 320, 440, 540... Selection circuit, 400, 430, 500... OR circuit, 41
0, 450, 510, 530... each bit inversion circuit, 420, 520, 521... full adder.

Claims (1)

[Claims] 1 M-bit binary number X and lower N of M bits
In an absolute value arithmetic circuit that calculates the absolute value Z= | Let the part be a binary number X1,
And the upper M-N bit part of the binary number Y is converted into a binary number.
When Y1, it includes an OR circuit that creates a logical sum C1 of all bits of the binary number X2, and determines the magnitude relationship between the sum of this logical sum C1 and the binary number X1, that is, X1 + C1, and the binary number Y1. However, when X1+C1>Y1, calculate X1-Y1 and output it as the upper M-N bit part _Z1 of the absolute value Z, and output the judgment signal C0=1, and when X1+C1≦Y1, Y1-X1-C1 an absolute value arithmetic circuit with an auxiliary input that calculates and outputs it as the upper M−N bit part _Z1 of the absolute value Z and also outputs a judgment signal C0=0, and calculates the two's complement X3 of the binary number X2. a complement generation circuit that outputs the binary number X2 and the complement X3, and generates the binary number X2 or the complement X3 based on the determination signal C0;
An absolute value calculation circuit comprising: a selection circuit which selects one of the following and outputs it as the lower N bit part _Z2 of the absolute value Z.