JPH05233217A - Three-input rounding addition circuit - Google Patents

Abstract

PURPOSE:To reduce circuit scale by simultaneously executing the addition of three inputs and the rounding of signals corresponding to lower two digits or less by directly generating a value to be carried to the least significant digit of an output from lower digits. CONSTITUTION:A rounding signal generating circuit 1 outputs plural '1's corresponding to carry to the 3rd digit obtained at the time of adding three inputs and that for half-adjusting processing. Two outputs from the circuit 1 are connected to two inputs of a full adder 2 and both the outputs are simultaneously added to the 3rd sum output outputted from a full adder 3 to obtain a rounded three-input added result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a 3-input rounding and adding circuit.

[0002]

2. Description of the Related Art FIG. 2 shows the configuration of a conventional 3-input adder with an integerizing function. In FIG. 2, (X ₁ X ₀ X _-1 X _-2 ),
Three numbers of which (Y ₁ Y ₀ Y _-1 Y _-2 ) and (Z ₁ Z ₀ Z _-1 Z _-2 ) are input, X ₁ , X ₀ , Y ₁ , Y ₀ , Z ₁ and Z ₀ is an integer part, and X _-1 , X _-2 , Y _-1 , Y _-2 , Z _-1 and Z _-2
Is the fractional part. 6 is a carry generator, 7-9, 11, 1
2 is a full adder and 10 and 13 to 16 are half adders. In this three-input adder, the full adder 7 in FIG.
Only the place is added. The carry generator 6 adds only the second decimal place and outputs a carry. The half adder 10 compares the sum output of the full adder 7 and the carry output of the carry generator 6.
Then, the value of the first decimal place is obtained from the sum output. The carry output of the half adder 10, the carry output of the full adder 7, and the sum output of the full adder 8 having the lowest integer part as input are added by the full adder 11 to obtain the lowest integer part. obtain.

Up to this point, addition of three inputs is completed, but the half adder 14 further adds the value of the first decimal place and the sum output of the full adder 11 to obtain a rounded integer part S ₀ . A half adder is required for all bits in the integer part to handle the carry from half adder 14. These are half adders 15 and 16 in FIG.

[0004]

However, in the above-mentioned conventional 3-input adder, the half adder 14,
15 and 16 were required. Therefore, it is difficult to reduce the circuit scale in the device using the 3-input adder.

SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide an adder circuit with a three-input rounding function which has a simple structure and can easily reduce the circuit scale.

[0006]

In the 3-input rounding adder circuit, when the bits below the digit to be rounded are the first bit group and the bits higher than the digit to be rounded are the second bit group, A rounding signal generation circuit having the first bit group as an input and having two outputs is provided, and the relationship between the input and the output of the rounding signal generation circuit is determined by the input, the value of the carry signal and the digit by rounding. A table is formed using the sum of the values of the raising signal, and the rounding process is performed by adding the output of the rounding signal generation circuit and the sum output of the least significant bits of the second bit group.

[0007]

The carry signal at the time of addition and the carry signal at the time of rounding can be calculated by the combination of the input signals.
These two signals must be added to the next higher digit. When the signal input to the rounding signal generation circuit is regarded as a decimal number, the maximum value of the total sum is 2.25 for 2 bits and 1.5 for 1 bit. Therefore, the sum of the carry signal and the carry signal at rounding is 0,
It is either 1 or 2, and two outputs are used to output (0, 0), (0, 1) or (1, 1), respectively.
It is possible to input this 2-bit output and the 1-bit sum output of the least significant bit that is not rounded to a 3-bit input full adder.

[0008]

1 is a block diagram showing the configuration of a 3-input adder circuit according to a first embodiment of the present invention. In Fig. 1 (X ₁
X ₀ X _-1 X _-2 ), (Y ₁ Y ₀ Y _-1 Y _-2 ) and (Z ₁ Z ₀ Z _-1
Z _-2 ) is an input three numbers, X ₁ , X ₀ , Y ₁ , Y ₀ ,
Z ₁ and Z ₀ are integer parts, and X _-1 , X _-2 , Y _-1 ,
Y _-2 , Z _-1 and Z _-2 are the fractional part. In FIG. 1, 1 is a rounding signal generation circuit, 2 and 3 are full addition circuits, 4 and 5 are signal paths, C ₁ , C ₀ , S ₁ and S ₀ are rounding addition outputs, and the rounding signal generation circuit 1 is ( It consists of the truth table in Table 1).

[0009]

[Table 1]

(O ₁ , O ₀ ) in Table 1 is a result of addition and rounding of 2 bits and 3 inputs, and when the value to be added to the least significant part of the integer part is 0, 1 and 2, respectively (0, 0) ), (0, 1)
And (1, 1). In FIG. 1, the signal path 4 is O ₁ and the signal path 5 is O ₀ , which are respectively connected to the two inputs of the full adder 2. The remaining one input is connected to the sum output of the full adder 3 having the lowest integer part as an input.

As described above (Table 1), a correct result can be easily obtained when the result of adding the fractional parts is converted into an integer. At this time, the relationship between the input and the output in (Table 1) can be realized by a combinational circuit. The operation of the integer part is performed in the same manner as a normal adder except for the least significant bit.

As a second embodiment of the present invention, the input data is (X ₁ X ₀ X _-1 ), (Y ₁ Y ₀ Y _-1 ) and (Z ₁ Z ₀ Z _-1 ).
Is shown. In this case, (O ₁ , O ₀ ) is generated by the truth table (Table 2), and if a rounding signal generation circuit is used, X _-2 , Y _-2 and Z _-2 are set to 0 in the configuration of FIG. It is equivalent to the above case, and a 3-input rounding addition circuit can be constructed.

[0013]

[Table 2]

At this time, the relationship between the input and output shown in Table 2 can be realized by a combinational circuit. As described above, according to the present embodiment, in the conventional example shown in FIG.
The adders 14, 15 and 16 which have added the carry from the place are eliminated, and the circuit scale is reduced. Further, the adder 10 for calculating the carry from the second decimal place is unnecessary, which is also advantageous in terms of speed. In fact, the number of transistors required in the configuration of FIG. 2 is 216, but in the configuration of the embodiment shown in FIG. 1, the number of transistors is reduced to 172, and the circuit scale can be reduced. Its practical effect is great as a rounding circuit.

In the present embodiment, the example of rounding the addition result of the decimal part has been described, but the present invention is not limited to converting the decimal part to an integer, but can be used for rounding within the last two digits.

[0016]

As described above, according to the present invention, the addition of 3 inputs and the rounding of the signal within the lower 2 digits are directly generated from the lower digit to the carry to the lowest output digit. By doing so, the circuit scale can be reduced and the practical effect as an addition and rounding circuit for IC and LSI is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a 3-input rounding adder according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional 3-input adder.

[Explanation of symbols]

 1 Rounding signal generation circuit 2 Full adder 3 Full adder 4 Signal path 5 Signal path

Claims (2)

[Claims] 1. A rounding signal generation circuit which has three numbers as inputs and obtains a 2-bit output by receiving the bits of the least significant digits of the three numbers, and the rounding signal generating circuit from the least significant two of the three numbers.
Three-input rounding addition having a first full adder that receives the bit of the first digit as an input and a second full adder that receives the output of the two bits and the sum output of the first full adder circuit. 2. A rounding signal generation circuit which has three numbers as inputs and which receives the least significant digit and the bits from the least significant digit of the three numbers as inputs and produces a 2-bit output, The first 3 bits from the least significant of the two numbers as input
3-input round adder circuit having a full adder of 2), and a second full adder having the 2-bit output and the sum output of the first full adder as inputs.