JPH052469A - Arithmetic circuit for variable-length word-length - Google Patents

Abstract

PURPOSE:To obtain a general purpose operation logic circuit by providing an additional circuit at an exclusive-use operation logic circuit. CONSTITUTION:This circuit is provided with an arithmetic means 12 equipped with the number of the full adder equal to the number of the bit of the prescribed input word-length, an input data converting means 11 to input the input data and the control signal, convert the input data to the data of the prescribed word-length in correspondence to the control signal and supply them to an arithmetic means, and an output data converting means 13 to input an arithmetic result and the control signal by the arithmetic means 12 and convert the arithmetic result to the output data equal to the word-length of the input data. In this configuration, by making preparations for the signal select suitably the input data word-length, the general purpose operation logic circuit is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dedicated arithmetic circuit suitable for LSI, which is a logical arithmetic circuit for performing a two's complement arithmetic operation and is adapted to perform arithmetic operations of plural kinds of data word lengths.

[0002]

2. Description of the Related Art In recent years, due to advances in LSI technology, there are cases in which dedicated LSIs are created for various purposes to reduce the size and speed of hardware. Especially in the case of communication, there is a demand for a high-speed logic circuit because real-time processing is required. For example, in a filter process or the like which is conventionally configured by individual circuit elements and performs analog signal processing, digital signal processing is performed by using an A / D converter, a D / A converter, and a dedicated logic circuit. Achieved miniaturization and high speed. In this processing, first, an analog input signal is converted into a digital signal by an A / D converter, and digital data is processed by a dedicated arithmetic logic circuit to perform filtering processing.
Finally, the D / A converter converts the analog signal to form an input / output system equivalent to the conventional one. In such a digital signal processing, as a device development method, there is a method for designing a dedicated arithmetic logic circuit to optimize hardware and a general-purpose arithmetic logic circuit as described in the following document. There has been a method of implementing a required function in software by using hardware, for example, a digital signal processor (DSP). Reference: Digital Signal Processing, Chapter 7, Hardware Technology,
Editor: Corporate Incorporated Association, The Institute of Electronics and Communication Engineers, Sales Office: Corona (published on November 10, 1975, the first edition).

[0003]

However, the former method has a problem that it takes time to develop and design a dedicated arithmetic logic circuit, and the latter method requires time to develop and design software. Depending on the scale of software, there was a problem that the real time processing could not be maintained. Also, when deciding the data word length to achieve the required performance, it is necessary to comprehensively consider each condition such as internal calculation accuracy, processing result accuracy, processing time, etc. There was a problem that it required a long word length evaluation period. The present invention has been made in order to solve the problems of the conventional circuit, and an object thereof is to provide a general-purpose arithmetic logic circuit by providing an additional circuit in a dedicated arithmetic logic circuit. To do.

[0004]

SUMMARY OF THE INVENTION The present invention comprises arithmetic means having a number of full adders equal to the number of bits of a predetermined input word length. Further, the input data and the control signal are input to the control signal. Corresponding to the input data converting means for converting the input data into data of a predetermined word length and supplying the data to the calculating means, and further, the calculation result by the calculating means and the control signal are inputted,
Output data conversion means for converting the operation result into output data having the same word length as the input data in accordance with the control signal is provided.

[0005]

According to the present invention, in a device for performing digital signal processing, by providing a signal for appropriately selecting the input data word length, it is possible to provide a circuit which has a degree of freedom in designing an arithmetic logic circuit, Therefore, it is possible to shorten the period of hardware design of a device that performs digital signal processing and improve the efficiency of use of the LSI.

[0006]

Embodiments will be described in detail below with reference to the drawings. Figure 1
FIG. 3 is a block diagram for explaining an outline of an embodiment of the present invention. In FIG. 1, the input data conversion means 11 is
It is a converter for converting the word length of the input data, and the calculating means 1
Reference numeral 2 is a computing unit for computing the output data of the transforming unit 11, and output data transforming unit 13 is a converter for transforming the word length of the output data of the computing unit 12. The control signal generator 14 is a generator that sends a control signal for controlling the word length conversion to the conversion means 11 and 12. The block of FIG. 1 is, for example, an arithmetic circuit included in a large-scale logic circuit such as a digital signal processor.

The outline of the operation of FIG. 1 is that, for example, 8-bit input data is input to the conversion means 11, converted into 16 bits, output from the conversion means 11 and input to the calculation means 12. The arithmetic means 12 performs arithmetic processing with a word length of 16 bits, and if the result exceeds 16 bits, a carry of 1 bit is generated. Therefore, the internal operation word length of the operation means 12 is 17 bits. The lower 16 bits of the output of the arithmetic means 12 are selected. The 16-bit output data is input to the conversion unit 13, and the word length is converted to the same 8-bit as the input data of the conversion unit 11 and output. That is,
The input data conversion means 11 and the output data conversion means 13 perform word length conversion between the input / output data and the data of a predetermined number of bits, and the calculation means 12 calculates the data of a predetermined number of bits to develop an LSI. It is possible to improve efficiency.

Next, the embodiment of the present invention shown in FIG. 2 will be described. In FIG. 2, the input data conversion circuit 11
0 is four 2-input AND circuits 111, 112, 11
3, 114 and four 2-input selection circuits 115, 116,
117 and 118, the arithmetic circuit 120 has four
An adder 121 that performs addition processing between bits and four adders 122, 123, and 12 that perform addition processing between 1 bits
4, 125, and an output data conversion circuit 130.
Is a four-input AND circuit 131, 132, 133,
It is composed of 134. In the operation block of FIG. 2, one of the two data to be added is data A, the other is data B, and the addition result is data C. Further, when these data are 8 bits, data A is sequentially output from the lower bit.
0, A1, A2, ... A7 (same for data B and C).

The adder 121 stores the lower 4 bits (A0 to A3) of the data A and the lower 4 bits (B0 to B) of the data B.
3) is input. Then, the addition result is output from the adder 121 as data C0, C1, C2, and C3. Further, the data A4 is at the first input end of the AND circuit 111, and the data B4 is at the first input end of the selection circuit 115.
The data A5 is input to the first input end of the AND circuit 112, the data B5 is input to the first input end of the selection circuit 116, and the data A6 is input.
However, at the first input terminal of the AND circuit 113, the data B6 is
The data A7 is input to the first input terminal of the selection circuit 117, and the data B7 is input to the first input terminal of the AND circuit 114.
It is input to the first input end of 18. And the selection circuit 11
A high level corresponding to fixed data “1” is supplied to the second input terminals of 5, 116, 117 and 118.

The AND circuit 111 and the selection circuit 11
5 and 5 are input to the adder 122, and the output of the adder 122 is connected to the first input of the AND circuit 131. Similarly, the outputs of the AND circuit 112 and the selection circuit 116 are
It is input to the adder 123, and the output of the adder 123 is connected to the first input of the AND circuit 132. AND circuit 11
3 and the selection circuit 117 are input to the adder 124, and the output of the adder 124 is connected to the first input of the AND circuit 133. The outputs of the AND circuit 114 and the selection circuit 118 are input to the adder 125, and the output of the adder 125 is connected to the first input of the AND circuit 134. Each of the AND circuits 131, 132, 133, 134 outputs addition result data C4, C5, C6, C7.

The carry generated as a result of the operation of the adder 121 is input to the adder 122. Similarly, adder 1
The carry generated as a result of the calculation of 22 is input to the adder 123, the carry generated as a result of the calculation of the adder 123 is input to the adder 124, and the carry generated as a result of the calculation of the adder 124 is added to the adder. Enter in 125. The carry generated as a result of the arithmetic operation of the adder 125 is output to the outside of the arithmetic unit 120. Further, the first control signal output from the control signal generating means 14 is input to the input terminals of the AND circuits 111 and 131 and the control terminal of the selection circuit 122. Similarly, the second control signal output from the control signal generator 14 is input to the input terminals of the AND circuits 112 and 132 and the control terminal of the selection circuit 123. The third control signal output from the control signal generating means 14 is input to the input terminals of the AND circuits 113 and 133 and the control terminal of the selection circuit 124. The fourth control signal output from the control signal generating means 14 is input to the input terminals of the AND circuits 114 and 134 and the control terminal of the selection circuit 125.

How the above circuits relate to the present invention will be described. As an operation example, FIG. 1 shows the addition processing when the input data length is 4 bits and when it is 6 bits.
This will be described with reference to FIG. The relationship between the control signal output from the control signal generating means 14 and the input data length prior to the addition processing is as follows.

[0013]

[Table 1]

First, in the case of 4 bits, the control signal generating means 14 of FIG.
To the input data conversion circuit 110 from the generating means 14.
And the first to fourth control signals are input to the output data conversion circuit 130. Since "0" is input as control data to the control terminals of the input data conversion circuit 110 and the output data conversion circuit 130, each AND circuit is closed and the final outputs C4 to C7 also output a fixed value of zero. To do. Next, two 4-bit data A0 to A3 and B0 to be added are added.
To B3 are input to the arithmetic circuit 120 via the input data conversion circuit 110. At this time, the upper 4 bits of the input data are all set to 0 and input to the input data conversion circuit 110, or the data are supplied only to the lower 4 bits.

The adder 121 adds the two input 4-bit data and outputs the addition result as C0 to C3 via the output data conversion circuit 130. The outputs of C4 to C7 are all "0" because the AND circuits 131 to 134 are closed. On the other hand, if a carry occurs in the addition of the adder 121, the carry is input to the next adder 122. Adder 1
Since the data of 2 inputs is "0" in 22, the addition of this "0" and the carry input of "1" is performed, and as a result, a carry output is generated and the carry is also carried to the next adder 123. There is input. The addition processing of the adder 123 is similar to that of the adder 122. Further, a carry output is generated, the carry is sequentially propagated to the adjacent adders 124 and 125, and finally output from the arithmetic circuit 120 to the outside. ..

When the data length is 6 bits, first, the precision switching control signal is input to the control signal generating means 14, and the generating means 14 generates the first to fourth control signals. At this time, the first and second control signals are "1", and the third and fourth control signals are
Control signal becomes "0". Therefore, in the arithmetic circuit 120, the 6-bit addition process is performed using the adders 121, 122, and 123, and C0 to C5 are obtained as outputs. Further, when carry occurs as in the case of the above 4 bits, it can be propagated through the adder and output from the arithmetic circuit 120.

[0017]

As described above, in the embodiment shown in FIG. 2, the addition is performed in which the word length of the input data is made variable by using the first to fourth control signals between 4 bits and 8 bits. Since processing becomes possible, the effect of increasing the usage rate of the LSI can be expected.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an outline of an embodiment of the present invention.

FIG. 2 is a block diagram showing details of an embodiment of the present invention.

[Explanation of symbols]

 11 Input Data Conversion Means 12 Arithmetic Means 13 Output Data Conversion Means 14 Control Signal Generation Unit 110 Input Data Conversion Circuits 111-114 2-Input AND Circuits 115-118 2-Input Selection Circuits 120 Arithmetic Circuits 121-125 Adders 130 Data Conversion Circuit 131-135 2-input AND circuit

Claims (1)

Claim: What is claimed is: 1. An arithmetic means having a number of full adders equal to the number of bits of a predetermined input word length, input data and a control signal are input, and corresponding to the control signal. Input data conversion means for converting the input data into data of the word length and supplying it to the operation means, an operation result by the operation means and the control signal are input, and the operation is performed corresponding to the control signal. An arithmetic circuit for variable length word length, comprising: output data conversion means for converting a result into output data having the same word length as input data.