JPS60254373A - Arithmetic unit for sum of product - Google Patents

Abstract

PURPOSE:To reduce only one adder as compared to an ordinary unit and to shorten an arithmetic processing time by adding the outputs of an accumulator by a Wallace tree adder together with the addition of partial products. CONSTITUTION:Input data to be the 1st data and factor data to be the 2nd data are supplied to terminals 1a, 1b respectively. A partial product formation circuit 2 forms the partial products of respective data on the basis of the Booth's method of 2 bits and the Wallace tree adder 7 adds the outputs of the accumulator 6 simultaneously with the addition of the partial products. The output of the Wallace tree adder 7 is supplied to a carry foreseeing adder 4 and its outputs are accumulated and outputted in/from the accumulator 6 as the calculated result for the sum of products. Said operation is sequentially repeated and the calculated result for the sum of products of all data is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a high-speed product-sum operation device used in digital filters and the like.

[Prior art and its problems]

For example, in a digital filter, the 20M modulated binary input data is multiplied by the filter coefficient t [several times, and the product-sum operation result is output by adding all the results. However, in application fields where the sampling frequency is high, The performance of digital filters is influenced by the speed of arithmetic processing, and there is a desire to shorten the arithmetic processing time.

FIG. 2 shows an example of a product-sum calculation device generally used in the above-mentioned digital filters and the like. In the same figure, a multiplier 1 includes a partial product generation circuit 2, a Wallac
e tree) consists of an adder 3 and a carry look-ahead adder 4, and its entry terminal 1a.

The long sword data and coefficient data are sequentially supplied to 1b. From both data, 2-bit Boo
Partial products are generated by the method of (th), and each partial product is added by the Wallace tree adder 5. The output of the Wallace tree adder 5 is supplied to a carry look-ahead adder 4, from which the result of multiplication of the input data and coefficient data is obtained and supplied to the adder 5. The adder 5 adds the new multiplication result to the accumulator 6, and this becomes the product-sum operation result and is output from the accumulator 6.

In the above configuration, the calculation processing involves partial product generation (Wallace)
In addition to IJ-addition and carry look-ahead addition, addition by the adder 5 is performed, which requires a long calculation time and is complicated in structure.

〔the purpose〕

The present invention aims at shortening the calculation processing time and simplifying the configuration by simultaneously adding the accumulator output and the partial product in the Wallace tree adder.

〔Example〕

In FIG. 1, terminals 1 a and 1 bK are supplied with input data, which is first data, and coefficient data, which is second data, respectively.
Partial products of each data are generated according to Bitt's Booth method. This is a feature of the present invention, in which the output of the accumulator 6 is simultaneously added together with the above partial products in the Wallace tree adder 7. This eliminates the need for the adder 5 shown in FIG. 2, making it possible to simplify the configuration and shorten the arithmetic processing time.

The output of the Wallace tree adder 7 is the carry look-ahead adder 4.
is supplied to the accumulator 6, and its output becomes the product-sum operation result.
is stored and output. The above operation is repeated one after another, and the product-sum operation results for all data are output.

By the way, since the Wallace tree adder 7 also adds the output of the accumulator 6, the number of inputs increases by one person depending on the bit, but the number of stages of the full adder does not increase significantly just by increasing the number of inputs by one person. .

Incidentally, the number of inputs n of the Wallace tree adder and the number of stages of full adders required for this are as shown in Figure 39. The number of stages of the adder is at most one stage.

Note that the present invention is not limited to digital filters, but can be applied to product-sum calculation devices used in various digital signal processing.

Further, in the above example, a case was described in which partial products are generated using a 2-bit Booth method, but the same applies to a case where a 5-bit or more Booth method is used.

〔effect〕

According to the present invention, since the output of the accumulator is also added together with the addition of partial products by the Wallace tree adder,
Compared to the conventional method, the number of adders can be reduced by one, the configuration is simplified, and the calculation processing time can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a conventional product-sum calculation device, and FIG.
The figure is an explanatory diagram showing the number of inputs of a Wallace tree adder and the number of stages of required full adders. 2...Partial product generation circuit 4...Carry key, adder 6...Accumulator 7...Wallet tree adder Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] a partial product generation circuit that generates a partial product of first data and second data according to Booth's method; an accumulator; an output of the accumulator; and an output of the partial product generation circuit; Ill'a
llace tree) adder, and a carry look-ahead adder that receives the output of this Wallace tree adder. Features a product-sum calculation device.