JPS5938849A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To execute a calculation at a high speed, by inputting a halfway part of multiplication in a parallel multiplier to the first and the second registers which are separately provided freshly by an N-bit portion, and adding its output and the previous calculation result by a three-input adder. CONSTITUTION:A multiplicand A and a multiplier B are inputted to 16-bit registers 1, 2, the partial product is derived by a parallel multiplying circuit 3, addition is executed in several stages so that three inputs become two inputs by an adder of each digit, and outputs whose final each digit (final digit is 32) becomes two inputs are inputted to 32-bit registers 9, 10 separately by 32 pieces each. Subsequently, these outputs and a calculation result C before a 32-bit register 8 which stores the previous calculation results are inputted to a three- input adder 11, are added, and (AXB+C) is derived, is inputted to the 32-bit register 8 and is stored.

Description

[Detailed description of the invention] (al Technical field of the invention Is r3A (AXB + previous calculation result)?
:Relates to circuits and relates to arithmetic circuits that can perform high-speed calculations.

(bl Problems with the Prior Art) FIG. 1 is a block diagram of the arithmetic circuit of the conventional CAXB 10th calculation result, and FIG. 2 is a time chart of the operation in the case of FIG. 1.

In the figure, 1 and 2 are 16-bit registers, 3 is a parallel multiplication circuit,
4 and 7 are adders, 5 and 8 are 32-bit registers, 6 is a parallel multiplier, '0+'l+F is shown in purple, and t is an operation cycle time.

Let the previous calculation result The (32 bits) be the multiplicand v
A, (x6 bits), multiplier? B (16 bits) and (
AXB+C) operation? When using the arithmetic circuit shown in Figure 1, A+B? Input to 16-bit register 1.2, calculate partial product in parallel multiplier circuit 3, and add each digit? , in an adder, add several stages so that 3 manual inputs become 2 outputs, and when adding manually to the adder 4 at the final stage, each digit is input as 2 outputs fj:. These two output signals for each case are calculated separately by the 'k7Jll calculator 4, and inputted to the Shinkin Bank 32-pit counter register 5 of the AXI 3 as a value indicated by 1 bit for each digit. This Δ, 32 of XB
The value stored in the bit register 5 is input to the full adder 7, and the calculation result C before the 32-bit register 8 which stores all the previous calculation results? 7] 11 Calculate manually on calculator 7 (calculate Ayl's name), input it into 32-bit register 8, and store it in memory.

Next, instead of A and H, input the next multiplicand A11 multiplier B and 2t6 into bit registers 1 and 2, perform the same multiplication as above to obtain A+XF'+ffi, store it in 32-bit register 5, and store the previous operation result (AXEl ) is calculated by the chord adder 7 and stored in the 32-bit register 8.

The above steps are repeated one after another.

The time 'tl from when one result is obtained to when the next result force 1 is produced will be explained with reference to FIG. The time surrounded by a solid line in FIG. 2 indicates the time 7 that each register stores, and each register stores data for an operation cycle time t. Is the time surrounded by dotted lines the calculation time of parallel multiplier 6 and the calculation time of adder 7? It shows. After inputting the multiplier B to the multiplicand in register 1511.2, from time t0, the parallel multiplier 6 inputs A, X
The time ht, -to=t until the multiplication result of B is output is the sum of the time required in the parallel multiplier circuit 3 and the time required in the adder 4, which is long.

Therefore, this time t, -4o=i determines the calculation cycle time.

Although it is shorter by the time (t,) required for the calculation circuit 3, the calculation cycle time t is determined based on the above conditions, so the time is t.

The waiting time is 2t until the operation of AXB10 is completed and the result is input to the money register 8, which has the disadvantage of increasing the operation time.

(C) Object of the Invention The object of the present invention is to provide an arithmetic circuit which can overcome the above-mentioned disadvantages of total heat and perform high-speed calculations.

(d) Structure of the Invention In order to achieve all of the above objects, the present invention has the following objectives: (AxB + previous operation result) 7 In an arithmetic circuit to obtain, the multiplication result of a V-connected B parallel multiplier is used to transfer each bit to an N-bit register. value? Two outputs to the adder to obtain N bits are newly provided T: 1st. The output is input to the second register, and the output of the third register, which stores all the results of the previous operation, is input to the newly installed three-man adder, and the result is added? It is assumed that the output to the third register is 11-%.

3- (el　Disastrous precedent for invention) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram of an arithmetic circuit according to an embodiment of the present invention, and FIG.
The figure is a time chart of the operation in the case of FIG.

Components in the figure that have the same functions as those in the vX1 diagram are indicated by the same symbols.

9.10 is a 32-bit register, 11 is a 3-person adder,
'O+'l'? ``'' is time, t' is the calculation cycle time O. As in Figure 1, the previous calculation result ?C, the multiplicand is person, the multiplier ?B, and the operation of (AXB + C)? Add several stages to make 3 manual outputs or 2 outputs, and input 32 outputs t1 separately into the 32-bit register 9.10, where each final digit (the final digit is 32) has 2 outputs.
These outputs are input to the 32-bit register 8 which stores all the previous calculation results, and the previous calculation result C'e-3 is input to the manual calculator 114-, and added (AXB 〇)'. The result is input into the 32-bit register 8 and stored. After that, instead of A and B, input the multiplicand A3 multiplier B to the 2t6 bit register 1.2, perform all multiplications as above, and output 2 outputs for each digit at the end, 32 bits each for 32 bits separately. register 9,
The previous calculation result (AX
B+C)? 3 Input to the human power adder 11 and add g (A,
XB, -+AXB-1-C)IU" 132-bit register 8 and stored.

The above steps are repeated one after another.

In this case, the operations of the force n calculator 4 and the adder 7 shown in @1 are simultaneously performed in parallel by the adder 11.

Time t from one result to the next result - 4th
This will be explained with a diagram. The time surrounded by the solid line in FIG. 4 indicates the time 7 during which each register stores data, and each register stores data during the calculation cycle time t1.

Is the time surrounded by dotted lines the calculation time of the parallel multiplier circuit 3 and the calculation time of the adder 11? It shows. Register 1.2
Multiplicand A multiplier B inputs -4 at time t7, and the parallel multiplier circuit 3 calculates the intermediate result of multiplication of A'='B (calculations until it is input to the knife 4 in Fig. 1). Jfit,
With '-t0=t', the calculation cycle time is determined at this time. This time is shorter than the case of FIG. 1 by the calculation time of addition: 4. The time required for the operation of the adder 11 is 7 in Fig. 1.
The time required for the III calculators 4 and 7 is almost the same, but it is slightly shorter than the computation time for the parallel multiplier IJ@3. However, since the calculation cycle time t' is determined based on the above conditions, the time t,
' is the waiting time.The calculation of machine AxB-1-C is completed and this result? The time required to input the data to the register 8 is 2(I, which is twice the calculation time of the adder 4 in FIG. 1 than in the case of FIG. 1).

The above is explained in terms of multiplicand and multiplier of 16 bits, and π is this UN/
It may be 2 bits. In this case, each 32-bit register becomes an N-bit register.

g) Effect of invention As explained in detail above, according to non-invention, there are two effects
．． Since the calculations are performed simultaneously in parallel using wx adders, there is an effect that the calculation can be performed at high speed.

[Brief explanation of drawings]

7- Fig. 1 is a block diagram of a conventional arithmetic circuit (person x B + previous calculation result), Fig. 2 is the operation time of 1,000 yards in the case of Fig. 1, and Fig. 3 is an embodiment of the present invention. FIG. 4 is a block diagram of the arithmetic circuit (results of the tenth AXB operation) and an operation time chart in the case of FIG. 3. In the figure, 1.2 is a 16 pit register, 3 is a parallel multiplier circuit,
4, 7.11 are adders, 5, 8, 9.10 are 32-bit registers, and 6 is a parallel multiplier? show. r---T Straw 2 Figure 43 Figure 4

Claims (1)

[Claims] (, A, X B + previous operation result), the multiplication result of A,
The first output is newly provided with N bits separately. Input to the second register, its output, and the result of the previous operation? What is the memorized output of the third register? The newly installed arithmetic circuit requires 2I\1 to input the input to the 3-way adder and output all the addition results to the third register.