JPS63164640A - Cosine transformation device - Google Patents

Abstract

PURPOSE:To attain high-speed cosine transformation by using a real number multiplier applying N/2 time real number multiplication and a butterfly adder in common with inverse cosine transformation device to use it easily as an inverse cosine transformation device through switching and applying the number of times of real number multiplication of N/2log2N. CONSTITUTION:After an input value is converted by butterfly adder 24, a part is multiplied to a real number by a multiplier 27. The result is transformed by a butterfly adder 25, a part is multiplied to the real number by a real number multiplied 28 and added by an adder 30. Moreover, data is processed similarly by a buffer fly adder 26, a real number multiplied 29 and an adder 31 similarly, multiplied by a multiplier 32 and then outputted. Since the division of 2's power is processed by a multiplier 32, 1/4 and 1/2 time are realized by one-and two-bit shift processing. In this case, the butterfly adders 24, 25, 26 and the real number multipliers 27, 28, 29, 32 are of the same constitution as those of a conventional inverse cosine transformation device. Thus, in using this transformation device, many circuit are used in common for the inverse cosine transformation device.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a cosine transform device in digital signal processing.

[Prior art] Sine transformation is known to have a great effect on image signal compression, etc., and N-dimensional high-speed cosine transformation and N
As a dimensional fast inverse cosine transform, we currently have a total of 2 llo
A method is known that can be performed using g2 N real number multiplications. Figures 3 and 4 are examples of signal diagrams for 8-dimensional cosine transformation and 8-dimensional inverse cosine transformation using the method of Moriyo et al. Theory A, 1ea
-A.

PP, 173-180 (1985)). However, it is assumed that the cosine transform pair is defined by the following equation.

(!Yu); Original data (';): Cosine transformed data In FIG. 3, after the eight input values input from input part 1 are transformed by adder 2 and real multiplier 3, It passes through a butterfly adder 4, is converted by a real number multiplier 6 and an adder 6, passes through a butterfly adder 7, and is further converted by a real number multiplier 8. The signal is output to an output section 11 via a butterfly adder 9 and a multiplier 10.

In FIG. 4, eight pieces of data input from the input section 12 are added by a butterfly adder 13,
The multiplier 14 performs real number multiplication on two pieces of data, which is the number of H outputs, and the adder 16 performs addition on six pieces of data among the outputs. A real number multiplier 16 performs real number multiplication on the data, an adder 17 performs addition on 7 of the output data, and a real number multiplier 18 performs real number multiplication on 4 of the output data. perform the multiplication,
The adder 19 adds data to four of the outputs, the butterfly adder 2o adds data to four of the outputs, and the butterfly adder 2o adds data to six of the outputs. As a result of real number multiplication performed by the real number multiplier 21, a cosine-transformed output value is outputted from the output portion 22. The total number of multiplications is 13, but if we do not count division by a power of 2 as multiplication, the total number is 1.
The number of multiplications is twice, which matches the number of multiplications required for the inverse cosine transformation shown in FIG. Furthermore, the configurations of the devices are largely different between the inverse cosine transform device shown in FIG. 3 and the cosine transform device shown in FIG.

Problems to be Solved by the Invention In the above algorithm, the number of multiplications of real numbers is 3ANltOq2N times for N-dimensional cosine transform, but there are few parts that can be shared between the cosine transform and inverse cosine transform circuits, and the hardware scale is low. It has the disadvantage of increasing

Means for Solving the Problems The present invention performs N-dimensional cosine transformation on N data using a butterfly adder, a subsequent real multiplier that performs N real number multiplications, and a part of the multiplication results. This type of device can be used as a set of devices including an adder that adds data before multiplication.
In a cosine transform device configured by cascading og2N integer multipliers that perform division by a constant of a power of 2, the butterfly adder and the real number multiplier that performs i real number multiplications are combined into an inverse cosine transform device. This is a cosine transform device that can be easily switched and used as an inverse cosine transform device by being used in common with the inverse cosine transform device.

Operation According to the present invention, the main circuits for cosine transformation and inverse cosine transformation can be shared by the above-described configuration, so that both can be switched and used in one device, thereby greatly simplifying the hardware. Furthermore, in fact, the number of multiplications of N number is 71og2N times, which is less than the number of multiplications of currently known high-speed cosine transform, and high-speed cosine transform is possible.

Embodiment FIG. 1 shows a signal diagram of an embodiment of the present invention in the eight-dimensional case. 23 in Fig. 1 is the input part of this device, 2
4-26 are adders for butterfly addition, 27-29
is a real number multiplier for real number multiplication, 30.31 is an adder for other than butterfly addition, 32 is a real number multiplier for division by a power of 2, and 33 is the output part of this device. .

In the device shown in FIG.
After the input values are converted by the butterfly adder 2, a part is multiplied by a real number by the multiplier 27. Next, after being converted by the butterfly adder 26, a part is multiplied by a real number by the real number multiplier 28, and addition is performed by the adder 3o. Furthermore, after being converted by the third stage butterfly adder 26, the real number multiplier 2
9 is multiplied by a real number, and a portion is added by an adder 31.
It is multiplied by a multiplier 32 and output to an output section 33. Since the multiplier 32 performs division by a power of 2, K times and % times can be realized by 2 pits and 1 bit shift, respectively, so calculations are easy.

Butterfly adders 24 and 25 in FIG.

26 are the butterfly adders 4°7.9 in FIG.
is the same as the real multiplier 27゜28.29,
32 are real multipliers 3, 5, 8, and 10 in FIG. 3, respectively.
It has the same configuration as . Therefore, by using the cosine transform device of the present invention, many circuits can be shared with the inverse cosine transform device.

FIG. 2 shows a block diagram of a device in which the cosine transform device of the present invention and the conventional cosine transform device are combined in the case of eight dimensions so that both transforms can be performed by one device by switching appropriately. In the figure, D represents a delay device for one data processing time, ■ represents an adder, and ■ represents a multiplier. 34 is an input terminal to which signals are input in series. 36 is an arithmetic unit for inverse cosine transformation, which performs the processing of the adder 2 in FIG. 36 is a real number multiplier for inverse cosine transformation, which performs the processing of the real number multiplier 36 in FIG. 37 is a butterfly adder, which is similar to adder 24 in FIG.
and performs the processing of the adder 4 in FIG. 38 is an arithmetic unit for inverse cosine transformation, which performs the processing of the adder 6 in FIG. 39 is a real number multiplier, which is the same as the real number multiplier 27 in FIG.
and performs the processing of the multiplier 6 in FIG. A butterfly adder 40 performs the processing of the adder 26 in FIG. 1 and the adder 7 in FIG. 3. 41 is an arithmetic unit for cosine transformation, which performs the processing of the adder 30 in FIG. A real number multiplier 42 performs the processing of the real number multiplier 28 in FIG. 1 and the real number multiplier 8 in FIG. 3. 43 is a butterfly adder;
The processes of adder 26 in FIG. 1 and adder 9 in FIG. 3 are performed. 44 is an arithmetic unit for cosine transformation, which performs the processing of the adder 31 in FIG. 46 is a real number multiplier for cosine transformation, which performs the processing of the real number multiplier 29 in FIG.

A multiplier 46 performs the processing of the multiplier 32 in FIG. 1 and the multiplier 10 in FIG. 3. 47 is an output terminal, from which the converted signal is output.

In FIG. 2, the number of multipliers is six. However, since the multiplier 46 performs division by a power of 2, it can be realized by a simple bit shift. Furthermore, the real number multiplier 36 is not used in cosine transformation, and the real number multiplier 46 is not used in inverse cosine transformation.

Therefore, the real number multiplier 36 and the real number multiplier 45 can be used by switching one real number multiplier, and a total of 3 real number multipliers can be used.
The circuit shown in FIG. 2 can be constructed using real number multipliers.

Although the above explanation has been about 8-dimensional cosine transformation, it is generally possible to easily derive exactly the same thing in the N-dimensional case as well. In this case, the number of real multipliers and the number of butterfly adders are both log2 N.

As described above, according to this embodiment, by skillfully combining the transformation pairs of cosine transformation and inverse cosine transformation,
It is possible to reduce the number of elements required for the circuit configuration.

Furthermore, each multiplier performs real number multiplication only on the number of H input data, and by using delay elements, etc., it is possible to make the time required for real number multiplication approximately twice the average conversion time. This also has the advantage that the configuration of the real multiplier is easy.

Also, by using the fact that each multiplier performs real number multiplication only on the number of H input data, the number of multipliers can be reduced to flog
It is possible to configure two cosine transform devices with 2N units. In this case, it is possible to configure two cosine transform devices that can be switched and used as inverse cosine transform devices, or to configure one dedicated cosine transform device and one inverse cosine transform device. Even when used as a dedicated device for a cosine transform device, the present invention is effective because the number of real number multiplications is equal to or less than that of other currently known high-speed cosine transforms, and the structure is simple.

In place of the real multiplier in FIG. 2, a memory may be used in which a combination pattern of a multiplier and a multiplicand is used as an address and the product is output.

Although the above explanation has been about 8-dimensional cosine transformation, it is generally possible to easily derive exactly the same thing in the N-dimensional case as well. In this case, the number of real multipliers and the number of butterfly adders are both llog2N.

As described in detail, according to the present invention, cosine transform can be performed with the minimum number of calculations known at present, and a large number of elements can be shared for cosine transform and inverse cosine transform when creating a device. The practical effects are great.

Furthermore, in the cosine transform of the present invention, since the number of real multiplications per real multiplier is % of the number of input data, two cosine transform devices can be incorporated into one device to reduce the total number of necessary real multipliers to 3. By doing so, it is possible to substantially reduce the number of real multipliers required for one cosine transformation, which has a great practical effect.

Furthermore, in the cosine transform of the present invention, since the number of multiplications for each real multiplier is % of the number of input data, the calculation time required for multiplication is reduced to about twice the average conversion time by using a delay element. It is possible to do so, and it is of great significance.

Further, even when the present invention is configured as a dedicated cosine transform device, the number of required multiplications is equal to or less than that of other currently known high-speed cosine transforms, and the structure is simple. It can also be used as a method, and its significance is great.

[Brief explanation of the drawing]

Fig. 1 is a signal line diagram of an embodiment of the present invention in the case of 8 dimensions; Fig. 2 is a block diagram of the new cosine transform device in the case of 8 dimensions; Fig. 2 shows the combination of the present invention with a conventional inverse cosine transform device; FIG. 3 is a signal line diagram of a conventional inverse cosine transform device in the case of eight dimensions, and FIG. 4 is a signal line diagram of the conventional cosine transform device in the case of eight dimensions. 24.25.26...Butterfly adder, 27
゜28.29... Real number multiplier, 30, 31...
... Adder, 32... Multiplier for reciprocal of power of 2, 36°37... Real multiplier for inverse cosine transformation, 37°40.43... ...Butterfly adder, 36... Real number multiplier for inverse cosine transformation, 3
9.42... Real number multiplier, 41, 44...
. . . Arithmetic device for cosine transformation, 46 . . . Real number multiplier for cosine transformation, 46 . . . Multiplier for reciprocal of power of 2.

Claims (4)

[Claims] (1) For N (N=2^ν; ν is a natural number) data, N-dimensional cosine transformation is performed using a butterfly adder, followed by a real number multiplier that performs N/2 real number multiplications, and its multiplication results. A cosine is constructed by connecting a set of adders that add part of the pre-multiplication data to , cascade-connecting ν of the devices, and then connecting an integer multiplier that divides by a constant of a power of 2. In the converter, a butterfly adder and an N/
A cosine transform device that can be easily switched and used as an inverse cosine transform device by sharing a real number multiplier that performs two real number multiplications with the inverse cosine transform device. (2) In real number multipliers, by utilizing the fact that the number of real number multiplications per multiplier is 1/2 of the total number of data, two cosine transform devices can be incorporated into one device to reduce the number of real number multipliers required. 2. The cosine transform device according to claim 1, wherein ν is a total of ν. (3) Using the fact that the number of real number multiplications per multiplier is 1/2 of the total number of data in each real number multiplier, the multiplication time is
The cosine transformation apparatus according to claim 1, characterized in that the hardware configuration of the real multiplier is simplified by performing the processing within twice the average processing time per stage of one data. (4) A patent claim characterized in that, instead of using a real multiplier, real number multiplication is performed by using the number of combination patterns of a multiplier and a multiplicand as an address, and accessing a memory in which a product is stored at a location indicated by this address. The cosine transform device according to the first, second, or third range.