JPH0447454A - Method and device for discrete fourier transformation or cosine transformation of digital data - Google Patents

Abstract

PURPOSE:To reduce the number of multipliers and to design a more compact VLSI by introducing Wallis transformation having a specific element in the operation process of a first stage. CONSTITUTION:In the operation method of discrete Fourier transformation or cosine transform of N=2<n> digital data (n is a positive integer), a product [Z]=[W] [x] between +1 and input data 1 of a Wallis transformation matrix [W] 2 having elements of only -1 is calculated by only addition and subtraction in an operation process 3 of the first stage. In an operation process 5 of a second stage, the product between a discrete Fourier transformation matrix [F] and an inverse Wallis transformation matrix [W-<1>] (=[W]) or between a discrete cosine transformation matrix [C] and the inverse Wallis transformation matrix [W-<1>] is preliminarily calculated in a process 4, and matrix operation of a product [yf] between the output [Z] of the operation process 3 and a product [Af] or a product [yc] between the output [Z] and [Ac] is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a discrete Fourier or cosine transform method and apparatus.

[Prior art]

Conventionally, techniques in this type of field include Mikio Hino, "Spectrum Analysis, Chapter 12, Section 3, Breakfast Shoten, 1977," W.
H, Chen, etal, I
EEE, h-transaction on communication (I)
transaction on communication
on).

Vol. C0M-25, NO, 9, 9, 1977.

Vector [X)""(X,,XI,Xt,"'-,!,
-1) of N data represented by one-dimensional discrete Fourier transform Cyr) and discrete cosine transform [yJ are matrices (F) and [C], respectively, (y=)=(F][x) ( y, )=[C)(x) However, ;f,=exp (2πi jk/N)'C4h
=c(j)cos (2π(2+1)jπ/2N);
C(j)”1/, /2 for j=o.

C(j)=1 for j=1.2. -1N-1)
It can be expressed as

Conventionally, the above-mentioned discrete Fourier transform [y,] or discrete cosine transform [y. ] Calculation methods include a direct matrix calculation method and a high-speed calculation method disclosed in the above-mentioned literature. The former directly calculates the product of the above matrix [F] or [C] and the input data string [x], and the latter when the number of input data is N=2n
(where n is a positive integer), the number of operations is significantly reduced by utilizing the periodic characteristics of the elements in the matrix and performing addition, subtraction, and multiplication in a butterfly form.

[Problem to be solved by the invention]

However, when the above-mentioned direct matrix calculation method is attempted to be implemented with a processor capable of vibrating processing, there is a problem in that at least the same number of multipliers as the number of input data is required.

In addition, since the algorithm used in the above-mentioned high-speed calculation is irregular, - Boat fishing is a method that is processed by a computer program, so if you try to implement it with a hardware configuration, the control will be complicated, making it unsuitable for algorithms to be introduced into equipment. There was a problem that.

The present invention has been made in view of the above-mentioned points, and in order to eliminate the above-mentioned problems, it has an algorithm that is easy to control, and is capable of performing vibration line processing using half the number of multipliers used in conventional matrix calculation methods. It is an object of the present invention to provide a discrete Hoonoe or cosine transform method and apparatus.

[Means to solve the problem]

In order to solve the above problems, the present invention provides N=2n (n is a positive number)
The discrete Fourier transform or discrete cosine transform method for the data of +
Walsh transformation matrix [W] and inverse Walsh transformation matrix [W-1] ((W) = [W-1]
), and in the first step, the product CZ)-[Wl]'[x] of the input data string [x] and the Walsh transformation matrix [W], which can be realized only by addition and subtraction, is calculated, and the second In the step calculation, a discrete Fourier transform matrix [F] or a discrete cosine transform matrix [C] and an inverse Walsh transform matrix (W-1) are used.
Product [Af:]=CF] [:W-1] or [Ac)
Calculate and prepare = (C) (W-1) in advance,
Product [y r ) with output [z] of first stage operation =
CA f ) CZ ) or [y,)=[Ac][Z
] is calculated.

[Effect]

By performing the discrete Fourier transform or discrete cosine transform method as described above, a Walsh transform having only +1 and -1 elements is introduced in the first stage calculation process, so the number of adders and subtracters equal to the number of input data N is used. In the second step, the matrix resulting from the product of the discrete Fourier or cosine transform matrix and the Walsh transform matrix has many zero elements.
Since the data can be compressed to /2 lines, pipeline processing using N/2 multiplications and N adders is possible [Embodiment] Hereinafter, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the operational order of the present invention. Identity, Discrete Fourier Transform: [y. L=[F)Ex:1=1/N[:F][]W-1](W)Cx) Discrete cosine transform: [y. ]=[C][x] =1/NEC)(W-1](W)[:x], the first
In step 3, the product of input data string [x] 1 and Walsh transformation matrix [W] 2 = [:Z) = [W) [x)] is calculated, and in the second step, the known discrete Fourier Product of transformation matrix [F] and inverse Walsh transformation matrix [W-1] [:
Af)=[”H)(W-1] or the product of the discrete cosine transformation matrix [C] and the inverse Walsh transformation matrix [:W-'] [
:Ac3-[:C](W-'] is calculated and prepared in advance, and its product with the output of the first stage calculation is [y,)=[:
Af) [Z) or Cy,] = (Ac) [Z] is calculated.

For example, in the case of N=8 (n=3), the Walsh transformation matrix [W] is given by The first stage operation can be realized by a pipeline configuration using only eight adders. The discrete Fourier transform matrix (F) and the discrete cosine transform matrix [C] in the case of N=8 are: ;a=1 b=ic c=exp (2πi/8) d=exp (−2πi/8) ;e= 1/J2 f=cos (π/16) g=cos (3π/16) h=cos (5π/16) 1=cos (7π/16) m=cos (π/8) n=cos (3π/8 ), and the product of each of the above and CW) is the Orsch transformation matrix; * is a non-zero number; * is a non-zero number. There are many elements that are zero in the matrices (Af) and [Ac'], and there is always one element that is zero in the same column of any two adjacent rows, so for example, as shown in Figure 2, , 1st and 2nd rows, 3rd and 4th rows
row, the 5th and 6th rows and the 7th and 8th rows are combined,
One multiplier is assigned to each set, and the operation results are allocated to registers that store the operation results of each row. Further, as shown in FIG. 2, since the timing of allocating the multiplication results to all groups is the same, it can be realized with one control signal. In this way, as long as N=2n is satisfied, [Afl and [
:Ac) has the above properties, so discrete Fourier or cosine transform for N input data can be realized by N/2 multipliers.

Next, an example of a conversion actual device that performs the conversion method on real vector data will be described with reference to FIGS. 3 to 6.

FIG. 3 is a block diagram showing the overall configuration of the conversion device. Vector data to be orthogonally transformed is input from terminal A. The data is sent to the first stage arithmetic block 10 and is converted into I"Z)-4W)[x
) matrix operations are performed. The result of this calculation is
For example, in Figure 3, N=23, so
When 8-dimensional vector data is input, terminals B1 to B are input.

Data is output to each simultaneously. The data becomes the input data of the output controller 20, and when eight pieces of data are input from the terminal A1, the output controller 20 can control the data output at once, and it takes eight clocks to input the data to the terminals sequentially starting from the terminal B1. Output to CI.

In the second stage calculation block 30, as shown in the explanation of the conversion method, in the case of the discrete two'/to conversion, (A
f) = [F) [W-clause, [A
c)=(C)(W-“) is calculated in advance, and a matrix operation is performed between that (Af1)[Ac:l and the input data from the terminal CI.The result of this operation is also N=23 In this case, when 8 pieces of input data are input, they are sent to the terminals from to D8, 8 pieces in the case of discrete cosine transform, 16 pieces in the case of discrete Fourier transform (in this case, 8 pieces of real part, Since the data of 8 imaginary parts is outputted, it is input to the output controller 40, and the input data from the terminals 1 to 1 is sequentially outputted to the terminal E, thereby controlling the output of the input data.

FIG. 4 is a block diagram showing a configuration for realizing the calculation of the first stage calculation block 10 in FIG. 3. This example shows a case where N=23, and the first stage calculation block 10 performs the above-mentioned matrix calculation of [z]=[W][x]. Here, [W] is a Walsh transformation matrix, and its transformation coefficients are only 1 and -1, so in matrix operations, the sign controller that can perform sign inversion and its value can be cumulatively added without using a multiplier. It can be configured with adders and registers that can perform Next, the connection state of each component and its operation will be explained using FIG.

Vector data to be orthogonally transformed is input from terminal A1, and the vector data is applied to each process element 11 to 1.
8 at the same time. Each process element 11-1
In step 8, one row of matrix calculation is performed.

Further, each of the process elements 11 to 18 has the same configuration except for the code control unit that performs code inversion, so the process element 11 will be used for explanation here.

First, input data is input to the sign controller 111, and the sign of the input data is controlled by the values of the matrix coefficients of the Walsh transform matrix. In other words, this code controller 1
In No. 11, if the value of the matrix coefficient is 1, the input data is output as is, and if it is -1, the sign is inverted and output. For example, if the process element is in charge of the second row of the matrix operation, the coefficient values are (1, -1, 1, -1, 1, -1, 1°1), so The first data is output as is, the sign of the next data is inverted, and the next data is output as is. The output of sign controller 111 is passed to adder 112. The output of adder 112 is sent to register 11
One of the outputs of the register 113 is input to the adder 112, and the other is the input of the register 113.
I can connect to 4. The adder 112 and the register 113 constitute a cumulative adder, and in this example, N=23, so after cumulatively adding the eight outputs from the sign controller 111, the operation result is stored in the register 114. It is output to terminal B. Similar processing is performed for the other process elements 12 to 18, and outputs are output to output terminals B, ~B, respectively.

FIG. 5 is a Pronk diagram showing an example of the configuration of the second stage calculation block 30 when performing a discrete Fourier transform, and FIG. 6 is a diagram showing an example of the configuration of the second stage calculation block 30 when performing a discrete cosine transform. FIG. The connection state and operation of each component will be explained below.

In the second stage of calculation, the pre-calculated matrix at the time of discrete Fourier transform 7x coefficient [Af) = CF
:] [W-1] ([:Ac1] during discrete cosine transform)
=[C:][W-']), and a matrix operation is performed between the vector data obtained above and the matrix operation result of the Walsh transformation.

Here, the matrix coefficient [A
If r1 becomes special and the number of zero coefficients increases considerably, and as explained earlier using Figure 2, it becomes possible to perform calculations on two rows at once, the number of multipliers becomes smaller than usual. It can be configured with half the number than the case. That is, in order to perform matrix operations on each row, the final stage cumulative adder that cumulatively adds the multiplication results is provided for each row, and the matrix coefficients can be multiplied with zero coefficients, so two multipliers are used. Calculation is possible by providing one per row. An example of a second stage arithmetic circuit when performing a discrete Fourier transform will be described below with reference to FIG.

The calculation results of the first stage are input from the terminal CI and can be input to each of the process elements 31 to 34. Each of the process elements 31 to 34 is responsible for matrix calculations for two rows. Each of the process elements 31 to 34 is basically the same in configuration and operation except for the content of ROM data required for multiplication, so the process element 31 will be used for explanation here. Some of the figures are marked with dashes, but since this operation is a discrete Fourier transform, the dashes are added to the arithmetic circuit side of the imaginary part to distinguish between the real part and the imaginary part. . The arithmetic circuits for the real part and the imaginary part have the same basic configuration and operation except for the ROM data required for multiplication, so the arithmetic circuit for only the real part will be described.

Pre-calculated matrix coefficient data [Ar:]=+:F)(w-1] is stored in the ROM 312. When input data is input to the multiplier 311 from the terminal C11, the data is stored in the ROM 312 at the same timing. Matrix coefficient data [Af1] = [F] (W
-1] is input to the register 113. The output of the multiplier 311 is connected to two adders 313 and 314,
The outputs of the adders 313 and 314 are respectively input to the register 31.
5.316. One output of register 315 is connected to the input of adder 313, and the other output is connected to register 317. Further, one output of the register 316 is connected to the input of the adder 314, and the other output is connected to the register 318. In other words, adder 3
13 and register 315 and adder 314 and register 31
6 constitutes a cumulative adder that cumulatively adds the multiplication results. The cumulative addition results are in registers 317.3 and 317.3.
It will be stored in 18.

The multiplier 311 has two rows worth of multiplication, and when one cumulative adder cumulatively adds the multiplication results, the other cumulative adder always has a multiplication result of zero, so there is no need to perform cumulative addition. By controlling whether or not to add the multiplication results on the cumulative addition side in this manner, matrix calculation becomes possible. For example, when the matrix coefficient in FIG.
14, the results of multiplication of the first four data and coefficients are cumulatively added in adder 313, and the results of multiplication of the remaining four data and coefficients are accumulated in adder 313.
14, cumulative addition is performed. The same thing is done for the imaginary part and other process elements 32-34.

And the result of the calculation is terminal, ~D,,D,'~Da'
You can output from.

Even in the case of discrete cosine transform, as shown in Figure 6,
Processing similar to that in FIG. 5 is performed. However, in the case of the discrete cosine transform shown in FIG. 6, only the real part is used, and there is no imaginary part calculation section as shown in FIG.

FIG. 7 is a block diagram showing a simplified example of the internal structure of the process element. Figure 5.

The process elements shown in FIG. 6 are shown as separate components to make the explanation of the ROM 312 and the multiplier 311 easier to understand, but in reality, the two functions are combined as a ROM multiplier 311a as shown in FIG. It is also possible to configure Furthermore, in the process elements shown in FIGS. 5 and 6, since the adder 313 and the adder 314 in the process element do not operate at the same time, it is possible to have a configuration in which the same adder 313 and adder 314 are used. In FIG. 7, the output of the adder 313 is directly read to a register 315 and a register 316, and when performing cumulative addition, the selector 319 selects the data output of the register to be cumulatively added and performs an operation. Store the calculation result in the register 317,
It fulfills the function of a process element by outputting.

〔Effect of the invention〕

As explained above, according to the present invention, the Walsh transform having only +1 and -1 elements is introduced in the first step calculation process, so the vibration line is generated by the same number of force subtracters as the number N of input data. In the second step of the calculation process, there are many zero elements in the matrix obtained by multiplying the discrete Fourier or cosine transform matrix by the Walsh transform matrix, so it can be compressed into N/2 rows. It is now possible to perform multiplication and Vibration line processing using N adders, and instead of increasing the number of N adders and subtractors compared to the conventional system, a larger VLS can be achieved while maintaining Vibration line processing.
The number of multipliers that require I area can be reduced by N/2, allowing for a more compact VLSI design.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the calculation order of the present invention, Fig. 2 is a conceptual diagram for compressing the matrix (Af) and CAc: ] in half, and Fig. 3 shows the overall configuration of the conversion device of the present invention. Figure 4 is a block diagram showing an example of the configuration of the first stage calculation, and Figure 5 is a block diagram showing an example of the configuration of the first stage calculation.
FIG. 6 is a block diagram showing an example of the configuration of the second stage calculation when performing discrete cosine transformation. FIG. 7 is a block diagram showing an example of the configuration of a simplified process element. It is a diagram. In the figure, 10...first stage calculation block, 20...
... Output controller, 30... Second stage calculation block, 40... Output controller, 11-1B... Process element. Patent Applicant Oki Electric Industry Co., Ltd. Agent Patent Attorney Takashi Kumagai (1 other person) ＃”
&f4L 5 T=incvg, QFII Fig. 2

Claims (3)

[Claims] (1) In the calculation method of discrete Fourier or cosine transformation of N=2^n (n is a positive integer) digital data, in the first stage calculation, a Walsh transformation matrix [W] with only +1 and -1 elements is used. and the input data [Z] = [W
] [x] is calculated only by addition and subtraction, and in the second step, the discrete Fourier transformation matrix [F] and the inverse Walsh transformation matrix [W^-^1] (= [W
]) [Af] = [F] [W^-^1] or the product of the discrete cosine transformation matrix [C] and the inverse Walsh transformation matrix [W^
-^1] and the product [Ac] = [C] [W^-^1] is calculated and prepared in advance, and the product of the output [Z] of the first stage operation and the product [Af] is calculated and prepared in advance. [yf] = [Af] [Z]
Or the product [yc] of the output [Z] and the product [Ac] =
[Ac] A discrete Fourier or cosine transformation method characterized by performing a matrix operation of [Z]. (2) The product prepared in advance [Af] or [
2. The discrete Fourier or cosine transform method according to claim 1, wherein the matrix operation is performed by dividing the vectors [Ac] into groups such that non-zero elements do not overlap. (3) When performing a matrix operation by grouping, the matrix operation is performed by providing one multiplier for the matrix operation of the two rows and distributing the multiplication result to two cumulative adders; Part 2
Claim (1) characterized in that the timing of distributing to one cumulative adder is the same as the timing of distributing to each two cumulative adders of other groups, and the same control signal can be used.
2) A transform device for carrying out the discrete Fourier or cosine transform method described.