JPS60160720A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60160720A JPS60160720A JP1640284A JP1640284A JPS60160720A JP S60160720 A JPS60160720 A JP S60160720A JP 1640284 A JP1640284 A JP 1640284A JP 1640284 A JP1640284 A JP 1640284A JP S60160720 A JPS60160720 A JP S60160720A
- Authority
- JP
- Japan
- Prior art keywords
- shift register
- rom
- signal
- multiplier
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H17/0607—Non-recursive filters comprising a ROM addressed by the input data signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
- H03H17/0621—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing
- H03H17/0635—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies
- H03H17/065—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer
- H03H17/0657—Non-recursive filters with input-sampling frequency and output-delivery frequency which differ, e.g. extrapolation; Anti-aliasing characterized by the ratio between the input-sampling and output-delivery frequencies the ratio being integer where the output-delivery frequency is higher than the input sampling frequency, i.e. interpolation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H2218/00—Indexing scheme relating to details of digital filters
- H03H2218/08—Resource sharing
Abstract
Description
【発明の詳細な説明】
＋１１ 発明の輌する分野
本発明は、時分割多電化された２チヤンネルのＰＣＭデ
ジタル信号に対して、レート変換デジタル・フィルタリ
ングを行なう半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION +11 Field of the Invention The present invention relates to a semiconductor device that performs rate conversion digital filtering on a time-division multiplexed two-channel PCM digital signal.
（２１従来の技術の説明
非巡回型デジタル・フィルターの基本構成を第１図に示
す。図に示すように、デジタル・フィルターは、入力デ
ジタル信号４を順次遅延する複数の遅延装置ｌとこの遅
延されたそれぞれのデータに係数を簀ける乗算器２と各
々の乗算結果を加算して出力信号５を得る加算器３から
成る。(21 Description of Prior Art) The basic configuration of an acyclic digital filter is shown in FIG. The multiplier 2 includes a multiplier 2 that stores coefficients in each data, and an adder 3 that adds the results of each multiplication to obtain an output signal 5.
従来、この種の演算をする半導体装置は、データ遅延に
用いるＲＡＭと、係数を格納するＲＯＭと、専用の乗算
器、加算演算のため演算回路等から成っている。この種
のデジタル信号処理装置は、プログラムや係数ＲＯＭの
変更により種々雑多の信号処理を可能として、汎用性に
すぐれている。Conventionally, a semiconductor device that performs this type of operation consists of a RAM used for data delay, a ROM that stores coefficients, a dedicated multiplier, an arithmetic circuit for addition operations, and the like. This type of digital signal processing device has excellent versatility as it can perform various types of signal processing by changing programs and coefficient ROMs.
しかし、レート変換を目的とし、高いサンプリング周期
のデータを処理しようとした場合、サンプリングとテン
ブリングの間にできる槓和算の数は、限界がありおのず
と帯域外減衰量に限界が生じ。However, when attempting to process data with a high sampling period for the purpose of rate conversion, there is a limit to the number of summations that can be performed between sampling and tenbling, which naturally limits the amount of out-of-band attenuation.
仮に所望の減衰量を得ようとすると９ｊｅ算益を複数用
い、並列処理を行なわねはならない場合も生じる。この
結果ハード・フェアが増大する結果となってしまう。If a desired amount of attenuation is to be obtained, it may be necessary to use a plurality of 9je calculations and perform parallel processing. This results in an increase in hard fairs.
別の積和方式としてＲＯＭ積和と呼はれる方法が有る。Another product-sum method is a method called ROM product-sum method.
仁の方法は、ビットごとの積をめらかしめＲＯＭに内蔵
させ、その出力によりシフトと加算をくりかえし、演算
結果を得るものである。この方法によれは、原理的には
最小所要クロック数はワード長（ビット数）でよく、積
和の数すなわち、タップ数が所要クロック数に影曽され
ないため、比較的容易に集積化が可能である。また乗算
器を複数必要としないためハードウェアの規模も小さく
なる。反面、並列処理をするため配線領域が増加する欠
点がおる。In Jin's method, the product for each bit is smoothed and stored in a ROM, and the output is used to repeat shifting and addition to obtain the calculation result. With this method, in principle, the minimum required number of clocks is just the word length (number of bits), and the number of sums of products, that is, the number of taps, is not affected by the number of required clocks, so integration is relatively easy. It is. Furthermore, since multiple multipliers are not required, the scale of the hardware is also reduced. On the other hand, there is a drawback that the wiring area increases due to parallel processing.
（３） 発明の目的
本発明の目的は、配線領域が小さくかつ全体としてのチ
ップ専有面積の小さなレート変換ディジタルフィルター
用半導体装ｔｔ−得ることにおる。(3) Purpose of the Invention An object of the present invention is to obtain a semiconductor device for a rate conversion digital filter which has a small wiring area and a small chip area as a whole.
（４１発明の構成
本発明によれは、ｆジタル信号を入力するシフトレジス
タと、？：、のシフトレジスタの偶数次シフト段および
奇数次シフト段の出力を係数乗算してそれぞれ累積加算
する乗算番加算回路？シフトレジスタの左右にそれぞれ
配置し、これら２つの乗算・加算回路の出力を加え合わ
すマルチプレクサを設け、これらシフトレジスタ、２つ
の乗算−加算回路およびマルチプレクサ−を同じ半導体
チップ上に設けた半導体装置を得る。(41 Structure of the Invention According to the present invention, the outputs of the even-order shift stage and the odd-number shift stage of the shift register input with the f-digital signal are multiplied by coefficients and cumulatively added. Addition circuit? A semiconductor in which multiplexers are placed on the left and right sides of a shift register and add the outputs of these two multiplication/addition circuits, and these shift registers, two multiplication/addition circuits, and a multiplexer are provided on the same semiconductor chip. Get the equipment.
（５）発明の原理
発明者はｌ１１８和５８年ｌθ月５日付で出願した特願
昭５８−１８６５４５号で２チヤンネルのＰＣＭデジタ
ル信号に２倍レート変換を行なう場合、偶数次。(5) Principle of the invention In Japanese Patent Application No. 58-186545 filed by the inventor on May 5, 1118, 1985, when performing double rate conversion to a 2-channel PCM digital signal, the even order.
奇数次のそれぞれのフィルタを２チヤンネルの信号が多
重使用すれは効率よく処理できることを示した。本発明
は、前記先願にかかる発明と前述のＲＯＭ［相方式とを
半導体素子上で組み合わせたものである。It was shown that multiple use of two channels of signals by each odd-order filter can be efficiently processed. The present invention is a combination of the invention according to the prior application and the above-mentioned ROM [phase system] on a semiconductor element.
ＲＵＭ積和積和法式第２図に処理の流れをブロック図で
示したように、入力信号４′を遅延する遅延装置として
シフトレジスタ６ｔ−用いる。このシフトレジスタ６に
２チヤ／ネルの信号を交互に入カシ、ソのシフト・レジ
スタ６の出力’ｋＲ互に奇数次ＲＯＭ積和回路７と偶数
次ＲＯＭ積和回路８Ｓ【
回路７からの出力と偶数次ＲＯＭ積和回路８からの出力
とをマルチプレクサ−９で加算して出力５′を得ている
。RUM product-sum product method As shown in the block diagram of the processing flow in FIG. 2, a shift register 6t is used as a delay device for delaying the input signal 4'. The signals of the 2 channels/channels are input alternately to this shift register 6, and the output of the shift register 6 is 'kR'. and the output from the even-order ROM product-sum circuit 8 are added together by a multiplexer 9 to obtain an output 5'.
半導体素子上では、このシフト・レジスタ６を積和回路
８とをシフト・レジスタ６の左右に配置し、ＲＯＭ、加
算器を順次配列すれは、デジタル・フィルターは実現で
きる。On a semiconductor device, a digital filter can be realized by arranging this shift register 6 and the product-sum circuit 8 on the left and right sides of the shift register 6, and arranging a ROM and an adder in sequence.
（６）発明の実施例 第３図に本発明の一実施例のブロック図を示す。(6) Examples of the invention FIG. 3 shows a block diagram of an embodiment of the present invention.
半導体ベレット２２上に入力信号を遅延するシフトレジ
スタ１６ｔ−配置する。このシフトレジスタ１６の上下
に乗算する係数をＲＯＭに記憶している乗算器２０ｔ−
有している。これら乗算器２０の！ｉｔはそれぞれ加算
器２１で加算されマルチプレクサ−１９で加え合わされ
て出力を得る。A shift register 16t for delaying input signals is arranged on the semiconductor bellet 22. A multiplier 20t- that stores coefficients to be multiplied above and below this shift register 16 in ROM.
have. of these multipliers 20! It is added by an adder 21 and added together by a multiplexer 19 to obtain an output.
このように、中央にシフト−レジスタ１６’に配し、そ
の両側にそれぞれ乗算器２０と加算器２１とのＲＯＭ積
和回路を配置して、シフトレジスタ１６の出力を交互に
各側に出力するようにすれば配線領域°が並列処理にも
かかわらず、小さくなり、半導体装置の面積を小さくす
る効果が生じる。すなわち、低価格で高性能レート変換
テジタルフィルターを実現することができる。In this way, a shift register 16' is placed in the center, and ROM product-sum circuits including a multiplier 20 and an adder 21 are placed on each side of the shift register 16', and the output of the shift register 16 is alternately output to each side. By doing so, the wiring area can be reduced despite parallel processing, resulting in the effect of reducing the area of the semiconductor device. In other words, a high-performance rate conversion digital filter can be realized at a low cost.
ｓｔ因は、従来の非巡回型デジタルフィルターのブロッ
ク図である。
第２因は、従来のＲＯＭ積相方式によるティジタルフィ
ルターのブロック図でおる。
第３図は、本発明の一実施例を示すブロック図でｈる。
ｌ・・・・・・遅延装置、２・・・・・・係数乗算器、
３・・・・・・加算器％ ４・・・・・・ＰＣＭデジタ
ル信号入力、５・・・・・・デジタル信号出力、６・・
・・・・シフト・レジスタ、７・・・・・・奇数次ＲＯ
Ｍ積和回路、８・・・・・・偶数次ＲＯＭ積和回路、９
・・・・・・マルチプレクサ、ｌｏ・・・・・・乗算器
、１１・・・・・・加算器。
冗１図
ゞ＼寸
′ｙＦ１３図1 is a block diagram of a conventional acyclic digital filter. The second factor is a block diagram of a digital filter based on the conventional ROM multiplication method. FIG. 3 is a block diagram showing one embodiment of the present invention. l... Delay device, 2... Coefficient multiplier,
3... Adder % 4... PCM digital signal input, 5... Digital signal output, 6...
...Shift register, 7...Odd order RO
M product-sum circuit, 8...Even-order ROM product-sum circuit, 9
...Multiplexer, lo...Multiplier, 11...Adder. Figure 1
Claims (1)
交互に出力するシフトレジスタと、該シフトレジスタの
左右に設けられ、該シフトレジスタ数次積和回路と、該
偶数次および奇数次積和回路の出力を加え合わすマルチ
プレクサとを有し、前記シフトレジスタ、前記偶数次お
よび奇数次積和回路および前記マルチプレクサと２同じ
半導体テップ上に形成したことを特徴とする半導体装置
。A shift register that shifts the input No. 1g and outputs the output side alternately on the left and right each time it is shifted by one stage, a shift register multi-order product-sum circuit provided on the left and right sides of the shift register, and the even-order and odd-order 1. A semiconductor device comprising: a multiplexer for adding together the outputs of the product-sum circuit; and wherein the shift register, the even-order and odd-order product-sum circuits, and the multiplexer are formed on the same semiconductor chip.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1640284A JPS60160720A (en) | 1984-01-31 | 1984-01-31 | Semiconductor device |
| EP84111952A EP0137464B1 (en) | 1983-10-05 | 1984-10-05 | A digital signal processing apparatus having a digital filter |
| DE8484111952T DE3484701D1 (en) | 1983-10-05 | 1984-10-05 | DIGITAL SIGNAL PROCESSING DEVICE WITH A DIGITAL FILTER. |
| US06/657,910 US4777612A (en) | 1983-10-05 | 1984-10-05 | Digital signal processing apparatus having a digital filter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1640284A JPS60160720A (en) | 1984-01-31 | 1984-01-31 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60160720A true JPS60160720A (en) | 1985-08-22 |
| JPH043689B2 JPH043689B2 (en) | 1992-01-24 |
Family
ID=11915246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1640284A Granted JPS60160720A (en) | 1983-10-05 | 1984-01-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60160720A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01144732A (en) * | 1987-07-06 | 1989-06-07 | Grass Valley Group Inc:The | Sub-range band digital filter and method of contraction and expansion of data rate |
| JPH0282807A (en) * | 1988-08-30 | 1990-03-23 | Internatl Business Mach Corp <Ibm> | Digital filter |
-
1984
- 1984-01-31 JP JP1640284A patent/JPS60160720A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01144732A (en) * | 1987-07-06 | 1989-06-07 | Grass Valley Group Inc:The | Sub-range band digital filter and method of contraction and expansion of data rate |
| JPH0282807A (en) * | 1988-08-30 | 1990-03-23 | Internatl Business Mach Corp <Ibm> | Digital filter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH043689B2 (en) | 1992-01-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |