JP2599984B2 - Input data peak value detection circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peak value detecting circuit for detecting a peak value of a serially input data string in a semiconductor integrated circuit.

[Conventional technology]

Conventionally, this kind of peak value detection circuit has an n-bit serial / parallel conversion circuit 11 for converting serial input data into parallel data after inputting the serial input data, as shown in FIG. N-bit register 12 for holding the input data, n-bit register 14 for holding the peak value data of the input data, inverter circuit 15 for inverting the peak value data, and the input data and the inverter circuit 15 for inverting the input data. N-bit adder for inputting the data of the peak value and comparing the magnitudes of the two values
16 and a switch circuit 13 for selecting peak value data in accordance with the comparison result, and is configured to detect the peak value of serially input data. In FIG. 4, 1 is an input terminal for serially inputting input data, 2 is an output terminal for serially outputting peak value data, and Ao to An-1 are n-bit input data. , And Bo to n−1 indicate n-bit peak value data, respectively.

 Next, the operation will be described.

First, the serial n-bit input data Ao to An-1 is converted from the input terminal 1 into parallel data input to the serial / parallel conversion circuit 11. Next, the data of each parallel bit is held in the n-bit register 12, and its output is input to one input terminal of the n-bit adder 16. The peak value data of the input data Ao to An-1 is held in the n-bit register 14, and its output is inverted by the inverter circuit 15 and input to the other input terminal of the n-bit adder 16. Here, the n-bit adder 16 performs addition by inputting 1 as a carry input to the input data and the inverted peak value data. That is, the n-bit adder 16 subtracts the input value from the peak value. For example, if the input value is greater than or equal to the peak value, the carry output of the n-th bit of the n-bit adder 16 becomes 1 (High), and if the input value is smaller than the peak value, it becomes 0 (Low). .

Next, the carry output of the n-th bit is supplied to the switch circuit 13.
Is input to Here, if the switch circuit 13 is turned on at 1 (High), the n-bit register 14 always holds the data of the maximum value, which is one peak value. If the switch circuit 13 is turned on at 0 (Low), the n-bit register 14 always holds the data of the minimum value which is one peak value.

Next, as shown in FIG. 5, a 4-bit example will be described for simplicity. In this case, an example of the maximum value is shown as one peak value. Here, as shown in FIGS. 5 (a) and 5 (b), assuming that the input value is 5 and the previous peak value is 3, a 4-bit adder is used.
The input to 16 is as shown in FIG. 5C, and the carry output of the fourth bit is 1 (High). Next, the carry output is input to the switch circuit 13. When the switch circuit 13 is 1 (High), the switch circuit 13 becomes conductive and the 4-bit register 14
Is rewritten with the input data, and the peak value becomes 5.

Assuming that the next input value is 4, the input to the 4-bit adder 16 is as shown in FIG. 6C, as in FIG. 5C. In this case, the carry output of the fourth bit is 0 (Low), and the switch circuit 13 does not conduct. Therefore, the data of the n-bit register 14 is held, and the peak value becomes 5.
As described above, conventionally, the maximum value or the minimum value that is the peak value of the serially input input data is detected from the output terminal 2.

[Problems to be solved by the invention]

Since the conventional peak value detection circuit is configured as described above, an adder corresponding to the number of data between the input value and the peak value is required, and the problem is that the area of the semiconductor integrated circuit increases as the number of data increases. There was a point.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. One of data serially input and data of a peak value is inverted, and both data are added bit by bit. An object of the present invention is to provide a peak value detection circuit for input data which can reduce the circuit area irrespective of the number of data between the input value and the peak value by comparing the magnitude of both data with the final carry output by addition.

[Means for solving the problem]

A peak value detection circuit for input data according to the present invention is configured such that input data from a first register (n-bit register 3), inverted data of peak value data from an inversion circuit (inverter circuit 6), and carry input are 1 bit. Each time,
Alternatively, the peak value data from the second register (n-bit register 4), the inversion data of the input data from the inversion circuit (inverter circuit 6) and the carry input are added for each bit, and the addition is performed. An adder (1-bit adder) 7 for outputting the carry as a carry output;
A carry control circuit 8 outputs the carry output from the adder 7 as an input with the first carry input as 1 and outputs the carry output from the adder 7 to the adder 7 as a carry input for the next bit addition. A final carry output as a result of adding up to the last bit by the adder 7 is input from the carry control circuit 8, and based on the final carry output, the magnitude relationship between the input data and the peak value data is compared. And a switch circuit 9 for transferring data resulting from the peak value to a second register (n-bit register 4).

[Action]

The input data peak value detecting circuit adds the input data from the first register (n-bit register 3), the inverted data of the peak value data from the inverting circuit (inverter circuit 6), and the carry input for each bit. Alternatively, the peak value data from the second register (n-bit register 4), the inverted data of the input data from the inverting circuit (inverter circuit 6), and the carry input are added for each bit, and The resulting carry is output as a carry output. At that time, the carry input is first input to an adder (1-bit adder) 7, and the carry output output from the adder 7 is added to the next bit. Is input to the adder 7 as a carry input, and based on the final carry output as a result of adding up to the last bit, the input data and Comparing the magnitude of over click value data, transfer the data and the results peak value in the second register (n-bit register 4).

(Example of the invention)

Hereinafter, the present invention will be described based on embodiments shown in the drawings. FIG. 1 is a block diagram showing a basic configuration of a peak value detection circuit according to one embodiment of the present invention. In the figure, 1
Are input terminals for inputting input data serially, 2
Is an output terminal for serially outputting peak value data, and 3 is an n-bit register (first bit) for holding input data.
4) An n-bit register (second register) for holding peak value data among input data, 5 is a serial / parallel conversion circuit for serially inputting peak value data and converting it into parallel data And are continuously connected to the input terminal 1 respectively. Also,
6, an inverter circuit (inverting circuit) for inverting peak value data serially output from the n-bit register 4;
Reference numeral 7 denotes a 1-bit adder for serially inputting the input data and data of the peak value inverted by the inverter circuit 6 and comparing the two data with each other. Reference numeral 8 controls a carry output of the 1-bit adder 7. A carry control circuit 9 is a switch circuit for selecting peak value data from the serial / parallel conversion circuit 5 according to the comparison result and transferring the data to the n-bit register 4. Ao to An
-1 indicates n-bit input data, and Bo to Bn-1 indicate n-bit peak value data.

 Next, the operation of the above embodiment will be described.

N-bit input data Ao to An-1 are serially input from an input terminal 1 to an n-bit register 3. At this time, the peak value data Bo to Bn are stored in the n-bit register 4.
It is assumed that -1 is held. Here, the input data of the n-bit register 3 is serially output, input to one input terminal of the 1-bit adder 7, and input to the n-bit register 4 which is continuously connected. The data of the peak value of the n-bit register 4 is output serially from the output terminal 2 and is also input to the serial / parallel conversion circuit 5 connected in cascade. Further, the peak value data is inverted by the inverter circuit 6 and input to the other input terminal of the 1-bit adder 7.

Next, the one-bit adder 7 further adds a carry control circuit 8 to the addition of the input data and the inverted peak value.
Add the carry input from. Here, as shown in FIG. 2C, the carry control circuit 8 compares the first, for example, the least significant bit with the 1-bit adder 7
Is set to 1 (High), and the carry output output from the 1-bit adder 7 for the previously added bit is used as the carry input when the next bit is added. Then, a final carry output as a result of adding up to the final n-th bit output from the 1-bit adder 7 is input to the switch circuit 9 for control. At this time, the carry output of the n-th bit of the 1-bit adder 7 becomes 1 (High) if the input value is larger than or equal to the peak value, and becomes 0 (Low) if the input value is smaller than the peak value.

Here, assuming that the switch circuit 9 is turned on at 0 (Low), the peak value data is converted into parallel data by the serial / parallel conversion circuit 5 and input to the n-bit register 4. In this case, the n-bit register 4 always holds the maximum value which is one peak value. If the switch circuit 9 is turned on at 1 (High), the n-bit register 4 always holds a minimum value, which is one peak value.

Next, as shown in FIG.
An example will be described using bits. In this case, a data example of the maximum value which is one peak value of the input data is shown.

If the input value of the input data is 5 and the peak value is 3, as shown in FIGS. 2A and 2B, the input to the 1-bit adder 7 is as shown in FIG. 2C. As the first carry input, 1 (High) is input to the 1-bit adder 7, and the least significant 1-bit data is added to each other. As a result of this addition, the carry output of the first bit becomes 1 (High). .
This carry output becomes the carry input of the 1-bit adder 7 for the next bit by the carry control circuit 8. In this way, the final carry output of the fourth bit, which is the most significant bit, becomes 1 (High), and the final carry output is input to the switch circuit 9 by the carry control circuit 8. At this time, the switch circuit 9
When the input is 0 (Low), it is conductive, and when the input is 1 (High), it is not conductive. The input data is held in the 4-bit register 4 and the peak value becomes 5.

Next, assuming that the input value is 4, the input to the 1-bit adder 7 is as shown in FIG. 3 (c), as in FIG. 2 (c). In this case, the carry output of the fourth bit becomes 0 (Low), and the switch circuit 9 becomes conductive. Therefore, the data of the peak value is converted into parallel data by the serial / parallel conversion circuit 5 and input to the 4-bit register 4, and the peak value becomes 5.

In this manner, the maximum value or the minimum value, which is the peak value of the input data serially input, can be detected from the output terminal 2.

In the above embodiment, the peak value data held in the n-bit register 4 is inverted.
May be inverted.

〔The invention's effect〕

As described above, according to the present invention, either one of the serial input data and the peak value data is inverted, and both data are added one bit at a time. Because it was configured to do
The above addition can be performed by a 1-bit adder without using an n-bit adder corresponding to the number of data between the input value and the peak value as in the related art, and thus the circuit area of the semiconductor integrated circuit can be reduced. The effect of being able to achieve is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a peak value detection circuit according to one embodiment of the present invention, and FIGS.
3 (c) and FIGS. 3 (a), 3 (b) and 3 (c) show an example of data input and output in this embodiment, and FIG. 4 is a block diagram showing a basic configuration of a conventional peak value detecting circuit. FIGS. 5 (a), 5 (b) and 5 (c) and FIGS. 6 (a), 6 (b) and 6 (c) show examples of data input / output in this conventional example. 3... N-bit register (first register), 4.
Bit register (second register), 5... Serial /
Parallel conversion circuit, 6: Inverter circuit (inverting circuit), 7: 1-bit adder, 8: Carry control circuit, 9: Switch circuit

Claims (1)

(57) [Claims] 1. A first register for holding serial input data, a second register for holding peak value data among data held in the first register, and a first register for holding data in the first register. A peak value detecting circuit having an inverting circuit for inverting one of the input data obtained and the peak value data held in the second register, wherein the input data from the first register and the inverting circuit are provided. The inverted data of the peak value data from the
The addition is carried out bit by bit, or the peak value data from the second register, the inverted data of the input data from the inverting circuit and the carry input are added bit by bit, and the carry generated by the addition is carried out. And the first carry input is set to 1 and output to the adder,
A carry control circuit for receiving the carry output from the adder and outputting the carry output to the adder as a carry input for the next bit addition; and a final carry output as a result of adding up to the last bit by the adder. And a switch circuit for comparing the magnitude relationship between the input data and the peak value data based on the final carry output from the control circuit, and transferring the resulting data as the peak value to the second register. A peak value detection circuit for input data that is a feature.