JPH05257643A - Binary complement unit - Google Patents

Abstract

PURPOSE:To obtain the complement unit of simple constitution which maintains the relation of negative-to-positive conversion without fail. CONSTITUTION:Data input terminals for (n) bits are coupled with (n) bits of one side of an adder 14 through inverters, the output side of a NAND circuit 15 is coupled with the least-digit input terminal CO among input terminals for (n) bits of the other side of the adder 14, and the remaining inputs are grounded; and the largest-digit input terminal E3 among the input terminals of the NAND circuit 15 is coupled with the largest digit A3 of (n)-bit data, other terminals are coupled with the output sides of the inverters except the largest digit in order, and a complementary number is obtained from the output terminals for (n) bits of the adder 14. For example, when negative maximum values 1, 0, 0, and 0 are inputted as 4-bit input data, they are inverted and 0, 1, 1, and 1 are inputted to the adder; and thus 0, 1, 1, and 1 are outputted for the input of 1, 0, 0, and 0, and consequently the negative-to-positive conversion is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary complementer used to obtain a negative number in a computer or the like.

[0002]

2. Description of the Related Art Conventionally, when a binary complementer is constructed by an adder, it becomes as shown in FIG. That is, the digital signals input from the n-bit data input terminals A0, A1, A2, A3 are inverted by the inverters 10, 11, 12, 13 and one input terminal B0, B1, B2, B of the adder 14 is inverted.
Enter in 3. This adder 14 has the other input terminal C
1 is always added from 0, C1, C2 and C3. Then, the complement of the input number is obtained at the output terminals D0, D1, D2 and D3.

Specifically, in FIG. 4, A0, A1,
If the data input to A2 and A3 are 0, 0, 0 and 1, they are inverted by the inverters 10, 11, 12 and 13,
Inputs to B0, B1, B2, B3 are 1, 1, 1, 0. The inputs to the other C0, C1, C2 and C3 are always 0, 0, 0 and 1, so this 1 is added and D
As outputs from 0, D1, D2 and D3, input complements 1, 1, 1, 1 are obtained. Similarly, A0, A1, A
When 2, A3 is 0,1,1,1, D0, D1, D
For 2, D3, complements 1, 0, 0, 1 are obtained. The same applies to other cases.

[0004]

However, in this conventional complementer, the maximum negative value of 1 for A0, A1, A2 and A3,
When 0, 0, 0 is input, B0, B1, B2, B3 are
0, 1, 1, 1, and C0, C1, C2, C3 are always 0, 0, 0, 1, so this 1 is added to D
1, 0, 0, 0 is obtained in 0, D1, D2, D3. As described above, there is a problem in that the output becomes 1, 0, 0, 0 with respect to the input of 1, 0, 0, 0, and there is a relation of conversion from negative to negative.

It is an object of the present invention to obtain, with a simple structure, one in which the relationship of conversion from negative to positive is always maintained.

[0006]

According to the present invention, an adder 14 is provided for each of n-bit data input terminals via an inverter.
Is connected to one of the n-bit input terminals of
Of the other n-bit input terminals, the output side of the NAND circuit 15 is coupled to the input terminal of the least significant digit, the remaining input terminals are grounded, and the input terminal of the most significant digit of the NAND circuit 15 input terminals is It is connected to the maximum digit of the n-bit data input terminal, the other input terminals are sequentially coupled to the output side of the inverter other than the maximum digit, and the complement is obtained from the n-bit output terminal of the adder 14. It is a binary complementer.

[0007]

Operation: When n-bit (for example, 4-bit) input data is
When 0, 0, 0, 1 is inverted by the inverter and the data input to the adder becomes 1, 1, 1, 0. The inputs to the NAND circuit 15 are 0, 1, 1, 0. Here, the output of the NAND circuit 15 is all 1 except that the input to the NAND circuit 15 is 0 when the input to this NAND circuit 15 is 1, 1, 1, and 1, so the minimum digit of the other input of the adder is 1. Is.
Therefore, the other input of the adder becomes 0, 0, 0, 1 and this 1 is added, and the complements of the input 1, 1, 1, 1 are obtained as the output of the adder. Similarly, when the input data is 0, 1, 1, 1, the output is complement 1, 0,
0 and 1 are obtained. The same applies to other cases.

Next, as the input data, the maximum negative value 1,
When 0, 0, 0 is input, it is inverted by the inverter and the data input to the adder becomes 0, 1, 1, 1. The inputs to the NAND circuit 15 are 1, 1, 1, 1. Here, the output of the NAND circuit 15 has inputs 1, 1,
Since it becomes 0 only when it is 1, 1, the other input of the adder becomes 0, 0, 0, 0, and 0, 1, 1, 1 of the data input to the adder as the output of the adder Can be obtained as is. In this way, for inputs of 1, 0, 0, 0, outputs become 0, 1, 1, 1 and conversion from negative to positive is performed.

[0009]

EXAMPLE An example of the present invention will be described below. In FIG. 1, n-bit (for example, 4-bit) data input terminals A0, A1, A2, and A3 are connected to inverters 10, 11, and 1.
One of the input terminals B0 and B of the adder 14 via
It binds to 1, B2 and B3. The adder 14 is provided with the other input terminals C0, C1, C2 and C3, of which C1, C2 and C3 are grounded. A NAND circuit 15 is coupled to the remaining minimum digit input terminal C0, and the input terminals E0, E1, E2 of the NAND circuit 15 are connected.
Of E3, E0, E1, and E2 are coupled to the output sides of the inverters 10, 11, and 12, respectively, and only the maximum digit input terminal E3 is directly coupled to the maximum digit A3 of the data input terminal. D0, D1, D2 and D3 are output terminals.

The operation of the above structure will be described with reference to FIG. Data input terminals A0, A1, A2, A3
When the data input to 0 is set to 0, 0, 0, 1, it is inverted by the inverters 10, 11, 12, 13 and the adder 14
The input to one of the input terminals B0, B1, B2, B3 is
It becomes 1, 1, 1, 0. The input terminals E0, E1, E2, E3 of the NAND circuit 15 have the data input terminal A0 of 0 and the outputs of the inverters 10, 11, 12 are 1, 1, 0. , 0. Here, the output of the NAND circuit 15, that is, C0, is such that the inputs E0, E1, E2, E3 of the NAND circuit 15 are 1, 1,
C0 because all are 1 except 0 when 1 and 1
Is 1. Therefore, the other input terminal C of the adder 14
0, C1, C2, C3 become 0, 0, 0, 1 and this 1 is added to the output terminals D0, D1, D2, D3, which are 1, 1, 1, 1 of the complement of the input. Is obtained. Similarly,
Data input terminals A0, A1, A2, A3 are 0, 1,
When 1, 1, output terminals D0, D1, D2, D3,
The complements 1, 0, 0, 1 are obtained. The same applies to other cases.

Next, the data input terminals A0, A1, A
When the maximum negative value 1, 0, 0, 0 is input to 2, A3, one input terminal B0, B1, B2, B3 of the adder 14 becomes
It becomes 0, 1, 1, 1. The input terminals E0, E1, E2, E3 of the NAND circuit 15 are 1, 1, 1, 1.
Here, the output of the NAND circuit 15, that is, C0 is E
0 only when 0, E1, E2, E3 are 1, 1, 1, 1
Therefore, the other input terminals C0, C1, of the adder 14
C2 and C3 become 0, 0, 0, 0, and output terminal D
0, D1, D2, D3 include input data 0, 1, 1, and 1 to one input terminal B0, B1, B2, B3 of the adder 14.
1 is obtained as it is. In this way, 1, 0, 0,
For 0 input, output becomes 0, 1, 1, 1 and conversion from negative to positive is performed.

In the above-described embodiment, the case of 4 bits has been described as an example, but the present invention is not limited to this and can be applied to the case of n bits.

[0013]

According to the present invention, an n-bit data input terminal is coupled to one of n-bit input terminals of an adder 14 via an inverter, and the n-bit other input terminal of the adder 14 is connected. , NAND circuit 1 to the input terminal of the smallest digit
5 is connected to the output side, the remaining input terminals are grounded, and the input terminal of the largest digit among the NAND circuit 15 input terminals is the n-th input terminal.
Since it is connected to the maximum digit of the bit data input terminal, the other input terminals are sequentially coupled to the output side of the inverter other than the maximum digit, and the complement is obtained from the n-bit output terminal of the adder 14. , Even if the maximum negative value is input, there is no relation of conversion from negative to negative,
The relationship of conversion from negative to positive is always maintained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a binary complementer according to the present invention.

FIG. 2 is an explanatory diagram of binary complement conversion according to the present invention.

FIG. 3 is a block diagram of a conventional binary complementer.

FIG. 4 is an explanatory diagram of conventional binary complement conversion.

[Explanation of symbols]

10, 11, 12, 13 ... Inverter, 14 ... Adder,
15 ... NAND circuit.

Claims (1)

[Claims] 1. An n-bit data input terminal is coupled to one of n-bit input terminals of an adder 14 via an inverter, respectively, and the n-bit other input terminal of the adder 14 has the least significant digit. The output side of the NAND circuit 15 is connected to the input terminal, and the remaining input terminals are grounded.
Of the five input terminals, the input terminal of the maximum digit is coupled to the maximum digit of the n-bit data input terminal, and the other input terminals are sequentially coupled to the output side of the inverter other than the maximum digit, respectively, A binary complementer, wherein a complement is obtained from an n-bit output terminal.