JPH0377538B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Exception value A of input data in decimal addition/subtraction circuit
Using the fact that ~F is a value in the range of 0 to 5 in both the output of the +6 adder during addition and the output of the complement circuit during subtraction, the same decimal data exception is generated for both addition and subtraction. Apply detection logic and simplify the circuit.

[Industrial application field]

The present invention relates to a data processing device,
In particular, it relates to data exception detection methods for decimal addition/subtraction circuits.

[Conventional technology]

Generally, in decimal subtraction using binary coded decimal numbers,
It is necessary to perform 6 corrections according to the calculation results.

FIG. 3 shows a typical example of such a conventional decimal addition/subtraction circuit.

In the figure, 31 is a +6 adder, 32 is a selector, 33 is a main adder, 34 is a complement circuit, and 35 is a
Decimal correction circuit, 36 is a decimal data exception detection circuit,
A and B represent input data, and CARRY represents a carry to the lowest digit.

Next, the basic operations will be explained for decimal addition and decimal subtraction.

Decimal addition Add 6 to each digit of input data B using the +6 adder 31. The result is selected by the selector 32, inputted to the main adder 33, and subjected to binary addition with the input data A. At this time, the decimal correction circuit 35 subtracts 6 only for digits that do not cause carry.

For example, when A=5649 and B=3291, the output of the +6 adder 31 is 3291 +6666 98F7. The main adder 33 converts this into “5649” of A and 2
By performing base addition, it becomes 5649 + 98F7 sum EF40 carry 0011, and the sum "EF40" is obtained. At this time, no carry occurs in the "E" and "F" digits.

Therefore, in the decimal correction circuit 35, "E",
A correction is made by subtracting "6" from each "F".

EF40 −6600 8940 In this way, “8940” is obtained as the decimal addition result.
is obtained.

Decimal subtraction Input data B is selected by the selector 32, and the complement circuit 34 of the main adder 33 multiplies it by 1, and the result, input data A, and CARRY=1 are converted into 2.
Add base. At this time, the decimal correction circuit 35 subtracts 6 only for digits that do not cause carry.

For example, in the case of A=7392 and B=4718, the complement circuit of the main adder 33 multiplies 1 for B,
In other words, the hexadecimal number “F” is complemented, resulting in FFFF −4718 B8E7. Add this to A=7392 and CARRY=1 to obtain 7392 +B8E7 (1)2C79 +0001 (CARRY) Sum 2C7A Carry 1010. The digits that do not cause carry in this addition are "C" and "A". Therefore, the decimal correction circuit 35 corrects these by subtracting "6", and 2C7A -0606 2674 yields "2674" as the decimal subtraction result.

Here, the decimal data exception detection circuit 36 detects a decimal data exception in the data on the addend or subtraction input side of the main adder 33. In other words, if the value of each digit of input data B exceeds the range of 0 to 9,
This is to treat this as an error if it has a value in the range of ~F. However, in the case of addition, input data B is set to "6" by 6+adder 31.
is added, so the values of A to F above change to values of 0 to 5.

Therefore, in the decimal data exception detection circuit 36,
In the case of addition, a digit value of 0 to 5 is detected as a decimal exception, and in the case of subtraction, a digit value of A to F is detected as a decimal exception.

[Problem that the invention seeks to solve]

In conventional decimal addition/subtraction circuits, separate methods must be used for addition and subtraction to detect decimal data exceptions, making the configuration of the detection circuit complex.

[Means for solving problems]

In the present invention, the data input circuit of the decimal addition/subtraction circuit is devised so that the exception detection method of the decimal data exception detection circuit in the decimal addition/subtraction circuit can be shared between addition and subtraction.

Therefore, in the present invention, when 6 is added to the decimal data, the values of A to F become 0 to 5, and when the 1's complement is taken for the decimal data, the values of A to F become 5 to 0. Focusing on this, during decimal addition, we take a decimal data exception between 0 and 5 for the value obtained by adding 6 to the input data, and when we perform decimal subtraction, we take a decimal data exception for the value obtained by converting the input data to 1's complement. The decimal data exception detection circuit is simplified by taking values from 0 to 5.

FIG. 1 is a diagram showing the basic configuration of the present invention, in which 11 is a +6 adder, 12 is a complement circuit, 13 is a selector, 14 is a main adder, 15 is a decimal correction circuit, and 16 is a decimal Data exception detection circuit, A and B are input data, and CARRY is a carry to the lowest digit.

The +6 adder 11 is used during decimal addition and adds 6 to each digit of input data.

The complement circuit 12 is used during decimal subtraction and converts the input data B into a one's complement number.

Selector 13 selects +6 adder 11 during decimal addition.
The output of the complement circuit 12 is selected during decimal subtraction.

The main adder 14 performs binary addition of input data A and input data B to which "6" has been added during decimal addition,
During decimal subtraction, input data A, 1's complemented input data B, and CARRY=1 are added in binary.

The decimal correction circuit 15 performs correction by subtracting "6" from digits in which no digit carry occurs during binary addition in the main adder 14 of decimal addition and decimal subtraction.

The decimal data exception detection circuit 16 performs decimal addition and 10
In both cases of base and subtraction, values from 0 to 5 are detected for the digits of the output data of the selector 13;
When a value of 5 is detected, it is reported as a decimal data exception.

[Effect]

According to the present invention, by simply changing the circuit to move the decimal data exception detection position of input data during decimal subtraction from before to after conversion to one's complement, decimal data exceptions can be detected without almost affecting addition/subtraction operations. The detection method can be unified.

To explain with a specific example, for example, input data is 10
For decimal 4-digit 1B4F, +6 for decimal addition
The adder adds “6” for each digit, resulting in 1B4F +6666 71A5, and the decimal data exception detection circuit converts the digits “1” and “5” into decimal data exceptions 0 to 5. Detected as entering.

Similarly, in the case of decimal subtraction, the input data
1B4F is converted to 1's complement in the complement circuit and becomes E4B0, so the decimal data exception detection circuit detects the digits "4" and "0" as falling into decimal data exceptions 0 to 5. Ru.

These digits refer to digits "B" and "F" in the original input data 1B4F in each case, and it can be seen that the decimal data exception is correctly detected.

〔Example〕

FIG. 2 is a configuration diagram of one embodiment of the present invention,
An example of a 4-digit decimal parallel addition/subtraction circuit is shown.

In the figure, 21 is a +6 adder, 22 is a complement circuit, 23 is a selector, 24 is a main adder, and 25 is a
Decimal correction circuit, 26 is a decimal data exception detection circuit,
27-1 to 27-4 are decoders, 28-1 to 28-4 are OR circuits, and 29 is an OR circuit.

The elements indicated by reference numbers 21 to 26 in FIG. 2 correspond to the elements indicated by reference numbers 11 to 16 in FIG. 1, and perform the same functions. Therefore, the decimal data exception detection circuit 26 will be mainly explained here.

During decimal addition, input data B of 4 decimal digits (4 digits = 16 bits) is incremented by 6 for each digit (digit) in the +6 adder 21, and the result is sent to the main adder via the selector 23. 24 and the decimal data exception detection circuit 26. Also, when doing decimal subtraction,
Input data B is converted into a one's complement number by a complement circuit 22, and is inputted to a main adder 24 and a decimal data exception detection circuit 26 via a selector 23.

The decimal data exception detection circuit 26 performs the same operation in both decimal addition and subtraction.

The decoders 27-1 to 27-4 each receive 4-bit data for each digit as input, and
Values from 0 to 5, i.e. (0000), (0001), (0010),
This circuit generates an output when detecting (001), (0100), and (0101).

The OR circuits 28-1 to 28-4 detect the outputs of the decoders 27-1 to 27-4, respectively, and the OR circuit 29 detects the outputs of the decoders 27-1 to 27-4, respectively.
Detects the output of 8-4 and outputs a decimal data exception detection signal.

Although the circuit of this embodiment is shown for the case of four decimal digits, the present invention can be applied to any n-digit decimal adding/subtracting circuit. It is also obvious that the present invention can be similarly applied to a circuit that uses a serial calculation method instead of a parallel calculation method.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the amount of hardware in the decimal data exception detection circuit without increasing the amount of hardware in the main body of the decimal addition/subtraction circuit, and without degrading the overall performance. This makes it possible to reduce costs and reduce costs.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of the principle of the present invention, FIG. 2 is a diagram of a circuit according to an embodiment of the present invention, and FIG. 3 is a diagram of a conventional circuit. In FIG. 1, 11: +6 adder, 12: complement circuit, 13: selector, 14: main adder, 1
5: Decimal correction circuit, 16: Decimal data exception detection circuit.

Claims (1)

[Scope of Claims] 1. In the decimal addition/subtraction circuit, one input section of the main adder 14 includes a +6 adder 11 that adds 6 to its input data, and a complement that takes the 1's complement of the input data. A decimal converter circuit 12 is provided in parallel and selectably, and further receives the output data of the selected one of the +6 adder 11 and the complement converter circuit 12 as input, and determines a value between 0 and 5 as a decimal data exception. A data exception detection circuit 16 is provided to detect a decimal data exception in the output data of the +6 adder 11 during decimal addition, and to detect a decimal data exception in the output data of the complement circuit 12 during decimal subtraction. Features a decimal data exception detection method in decimal addition/subtraction circuits.