JPH07152537A - Decimal adder and adder/subtractor - Google Patents

Abstract

PURPOSE:To provide a compact decimal adder which serves as the core of a decimal computing unit in an addition table system for each decimal digit. CONSTITUTION:A decimal adder consists of an even number adding circuit 1 which divides each digit of input into an even number component shown in higher 3 bits and an odd number component shown in a single lower bit, adds together even number components as an input, and outputs the lower 3 digit bits of the sum as the even number components and a single carry bit added to a higher order digit as a carry odd component respectively, a 3-input binary addition circuit 2 which outputs higher order bit of the sum as an even number component and a lower order bit of the sum as an odd number component respectively, and an even number-plus-2 addition circuit 3 which adds the even number component received from the circuit 1 or another circuit 3 to the higher order bit of the sum of the circuit 2 and outputs lower 3 digit bits of the sum as the even number components and a single carry bit added to a higher order digit as a carry odd number component respectively. In such a constitution, the circuits 1 are combined in a tournament form for each digit and both circuits 2 and 3 are cascaded together.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a decimal adder (and an adder / subtractor).

[0002]

2. Description of the Related Art Conventionally, a decimal adder is usually realized by a structure in which a correction circuit is added to a binary adder.
In addition, an addition table (FIG. 4A) that embodies an addition table for each decimal digit is indexed (by a logic circuit that obtains a corresponding result) to obtain the sum and carry for each digit. As for the carry, it is conceivable that the carry is transmitted to the upper digit.

The former is 2 in that it uses a binary arithmetic unit.
Although it is convenient to construct a simple decimal arithmetic operation in addition to a decimal arithmetic operation, it is not suitable to configure a decimal arithmetic unit for performing four arithmetic operations of decimal numbers. The latter requires a large number of logic circuits corresponding to the entries in the addition table.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to compactly configure a decimal adder, which is the core of a decimal arithmetic unit, by a method of indexing an addition table for each decimal digit.

[0005]

1 and 2 are block diagrams showing the principle of the present invention. Figure 1 shows 2 inputs 10
It is an example of the configuration of a binary adder, and is expressed mainly by the second digit from the lower order of each operand. For each decimal digit,
Even number adder circuit 1, 3-input binary adder circuit 2, and even number +2
Adder circuit 3 and further 3-input binary adder circuit 2 in the second stage
And an even number + 2 adder circuit 3.

The even-number adder circuit 1 is a circuit that realizes the logic as shown in FIGS. 4B and 5, and adds two even-numbers represented by the upper 3 bits of the BCD code and is also represented by 3 bits. The even number and the carry 1 bit corresponding to the upper digit are output. If one decimal digit is added, it is necessary to realize the logic shown in FIG. 4A, and the number of logic circuits can be reduced as compared with that.

The 3-input binary adder circuit 2 is a circuit that realizes the logic as shown in FIG. 6A, and may be a CSA (Carry Save Adder) used in normal binary addition. this is,
It can also be considered as a circuit that calculates the sum of three numbers that take the values of 1 or 0.

The even +2 adder circuit 3 is a circuit that realizes the logic as shown in FIG. 6B and can be said to be a simple one of the even adder circuit 1. The even number adder circuit 1 adds even numbers represented by the upper 3 bits for each digit of 2 to be added, and outputs the lower 3 bits (even number) as a sum output and the carry output 1 bit to the upper digit. C0u ~ and are output.

The 3-input binary adder circuit 2 adds the lower 1 bit and the carry output C0l of the even-numbered adder circuit of the lower digit for each digit of the two numbers to be added, and the 1-bit of each 1 bit is added. The sum output and the carry output are output.

The even +2 adder circuit 3 adds the lower sum output of the even adder circuit 1 of each digit and the carry output of the 3-input binary adder circuit 2 to the 3 bits representing the even number and the upper digit as a sum output. Carry output 1 bit of C1u to and is output.

Further, the sum output of the preceding three-input binary adder circuit 2 and the two carry C1l and C2l from the lower digit are added by the second-stage three-input binary adder circuit 20 to obtain 1 bit each. The sum output and the carry output of are output.

The second-stage (final-stage) even +2 adder circuit 30 adds the sum output of the preceding even-number +2 adder circuit 3 and the carry output of the second-stage three-input binary adder circuit 20 to obtain the sum. It outputs 3 bits that represent an even number and 1 bit carry output C2u ~ to the upper digit.

3 bits representing the even number of the sum output of the even-numbered + 2 addition circuit 30 in the second stage and the 3-input binary addition circuit 20 in the second stage
The 1-bit sum output is concatenated to form the sum output Z of this digit. The number of decimal numbers to be added can be increased by increasing the number of the aforementioned components. FIG. 2 is an example configured as a 3-input decimal adder that adds three decimal numbers. The even-numbered adder circuits 1 are connected in a two-tournament form according to the number of operands, and are connected in cascade with the 3-input binary adder circuit 2 and the even-numbered +2 adder circuit 3.

The even-numbered +2 adder circuit (30) at the final stage and the 3-input binary adder circuit (20) at the final stage may be integrally configured as a carry look-ahead adder circuit 4 as shown in FIG. Although FIG. 3 shows an example of two inputs, the same configuration can be applied to the case of three or more inputs.

When handling signed operands or subtraction, the following is performed. In addition to the decimal adder described above, the addend of the negative operand and the subtraction of the positive operand are converted into the complements at each input, and the addend of the positive operand and the subtraction of the negative operand are positive numbers. And a post-processing circuit for converting the result to a complement at the output, and the number of operands in the complement expression at the output of the pre-processing circuit and the most significant digit of the decimal adder described above. A decision circuit is provided that takes the difference from the sum of all carry outputs.

The number after conversion by the preprocessing circuit is set to 10 as described above.
Add with a decimal adder. The sign of the final result may be configured such that if the output of the determination circuit is negative, the addition result is passed through the post-processing circuit to make the sign negative, and if the sign is positive, the sign is passed without passing through the post-processing circuit. .

[0017]

Operation: The value of one decimal digit is even + 1 or even + 0
Can be replaced with 4 for BCD code
The upper 3 bits of the bit represent an even number, and the lower 1 bit represents 1 or 0. This is called an even component and an odd component, respectively.

Decimal 1 digit 2 number, X and Y are even components X '
Expressing Y ′ and odd-numbered components x and y (values are 1 or 0), X = X ′ + x, Y = Y ′ + y. The sum is X + Y = (X '+ Y') + (x + y) X '+ Y' = C0u × 10 + Z 0 x + y = z 0.

X '+ Y' is calculated by the even adder circuit 1 to obtain the lower value Z ₀ of the sum and the carry C 0u to the upper digit. Since the sum of the even number and the even number is 16 or less, the lower value Z ₀ of the sum is the even component as it is, and the carry C0u is 1 bit and is the odd component in the upper digit.

X + y and the carry C0l from the lower digit (this is the carry C0u to the upper digit in the lower digit) are added by the 3-input binary adder circuit 2 to obtain the 2-bit value z ₀ . obtain.
This directly corresponds to the lower 2 bits of the decimal 1 digit.
Therefore, this can be separated bit by bit into an even component and an odd component. That is, the upper 1 bit is an even component representing a decimal 2 or 0, and the lower 1 bit is an odd component representing a decimal 1 or 0.

Even component output of even adder circuit 1 and 3 inputs 2
When the output of the even-numbered component of the binary adder circuit 2 is added by the even +2 adder circuit 3, the sum of the even-numbered components and the carry of the odd-numbered component to the upper digit are similarly obtained.

Even adder circuit 1 and 3 inputs 2 as constituent elements
Both the decimal addition circuit 2 and the even +2 addition circuit 3 can be realized as a simple logic circuit. Since the carry may ripple propagate in the final stage, if the even-numbered +2 adder circuit 30 in the final stage and the 3-input binary adder circuit 20 in the final stage are integrally configured as the carry look-ahead adder circuit 4, high speed is achieved. Can be converted.

It is obvious that when a signed operand is handled, or when it is configured as a subtracter, it can be processed by converting a negative operand or a subtraction into a complement and inputting it to an adder.

Considering the sign of the result, it is a little complicated in the case of multiple inputs. The case of three inputs will be described below. Let A, B, and C be the three numbers of inputs. For convenience of explanation, these are single digit numbers. Alternatively, it may be considered that the representative is represented by the highest digit. 1) One of the three numbers (C) is negative.

When the carry from the highest rank is 1 or more. A + B + (10−C) ≧ 10 A + B ≧ C Therefore, the result is positive.

When there is no carry from the highest rank. A + B + (10-C) <10 A + B <C Therefore, the result is negative. 2) Of the three numbers, two (B, C) are negative.

When the highest carry is 2 or more. A + (10−B) + (10−C) ≧ 20 A ≧ B + C Therefore, the result is positive.

When the most significant carry is 1 or less. A + (10-B) + (10-C) <20 A <B + C Therefore, the result is negative. 3) When all three numbers are positive or zero. The result is positive, A + B + C ≧ 0, regardless of carry from the top. 4) When all 3 numbers are negative. The result is negative, A + B + C <9 + 9 + 9 <30 Therefore, the carry from the most significant digit is 2 or less.

The above can be summarized as the result is negative when the number of negative numbers in the operand is greater than the value of the carry output from the most significant digit. The same applies to the case of two inputs, and it can be easily expanded to the case of four or more inputs, and the same can be said.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 shows an embodiment of a 2-input decimal adder. In order to increase the speed, the carry look-ahead addition circuit 4 is provided at the final stage. Others are the same as those described in the section of means for solving the problem. FIG. 7 is an explanatory diagram showing an example of the calculation. Description will be given below with reference to FIGS.

Addend X = 9999999 and addend Y = 99
88777 is added. Each of X and Y is separated into an upper-order 3-bit even component and a lower-order 1-bit odd component. That is, 8888888
+1111111 and 8888666 + 1100111. The even-numbered component is added by the even-numbered addition circuit 1 and the sum of one digit for each digit Z0 = 66666444 and carry C0 = 1111111.
And get (· is 0). The two odd-numbered components of the input and the carry C0 of the output of the even-numbered addition circuit 1 are added by the 3-input binary addition circuit 2 to obtain the even-numbered component 0.
2222222 and the odd component 11100110 are obtained. The even number +2 addition circuit 3 adds Z0 = 66666644 and the even number component 0222222 to obtain the sum Z1 = 88886.
66 and carry C1 = 0000000. By the final stage adder circuit (carry lookahead adder circuit) 4,
Output sum Z1 = 8888666 and carry C1 = 00000
The output 00 and the odd component 11100110 of the output are added to obtain the final sum Z = 19988776.

The carry of each digit to the higher order is the sum of
When each digit of Z1 is '8'(`1000'B in binary), it can be easily generated by the most significant 1 bit of each digit of Z1 and carry C1 and each 1 bit of odd component. it can.

FIG. 8 shows a similar example. This is an example in which carry output is actually output at the third and sixth digits from the bottom of the figure. 9 and 10 show examples of subtraction using the decimal adder of the present invention.

The subtraction is converted to 9's complement by the complement circuit (a). Finally, if there is a carry output from the most significant digit, 1 is added to the least significant digit to correct it. Then, a complement circuit may be added so as to obtain the “difference” of the final result (b).

According to the present invention, it is easy to construct an adder having three or more inputs, and the final stage of the basic configuration example of the three-input decimal adder shown in FIG. Circuits and lines will be practical. Similarly, it is easy to expand to more than 4 inputs.

[0036]

As described above, according to the present invention, a decimal adder can be realized with a simple combination of functional circuits, and it can be easily expanded to a decimal adder having three or more inputs. . In addition to the decimal subtractor, it becomes easy to use it as the core of an arithmetic unit that performs decimal operations such as multiplication, division, and binary-decimal conversion.

[Brief description of drawings]

FIG. 1 is a configuration example of a 2-input decimal adder.

FIG. 2 is a configuration example of a 3-input decimal adder.

[FIG. 3] Example in which a carry-look-ahead adder is used at the final stage

FIG. 4 Function of adder circuit for 1 digit in decimal and 1 digit in decimal

[Figure 5] Lower digit (sum) output and upper digit (carry) output of the even number addition circuit

FIG. 6 Functions of 3-input binary adder circuit and even +2 adder circuit

FIG. 7 Addition example 1

FIG. 8 Addition example 2

FIG. 9 Subtraction example 1

FIG. 10 Subtraction example 2

[Explanation of symbols]

 1 even number adder circuit 2 3 input binary adder circuit 3 even number +2 adder circuit 20 final stage 3 input binary adder circuit 30 final stage even number +2 adder circuit 4 carry carry lookahead adder circuit

Claims (3)

[Claims] 1. An adder for adding a decimal number represented by a BCD code, wherein each digit of an operand is separated into an even component represented by upper 3 bits and an odd component represented by lower 1 bit, and 2. Two even-numbered components are added as input, the lower 3 bits of the sum are set as an even-numbered component, and one bit of carry to the upper-order digit is output as a carry-odd component. A three-input binary addition circuit (2) that adds three carry odd components from the digits as inputs, outputs the upper bit of the sum as the least significant bit of the even component, and outputs the lower bit of the sum as the odd component, Even adder circuit (1) or other even +2 adder circuit (3)
The even-numbered component from and the upper bit of the sum of the 3-input binary adder circuit (2) are regarded as the least significant bit of the even-numbered component and added, and the lower 3 bits of the sum are set as the even-numbered component and carry to the upper digit. For each digit, the even-numbered addition circuit (1) is combined in a tournament formula to add the even-numbered component of the input to 1 One even component is obtained and the carry odd component generated in the middle is sent to the upper digit, and the 3-input binary adder circuit (2) is connected in cascade to input and generate the odd component and the digit from the lower digit. Add up three odd-numbered components in combination and add the even-numbered +2 addition circuit (3) in a cascade connection to obtain an even-numbered component obtained at the final stage of the even-numbered addition circuit (1) or another even-numbered +2 addition circuit (3). Output even component and 3 inputs Add the odd component of the output of the binary adder circuit (2), carry the final carry of the even +2 adder circuit (3), send the output of the odd component to the upper digit, and add the final component of the even +2 adder circuit (3). A decimal adder characterized in that an even-numbered component output and an odd-numbered component output at the final stage of the 3-input binary addition circuit (2) are connected to obtain a sum output of this digit. 2. The output of the even +2 adder circuit (3) at the previous stage and the 3-input binary at the previous stage instead of the even +2 adder circuit (3) at the final stage and the 3-input binary adder circuit (2) at the final stage. A carry look-ahead addition circuit for adding the odd component of the adder circuit (2) and the carry from all the lower digits to produce a sum output of this digit and a carry output to the upper digit is provided. The decimal adder according to claim 1. 3. When handling signed operands or performing subtraction, in addition to the decimal adder according to any one of claims 1 to 3, the adder of the negative operand and the positive operand A pre-processing circuit is provided to convert a subtraction to a complement and to convert a positive operand addend and a negative operand subtraction to a positive number, and to provide a post-processing circuit for converting a result to a complement at the output. The number of operands in the complement representation in the output of
A decision circuit that takes the difference from the sum of all carry outputs of the most significant digit of the decimal adder is provided, the number after conversion by the preprocessing circuit is added by the decimal adder, and the sign of the final result is If the output of the determination circuit is negative,
A decimal adder / subtractor characterized in that the addition result is passed through a post-processing circuit to make the sign negative, and if the addition result is positive, the sign is made positive without passing through the post-processing circuit.