JPS63311433A - Binary redundant sd code converting/subtracting method and its circuit - Google Patents

Abstract

PURPOSE:To ensure the working of the titled method at a high speed by performing the binary redundant subtraction for the highest level digits 1 and 0 of the value shown in a complement code of 2 after adding the binary redundant SD codes +1 and -1 to the digit higher than the highest level digit by one step. CONSTITUTION:In case all digits of the value (= u) shown in normal complement series code of 2 are equal to 0, they are replaced with -1 and then with +1 if they are equal to 1 respectively. For the digit higher than the highest level digit by one step, +1 and -1 are added if the highest level digit of the unconverted complement series code of 2 is equal to 0 and 1 respectively. Thus it is possible to obtain the value (v) shown in a deformed binary redundant SD code having a larger digit number by an amount equal to a single digit. Such a deformed binary redundant SD code is used for execution of the binary redundant subtraction. Thus each digit is converted into a binary redundant SD code consisting of only +1 and -1 excluding 0.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention converts a commonly used two's complement code into a binary redundant SD code used in high-speed adders/subtracters, etc. The present invention relates to a conversion circuit suitable for performing subtraction of two numbers of binary SD redundant codes at high speed with a small circuit configuration.

[Conventional technology]

(b) Addition Redundant An adder using SD Coco can perform parallel addition without carry propagation when performing addition, and can perform addition in a fixed time that does not depend on the addition value (addend and summand). It has the characteristic that it can be done.

That is, an adder using a binary redundant SD code performs addition without causing carry propagation by the following two-step operation.

■ In the first stage, intermediate results such as an intermediate carry and an intermediate sum are generated so that the carry from the lower digit can be absorbed by the relevant digit, but these values are set according to the status of the lower digit.

■ In the second stage, the intermediate carry resulting from the lower digit and the intermediate phase of the digit are added, resulting in the final addition result.

At this time, carry propagation from lower to higher does not occur, so
High-speed addition independent of word length can be achieved.

It has the feature that the above two-stage operation can be executed in parallel for each relevant digit. To generate the above intermediate sum and intermediate carry, a signal (=C
) is required.

This signal C looks at the value of the adjacent lower digit, and if +1 cannot occur as a carry from the lower digit (indicates c=1), and if -1 cannot occur (indicates C=O) Detect. Then, in response to this carry prediction signal, an intermediate carry and an intermediate sum are generated.

This carry prediction signal C is generated according to the rules shown in FIG. 2, which shows the rules for adding each digit from the carry prediction signal. That is, at least either the addend or the summand is -
In the case of 1, a carry of +1 can never occur by adding the sum of the addend and summand of the digit, so c=l, and for other combinations of addend and summand, -1
Since a carry can never occur, C=0, indicating that this is sent to the adjacent upper digit. Note that φ(do
n' t care) indicates that the carry prediction signal from the adjacent lower order may be either 1.0. In other words, if the sum of the addend and summand of the relevant digit is 0 (when the combination of the addend and summand is O and 0, +1 and -1, -1 and +1), the digits from the lower order Since carry propagation does not occur regardless of the carry, both the intermediate carry and the intermediate sum are set to 0. For details, please refer to Japanese Patent Application No. 61-46598 (Japanese Patent Application No. Sho 61-46598) and T.
.

NAKANISHI etal, “CMO3Radi
x-2Signed-DigitANo, 4 Apr
See il.

When an arithmetic unit based on a binary redundant SD code is configured with a binary logic circuit, each digit must be expressed as a binary code of 0 and l, but it is not possible to express it as a ternary code of O, +1°, and -1. Each digit of the binary redundant code is represented by two bits: the S bit (sign) indicating whether it is positive or negative, and the V bit (value) indicating whether it is 0 or not. The redundant sD code is expressed as shown in the diagram showing the binary encoding method. Each bit is a binary code consisting of 0 and 1, and 0 in the binary redundant SD code is (φ, 1), +1 is (0, 0),
-1 is represented as (1,0). In the following encoding, the bit indicating whether it is positive or negative is called the S bit, the bit indicating whether it is 0 or not is called the V bit, and this code is called Sv Coco.

Now, in the commonly used two's complement system code, when the most significant digit is 0, it represents positive or zero, and when it is l, it represents negative.

Therefore, when converting a conventional two's complement code to a binary redundant code, if the most significant digit is 0, it is converted to 0 as it is,
If it is 1, replace it with -l, and for all other digits, if it is 0 or l, it will remain as 0.
Or it is replaced with +1.

Figure 9(a) shows the conventional binary redundant S from two's complement code.
An example of code conversion to D code is shown.

The circuit that realizes the addition rule in Figure 2 is shown in Figure 4 (a), a circuit diagram of a conventional binary redundant SD code adder with one digit. It is converted into a binary redundant code by Sv Coco by the conversion method and the summand 1. The addend is 2, and after passing through several logical stages,
The intermediate sum 3 and the inverse of the intermediate carry 4 between the adjacent upper and lower digits are output.

(b) In the subtractive binary redundant SD code, the value whose sign is inverted (that is, multiplied by -1) is equal to the value where the sign of each digit is inverted. Therefore, the subtraction rule shown in FIG. 3 can be obtained from the addition rule shown in FIG. 2 by reversing the sign of the addend in addition to obtain a subtracted number, and using the summand as it is as the minuend.

That is, a circuit that realizes FIG. 3, which is a diagram showing the rules for subtracting each digit from a carry prediction signal, is shown as a circuit with a single digit subtracter in FIG. 4(b). (See References) Compared to the adder circuit of FIG. 4(a), the subtraction circuit of FIG. 4('b) differs in that it is provided with an inverter 5 for inverting the sign of the addend.

Figure 5 shows the minuend of the conventional two's complement code and the two
Figure 5 is an example of a binary redundant SD code conversion subtraction circuit between the subtraction of a complement system code.
A code conversion subtraction circuit diagram is shown. Two two's complement code numbers p.

Convert q into a binary redundant SD code and express it as Sv Coco according to the encoding method shown in Figure 6 as the subtrahend and minuend,
Subtraction S of two numbers p and q expressed in two's complement code
It constitutes a circuit that performs D redundant subtraction (p-q). In the same figure, 4 is an intermediate carry related to adjacent digits, and 5 is a subtractor in FIG. 4 (bl).

[Problem that the invention seeks to solve]

The circuit diagrams in Figure 4 all require several logic stages and must be composed of logic circuits and switching circuits between them, so a considerable number of elements are required to realize this as a circuit. shall be. The cause of this is the summand and addend of the binary redundant SD code in Figures 2 and 3.

The minuend, tJ & number is +1. There are three values, -1 and 0,
In Figure 2, it is clear that the logic becomes complicated when either the summand or the addend is 0, and this is the reason for the fourth
This is the reason why the circuit in Figure (a) is complicated. Therefore, each digit is +1 without an O. -Binary redundancy S consisting only of 1s
A method of converting to D code is desired.

[Means for solving problems]

When converting a two's complement code into a binary redundant SD code, the present invention replaces it with a modified binary SD redundant representation consisting only of +1 and -1 digits, and uses the obtained modified binary redundant SD code. This achieves high-speed SD redundant subtraction in which each digit is operated in complete parallel using a small-scale circuit.

That is, for all digits of the value (=u) expressed by the normal two's complement code, if the code is 0, it is replaced with -1, and if it is 1, it is replaced with +1. Then, as the digit one above the most significant digit, if the most significant digit of the two's complement code before conversion is 0, +1 is added, and if it is 1, -1 is added, so that only one digit is added. A value (V) expressed by a modified binary redundant SD code with a large number of digits is generated.

Then, binary redundancy subtraction is performed using the modified binary redundant SD code generated in this way. An example of code conversion from a 2's complement system code to a modified binary redundant SD code is shown in Fig. 9 (mountain).

[For production]

The diagram showing the modified binary redundant SD rule obtained by the method according to the present invention is as shown in Figure 1, which shows the subtraction rule using the modified binary redundant SD code of the present invention, and is a combination of intermediate carry and intermediate sum. This will generate a simplified subtraction rule in which there is only one way.

Regarding the binary redundant SD code V obtained by the method according to the present invention and the two's complement code before conversion, v=2·u+1 holds true.

(Example 7 = 2・3+1.-9=2・(-5)+1) In binary SD redundant operation, intermediate values (intermediate carry and intermediate sum) generated to absorb carry propagation are used. , the calculated value is obtained by adding the intermediate sum of each digit and the intermediate carry from the adjacent lower digit.

As is clear from Fig. 1, if each digit of the subtrahend S or minuend r consists of only +1 or -1, the intermediate sum is always 0, so the subtraction value required by the problem digit (
The sum of the intermediate carry from the adjacent lower order and the intermediate sum) is the intermediate carry from the adjacent lower order itself. Furthermore, since there is no intermediate carry from the adjacent lower order in the least significant digit, the least significant digit of the subtraction value to be obtained is always 0.

On the other hand, in the subtraction method of the modified binary redundant SD code according to the present invention, two values p of two's complement code are used.

Replace each of q with a modified binary redundant SD code, and perform redundant SD subtraction with S as the minuend and the subtrahend, and the resulting two modified binary redundant SD code values are as follows: r-s= (2-p+1) (2・q+1)=2・
(p-q), and the subtraction result is equal to twice the subtraction value in the value expressed by the two's complement code before conversion.

Similar to the value expressed using the normal 2's complement system code, when the least significant digit is 0 in the value expressed using the binary redundant SD code, the subtraction value of r and 3 is calculated by dividing the value by 2. is obtained as the intermediate carry itself from the adjacent lower order, so
It is clear that by dividing this by 2 to obtain p-q, it is sufficient to simply return the intermediate carry from the adjacent lower order to the adjacent lower order, that is, use the own intermediate carry.

From the above, by using the method according to the present invention, each of the values p and q of the two two's complement code is replaced with a modified binary redundant SD code, and the resulting value r of the two modified binary redundant SD codes is
, s as the minuend and the subtrahend and generate an intermediate carry, which is one of the intermediate values, to obtain the subtraction result of p and q by the conventional binary redundant SD operation.

When subtracting r and 3, follow the rules in Figure 1 for each digit. If the signs of the minuend and the subtrahend are different, the minuend is used as an intermediate carry to generate the same value, and if the signs of the minuend and the subtrahend are the same, the value is generated as is. This can be done by generating 0 as an intermediate carry.

〔Example〕

FIG. 7 shows a circuit diagram of an embodiment of one index of the modified binary redundant SD code conversion/subtraction circuit of the present invention, and FIG. Transformation 2
A correspondence diagram before and after conversion of SV Coco to a value expressed in a hexadecimal redundant SD code is shown.

When converting a two's complement code to a binary redundant code, the lowest digit 0 of the normally used two's complement code is
represents positive or zero, and 1 represents negative, so the binary redundant SD code is expressed as 2 bits of S%V.
■When performing binary encoding with Coco, it is summarized in Figure 1θ.

Each digit of the value expressed in two's complement code is transformed into binary redundant S.
For each digit, the two's complement code before conversion is S.

If you use the 2-bit binary encoding method (2), the first
Regarding the operation of the present invention shown in the figure, it is only necessary to use the intermediate carry itself of the relevant digit as the subtraction result, so the S bit of 0 of the binary redundant SD code is used as the S bit of the intermediate carry of the circuit of the present invention. When φ is 1 and l is -1, the sign of the minuend may be used as it is, since it is sufficient to use the minuend from FIG.

If the signs of the minuend and subtrahend (corresponding to the S bit) are the same, a 1 (V bit of 0 in the binary redundant SD code) is generated for the V bit of the intermediate carry, and if they are different, a 0 (binary redundant code) is generated. (+1 to -1 V bit) of the SD code.

That is, an exclusive-NOR operation is performed on the S bits after converting the minuend into a binary redundant SD code and the S bits after converting the subtrahend into a binary redundant SD code.

As shown in Figure 1O, when the sign digit is positive, zero or negative, 0 or 1 before conversion becomes +1°-1 after conversion,
Corresponds to S bits 0 and 1.

FIG. 7 is a circuit diagram for one digit of the modified redundant SD code conversion/subtraction circuit according to the present invention. 11 is the input of the most significant digit of the minuend p and subtrahend q in the representation of the two's complement code, and 12 is the input of the most significant digit, excluding the most significant digit. The input of each digit, 13, is the input of the equivalent circuit shown in FIG. 3(b). 21 is the output of a circuit added to the adjacent upper order of the most significant digit of the modified binary redundant SD code, 22 is the output of each digit, and 23 is the output of the equivalent circuit shown in FIG.

Figure 7(a) is a circuit added to the adjacent higher order of the most significant digit,
V
, and the minuend Pn is set as 8□1 of the output 21.

In FIGS. 7-), the negation of the minuend Pi and the subtrahend Qi of the input 12 is input to an exclusive OR negation circuit.

FIG. 7(C) is a circuit obtained by performing equivalent logic conversion of the circuit shown in FIG.

FIG. 8 is a multi-digit example of the subtraction circuit of the present invention using the circuit for one digit of the present invention as an arithmetic circuit. 4 is an intermediate carry signal between adjacent digits, 33 is the circuit in FIG. 7(a) that is added to the adjacent uppermost digit of the most significant digit, and 34.35 is each digit except the most significant digit in FIG. 7(C). This circuit is an equivalent logic conversion of the circuit added to the circuit. Further, P is the minuend and Q is the subtrahend, both of which are values expressed in two's complement code.

For example, when p=q, the value is expressed by a binary redundant SD code. r=s, the intermediate carry is 0 from FIG. 1, and S=φ, ■=1 from FIG. Figure 7(a)
(b) All of the circuits of the present invention shown in (C) satisfy this relationship.

Using the binary encoding method of the modified binary redundant SD code shown in FIG. The numerical values r and s of the modified binary redundant SD code are used as the minuend and the subtrahend, and a circuit for performing SD redundant subtraction is constructed, which corresponds to the conventional circuit shown in FIG. 4(b).

Comparing both the circuits of FIG. 5 and FIG. 8, the circuit configuration of FIG. 8 according to the present invention can significantly reduce the circuit scale,
It is clear that when operated at the same speed, power consumption can be significantly reduced by reducing the number of elements. In addition, it is clear that higher-speed operation is possible because the number of logic stages has been significantly reduced.

From the above, it can be said that the method according to the present invention is superior to the conventional method in terms of circuit configuration scale, operating speed, power consumption, etc.

〔Effect of the invention〕

The present invention is a modification of the commonly used two's complement system code.
A method and implementation of modified binary redundant SD code conversion and subtraction that enables a smaller circuit configuration, lower power consumption, and faster operation when converting to a binary redundant SD code. The objective is to provide a circuit that

For example, a circuit constructed by the method of the present invention and a binary S
By combining circuits that determine whether the D redundant code is positive or negative, a magnitude comparison circuit using redundant binary operation of two numerical values can operate at higher speed, be smaller in size, or consume less power.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the subtraction rule using the modified binary redundant SD code of the present invention, Fig. 2 is a diagram showing the subtraction rule using the modified binary redundant SD code, Fig. 2 is a diagram showing the adder and subtractor using the conventional binary redundant SD code, and Fig. 5 is the conventional subtraction rule using the modified binary redundant SD code. Figure 6 is a binary redundant SD code conversion/subtraction circuit diagram based on the system.
FIG. 7 is a circuit diagram for one digit of a modified binary redundant SD code conversion/subtraction circuit according to the present invention, and FIG. 8 is a diagram showing a binary redundant SD code encoding method using binary 2 bits. A multi-digit circuit diagram of the SD code conversion subtraction circuit, FIG. 9 is a code conversion diagram, and FIG. 10 is a conversion correspondence diagram of SV Coco. ■... Addend 2... Addend 3... Intermediate sum 4... Intermediate carry signal between adjacent digits 5... Subtractor with binary SD redundancy 11.12.13...・Input of two's complement code 21.2
2.23... Output of modified binary redundant SD code 31.32... Inverter 33... Negation of exclusive OR exc lus 1ve-
NOR circuit 34...Circuit 35 added to the adjacent higher order of the most significant digit...
・Circuit S that performed equivalent logic conversion of intermediate digits...S pip)
(sign) Modified binary redundant SD code V ・V bit (value) Modified binary redundant SD code P... Minuend Two's complement code Q... Subtractive two's complement code N Whistle showing subtraction rules using two-way redundant SD code when none of the numbers contain 0 1
+lfQ from the adjacent lower order in Figure C-, if a carry does not occur c-o: If a carry of -1 cannot occur in the lower order of M, each digit from the carry prediction signal by the two-way redundant SO code Figure 2 shows the addition rule for Figure C-1 = Middle 1st digit from the adjacent adjacent position (if f is long enough to occur, c-o: -1 digit digit occurs from ps search down) Figure 3 (a) shows the rules for subtracting each digit from the carry prediction signal using the 2-way redundant SD code in the case of y! (-) 2-way redundant asD code jllll141 digit el!
Example of constructing a structure with the button calculation carving shown in Figure 2) Mouth 1 (b) Example of 2-way redundant iso code original calculator 1 digit constructed with the subtraction standard shown in Figure 3 Follow yR2Xt7i1' long SD hood Total addition! and subtractor circuit port 'M 4 Complement system code in Figure 2 Conventional 2-way redundant SD code 2's complement system code Modified 2-way redundant SD
Code (b) Code Watari Diagram Figure 9 S ■ Coco Conversion Correspondence Diagram Figure 10

Claims (2)

[Claims] (1) 2's complement code, each digit is 0, +1, -1.
In a method of converting to a binary redundant SD code expressed as a value and performing calculations, 1 of each digit of the value expressed as a two's complement code is used.
．． 0 is converted to +1 and -1 in binary redundant SD code, respectively, and 1.0 is the most significant digit of the value expressed in two's complement code.
For the above, there is a method of adding +1 and -1 of the binary redundant SD code to the digit one above the most significant digit to create a modified binary redundant SD code, and a method of adding +1 and -1 of the binary redundant SD code to a modified binary redundant SD code, and
A binary redundant SD code conversion and subtraction method, comprising: a circuit that performs a binary redundant subtraction. (2) 2's complement code, each digit is 0, +1, -1.
In a circuit that converts into a binary redundant SD code expressed as a value and performs an operation, the 1 of each digit of the value expressed as a two's complement code is
．． Converts 0 to +1 and -1 of the binary redundant SD code, respectively, and converts +1 and -1 of the binary redundant SD code to the most significant digit of 1 and 0 of the value expressed in two's complement code, respectively. 2, characterized in that it is comprised of a circuit that adds to the digit one above the digit to create a modified binary redundant SD code, and a circuit that performs binary redundant subtraction using the modified binary redundant SD code.
Hexadecimal redundancy SD code conversion subtraction circuit.