JP2002014804A - Ternary digital circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an arithmetic circuit capable of reducing the propagation of a carry signal with a relatively simple constitution. SOLUTION: Two data A and B corresponding to ternary digital data expressed as the combination of binary digital data are added by this following expression (A+, A-)+(B+, B-), and A++B+ is calculated by a first full adder 1, and A-+B- is calculated by a second full adder, and the result is inputted to a compensating circuit 3, and only when arithmetic outputs Sum+, Sum- of the first and second full adders 1 and 2 are both made equivalent to a logical value High, the final outputs Sum+, Sum- are both turned into a logical value Low, and in the other case, the final outputs Sum+, Sum- are made matched with the arithmetic outputs Sum+, Sum- of the first and second full adders 1 and 2 by the compensating circuit 3. Thus, it is possible to obtain the arithmetic result of the ternary digital data based on a prescribed rule.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital data addition and subtraction processing, and more particularly, to an encoding method and an arithmetic circuit for speeding up the processing.

[0002]

2. Description of the Related Art An adder / subtracter for performing addition / subtraction of digital data is often used in various digital signal processing circuits.
As shown in FIG. 11, a so-called full adder (referred to as "FA" in FIG. 11) is connected in multiple stages according to the required number of bits. It is well known.

[0003]

This ripple carry type parallel adder circuit has a simple structure, but as the number of bits to be handled increases, a so-called carry signal ("C '" or "C'" in FIG. 11). Propagation time of a signal at a portion denoted by "C" increases, and therefore, it takes time until the arithmetic processing is completed, and there is a disadvantage in that it is not possible to meet a demand for a high-speed circuit. As a circuit for solving such a drawback of the ripple carry type parallel addition circuit, for example, a carry look-ahead (CLA) type addition circuit as shown in FIG. 12 has been proposed, which is publicly known. That is, such a carry look-ahead type adder circuit is provided with a circuit for processing a carry signal called a carry look ahead (Carry look ahead) circuit to reduce the number of processing bits as in the ripple carry type parallel adder circuit. The inconvenience of increasing the carry time of the carry signal due to the increase can be avoided. However, the circuit configuration becomes more complicated than the ripple carry type parallel addition circuit,
Since the number of gates is large, there is a disadvantage that it is unsuitable especially for a digital signal processing device which can be integrated. In addition, carry-save-type adders, forresley-type adders, and the like are known and well-known as adders that achieve higher speeds than the ripple carry-type parallel adder, but all have complicated configurations. It has a large number of gates and has the same drawbacks as the carry look-ahead adder circuit.

SUMMARY OF THE INVENTION The present invention has been made in view of the above situation, and uses a conventional binary logic element, has a relatively simple configuration, and can transmit a so-called carry signal. An object of the present invention is to provide a ternary digital circuit capable of performing calculations. Another object of the present invention is to provide an encoding method for encoding a binary digital signal into a code that requires less carry propagation in an operation, and an encoding method for converting the encoded data to an original binary digital signal. An object of the present invention is to provide a decoding method for easily decoding a signal and a circuit suitable for the encoding and decoding.

[0005]

The object of the present invention is achieved.
Therefore, the ternary digital circuit according to the present invention
-1 of digital data is (0,1) and ternary digital
Data 0 is (0,0), and ternary digital data +
1 is the combination of (1,0) and binary digital data
Basically, ternary digital data is expressed as
(First encoded bit string, second encoded bit string) and table
On the premise that it is represented by two ternary digital data
The binary digital data based on the corresponding notation
The first and second encoded bit strings of each of the
, And the binary digital data A is (A
m-1⁺Am-2⁺... A0⁺, Am-1⁻Am-2⁻... A
0⁻), The binary digital data B is (Bm-1⁺Bm-2
⁺... B0⁺, Bm-1 ⁻Bm-2⁻... B0⁻Place)
The sum of these two binary digital data
(Am-1⁺Am-2⁺... A0⁺, Am-1⁻Am-2⁻...
A0⁻) + (Bm-1⁺Bm-2⁺... B0⁺, Bm-1⁻Bm-2
⁻... B0⁻) To each of the first encoded bit strings
Of the corresponding bits, and the second
The addition operation of corresponding bits of a plurality of bit strings is
Respectively, and the binary data
Combining digital data with the two binary
To perform an operation that is the result of adding data A and B
The ternary digital circuit of
Predetermined bits of the first and second encoded bit strings of data A
Bit combination at position α (Aα⁺, Aα⁻)
And the predetermined bit in the binary digital data B.
1 bit combination at the bit position α (Bα ⁺, B
α⁻The unit bit processing unit that performs the addition process of
The unit bit processing unit.
Has two input terminals, one carry input terminal and one
Operation output terminal and one carry output terminal.
A first full adder, two input terminals and one carry
Input terminal, one operation output terminal, one carry output
A second full adder having a terminal and two input terminals
And two output terminals, one of which is connected to the first
To the operation output terminal of the full adder, and the other input terminal
Respectively connected to the operation output terminal of the second full adder,
Logic is applied to both the operation output terminals of the first and second full adders.
The two output terminals only when the value High is output.
Outputs a logical value Low, while the first and second logical values
Of the full adder have a logical value other than High
State, one output terminal is connected to the first full adder.
The output state is the same as the output state of the operation output terminal of the arithmetic unit.
The other output terminal is an operation output terminal of the second full adder.
Output state is the same as the output state of
The binary digital data.
Of a unit bit processing unit that processes the least significant bit of
The carry input terminal of the second full adder has a logical low state.
While the unit bit processing unit
The carry output terminal of the full adder of 1 corresponds to the upper bit.
Carry input terminal of the first full adder of the unit bit processing unit
The digit of the second full adder of each unit bit processing unit
The rising output terminal processes unit bits corresponding to the upper bits.
Connected to the carry input terminal of the first full adder of the section
One output of each of the unit bit processing units
The output data obtained at each pin is
Are sequentially arranged to form a first bit string, and each of the unit bits is
Output data obtained at the other output terminal of the
Are sequentially arranged from the most significant bit side to form a second bit string.
Is represented as (first bit string, second bit string)
Is the combination of the two binary digital data A and B.
It is configured to be a result of addition.

In such a configuration, the ternary digital signal is configured to be expressed by a combination of the binary digital signals and can be used for the operation. An arithmetic circuit having a simple configuration and requiring less propagation of a so-called carry signal can be provided.

Further, in order to achieve the object of the present invention, the encoding method according to the present invention converts a positive binary digital data into a (first encoded bit sequence, a second encoded bit sequence)
Wherein the binary digital data is shifted by one bit to the most significant bit side and zero is added to the least significant bit to form a new first digital data. A bit string is obtained and set as (first bit string, 0), while the bit string of the binary digital data is set as a second bit string, and set as (0, second bit string). 0) + (0, second bit string) is performed based on a predetermined calculation rule, and the result of the addition is defined as (first coded bit string, second coded bit string). The operation rule is that, for each bit of the (first bit string, 0) + (0, second bit string), (0,0) + (0,0)
The result of the operation is (0,0) and the carry is (0,0).
In the case of (0,0) + (1,0), the operation result is (1,0), and the carry is (0,0).
In the case of (0,0) + (0,1), the calculation result is (0,0)
1), and carry (0, 0), (1,
In the case of (0) + (1,0), the operation result is (0,0), the carry is (1,0), and the data resulting from the carry is added to the addition operation of the upper bits,
In the case of (0,1) + (0,1), the calculation result is (0,1).
0), the carry is (0, 1), the data generated by the carry is added to the addition operation of the upper bits, and in the case of (1, 0) + (0, 1), the operation result is (0, 0) and carry (0, 0).

In this encoding method, the conventional binary digital data is converted into a representation of a combination of two sets of binary digital data, so that it can be operated by the ternary digital circuit according to the first invention. The transmission of a carry signal can be reduced as compared with the case where a calculation is performed using conventional binary digital data, thereby enabling more efficient data processing.

Further, in order to achieve the object of the present invention, a decoding method according to the present invention provides encoded data (a first encoded bit sequence, a second encoded bit sequence) obtained by the encoding method according to claim 3. Is a decoding method for decoding the coded bit string into the original binary digital data, in which each bit of the first coded bit string is inverted, and the result is set as a first bit string, The first bit string, 0), the addition of (the first bit string, 0) + (0, the second coded bit string) is performed based on a predetermined calculation rule, and the result of the calculation is (first 2), and the first coded bit string is shifted to the most significant bit side by 1
In addition to shifting the bits, 1 is added to the least significant bit to obtain a new third bit sequence, which is then referred to as (third bit sequence,
0), and the (second bit string, 0) + the (third bit string).
The addition operation of the bit sequence (0) is performed based on the above operation rules, and the result of the operation is obtained (decoded bit sequence,
0) is the decoded binary digital data, while the predetermined operation rule is that if each bit of the operation target is (0,0) + (0,0), the operation The result is (0,0) and the carry is (0,0).
0) and (0,0) + (1,0), the operation result is (1,0), the carry is (0,0), and (0,0) + (0,0) In the case of 1), the calculation result is (0, 1), and the carry is (0, 0).
In the case of (1,0) + (1,0), the operation result is (0,
0), the carry is (1, 0), and the data resulting from the carry is added to the addition operation of the upper bits. In the case of (0, 1) + (0, 1), the operation result is (0,0) and carry (0,1),
The data generated by the carry is added to the addition operation of the upper bits. In the case of (1, 0) + (0, 1), the result of the operation is (0, 0) and the carry is (0, 0). ).

In this decoding method, the data previously encoded by the encoding method according to the present invention can be decoded into the original binary digital data by a relatively simple procedure as desired. Yes, it is possible to easily use the encoded data by the encoding method according to the present invention and the original binary digital data as desired.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. The members, arrangements, and the like described below do not limit the present invention, and can be variously modified within the scope of the present invention. First, a circuit configuration of a basic ternary digital circuit according to an embodiment of the present invention will be described with reference to FIG. The ternary digital circuit is roughly divided into a first and a second full adder (both are denoted by "FA" in FIG. 1) 1 and 2 and a correction circuit 3. And has a function of performing an addition process on a combination (Aα ⁺ , Aα ⁻ ) of one-bit binary digital data and (Bα ⁺ , Bα ⁻ ). The ternary digital circuit shown in FIG. 1 serves as a unit bit processing unit in a multi-bit ternary digital circuit as described later. First and second full adders 1 and 2
Have the same configuration as that of a known / known full adder. The first and second full adders 1 and 2 shown in FIG. 1 are for 1-bit operation, have one input terminal X and the other input terminal Y, and have a carry input terminal C. ing. The first and second full adders 1 and 2 are connected to the input terminals X and Y and the carry input terminal C, respectively.
And a calculation output terminal S for outputting the calculation result of the sum of the numbers respectively input to the input terminal and a carry output terminal C ′. The operation output terminal S of the first full adder 1 is connected to one input terminal of a correction circuit 3 described below, and the operation output terminal S of the second full adder 2 is connected to the other input terminal of the correction circuit 3. Each is connected to an input terminal. In the embodiment of the present invention, the carry input terminal C and the carry output terminal C 'are both in an open state (a state where they are not connected to other parts).

The correction circuit 3 includes a NAND 4 having two input terminals and two A's having two input terminals.
ND5 and ND6. N
One input terminal of the AND 4 is connected to one operation terminal of the first AND 5 together with the operation output terminal S of the first full adder 1. The other input terminal of NAND4 is
The operation output terminal S of the second full adder 2 and one input terminal of the second AND 6 are connected. In addition, NAND4
Are connected to the other input terminals of the first and second ANDs 5 and 6, respectively. And the first AN
The output terminal of D5 is one output terminal of this ternary digital circuit, and the output terminal of the second AND6 is the other output terminal of this ternary digital circuit. The correction circuit 3 in such a configuration is used only when the two inputs of the NAND 4 are both “1” (in other words, only when the outputs of the first and second full adders 1 and 2 are both at the logical value High). ), Except that both the outputs of the first and second ANDs 5 and 6 become “0”.
The outputs 5 and 6 are the same signals as the respective inputs.

Next, the operation of the ternary digital circuit having the above configuration will be described. First, the ternary digital signal used in the ternary digital circuit shown in FIG. 1 will be described. This ternary digital signal is one bit, "+1", "0", and "-1". Are defined in advance to represent the two values. And
It is assumed that the ternary digital data is converted to binary data and input to the ternary digital circuit. That is, the binary digital data is represented as (D ⁺ , D ⁻ ). For the ternary digital data “+1”, (1, 0) becomes
For ternary digital data "0", (0,0)
However, for ternary digital data “−1”, (0,
1) are allotted in advance.

Under such a premise, the operation of the ternary digital circuit for the addition operation of the 1-bit ternary digital data A and B will be described with reference to FIG. First,
Since addition of 1-bit ternary digital data A and B is a combination of three values, there are six cases. Specifically, as shown in FIG. 2, 0 + 0, 0 + (+ 1), 0 + (−
1), (+1) + (+ 1), (-1) + (-1), (+
1) There is a case of + (-1). According to the above-described expression of the binary digital data, the addition A + B of these ternary digital data is (A ⁺ , A ⁻ ) +
(B ⁺ , B ⁻ ). That is, specifically, “0 + 0” is (0,0) + (0,
0) and “0 + (+ 1)” are (0,0) + (1,0)
And "0 + (-1)" are (0,0) + (0,1),
“(+1) + (− 1)” is (1,0) + (1,0)
And "(-1) + (-1)" are (0,1) + (0,
1) and “(+1) + (− 1)” are (1,0) +
(0, 1), respectively (see FIG. 2).

In the ternary digital circuit shown in FIG. 1, one input terminal X of the first full adder 1 receives one binary digital data A ⁺ , and the other input terminal Y receives one input terminal Y. B ^{+ of the} other binary digital data is input (see FIG. 1). Further, in the second one of the input terminals X of the full adder 2, of one of the binary digital data A ^- is, to the other input terminal Y, the other of the binary digital data B ^- are each input (See FIG. 1). Here, the calculation result for convenience the "Sum ^+" output from the first full adder 1, the operation result conveniently the output from the second full adder 2 "Sum ^-"
The carry data output from the carry output terminal C ′ of the first full adder 1 is represented by “C
arry ' ⁺ "and the carry output terminal C' of the second full adder 2.
The carry data output from the "Carry'^-" and will be represented respectively.

The operation results (Sum ⁺ , Sum ⁻ ) for Cace 1 to Cace 5 are basically the same as the results of ordinary 1-bit data addition. For example, Cace
4 will be described as an example. In this case, the first full adder 1
, "1" is used as A ⁺ and "1" is used as B ⁺
But whereas inputted respectively, in the second full adder 2, A ^- "0" as the, B ^- "0" as the, so that the inputted respectively. As a result, in the first full adder 1, since the operation is "1 + 1", zero is output as the operation output Sum ⁺ , and "1" is output as the carry data Carry ' ^+. (Refer to Case 4 in FIG. 2). Then, as described above, the correction circuit 3 operates so that the input signal and the output signal are the same except when both of the two inputs are “1”. The output Sum ^'+
It becomes "0" similarly to Sum ⁺ .

In the second full adder 2, "0"
Since a calculation of +0 ", the operation output Sum ^- so that the and carry data Carry' ⁺ both zero is output (see the portion of Cace4 in Figure 2). Then, the other output ^Sum'- of the correction circuit 3 also becomes zero. Cases 1 to 3 and Case 5 are basically the same, and a detailed description of each case will be omitted. On the other hand, in the case of Case 6, the operation of the ternary digital data is (+1) + (− 1)
Therefore, the value to be finally obtained by this ternary digital circuit is zero. However, the first and second
The operation results obtained from the full adders 1 and 2 are (Sum ⁺ ,
Sum ⁻ ) = (1, 1) (see Case 6 in FIG. 2). On the other hand, as described above, the correction circuit 3
If the inputs are both "1", the two outputs Sum ' ⁺ , Sum'
^{Since − is set} to zero, the output Sum ^{′ +} , S ^′ of this ternary digital circuit is finally obtained in Case ⁶ .
0,0 can be obtained as ^um'- . As described above, the ternary digital circuit shown in FIG. 1 is capable of performing a ternary digital signal operation using two full adders and three two-input gate elements having the conventional configuration. Has become.

Next, multi-bit addition / subtraction with reference to FIG.
An example of a circuit configuration will be described. First, multi-bit adjustment
In constructing the arithmetic circuit, basically, as shown in FIG.
Connected unit processing bit sections in multiple stages corresponding to the number of bits.
You only need to For example, FIG.
An example of the configuration of a value digital circuit is shown. That is,
In the figure, the combination of binary digital data
(Am-1⁺Am-2⁺... A0⁺, Am-1⁻Am-2⁻...
A0⁻) Is represented by m
= 4. In the example of FIG. 3, A = (A3⁺A2⁺
A1⁺A0 ⁺, A3⁻A2⁻A1⁻A0⁻). In addition, this
Here, A3⁺And A3⁻Is the most significant bit and A0⁺Passing
And A0⁻Is the least significant bit. Also, binary digital
Combination of data (Bm-1⁺Bm-2⁺... B0⁺, Bm
-1⁻Bm-2⁻... B0⁻) The other digit represented by
The data B also has m = 4. And in the example of FIG.
Is B = (B3⁺B2⁺B1⁺B0⁺, B3⁻B2⁻B1⁻B0
⁻) And B3⁺And B3⁻Is the most significant bit and B
0⁺And B0⁻Is the least significant bit. For convenience of explanation
Above, A1 and B1 are the second bit, and A2 and B2 are the third bit.
Each is defined. Also, in FIG.
After the code indicating each component shown in FIG.
A to d in order from the least significant bit corresponding to the
Each element will be distinguished from each other.

When configuring a multi-bit addition / subtraction circuit, the first and second full adders 1 for processing the least significant bit
Each of the carry input terminals C of a and 2a is connected to the ground so that the input state of the logical value Low is established. On the other hand, the first and second full adders 1a to 1d, 2a
To 2d are connected to the carry input terminals C of the first or second full adders 1b to 1d and 2b to 2d of the upper bits. In FIG. 3, Sum′0 ⁺ and Sum′0 ⁻ are the operation results of the least significant bit, respectively, Sum′1 ⁺ and Sum′1 ⁻ are the operation results of the second bit, respectively, and Sum ′ 2 ⁺ , Sum′2 ⁻
Each is the operation result of the third bit, and Sum′3 ⁺ , Su
m'3 ^- is the operation result of the most significant bit. Then, the operation results are sequentially arranged from the most significant bit (Sum'3 ⁺ Sum'2 ⁺ Sum'1 ⁺ Sum'0 ⁺ , Sum'3
^- Sum'2 ^- Sum'1 ^- Sum'0 ^-) to be treated is labeled. The operation of the above configuration is basically the same as that of the configuration shown in FIG. 1 except that the carry from the lower bit is added after the first bit. Therefore, a detailed description is omitted here.

Next, the above ternary digital circuit can be used not only as an adder / subtracter but also as a multiplier. In other words, multiplication of digital data can be generally performed as one-digit multiplication, and repetition of shift and addition. Therefore, in a multiplication circuit, a full adder is generally used as one of the components. On the other hand, multiplication between ternary digital data as described above can be basically processed by repeating one-digit multiplication, shift and addition as described above. Therefore, as a configuration of the ternary digital data multiplication circuit, the portion of the full addition circuit used in the conventional binary digital data multiplication circuit is changed according to the number of bits as shown in FIG. By using a ternary digital circuit configured for multiple bits, the configuration can be basically the same as that of a conventional multiplication circuit except for that part.

Next, a table of the above ternary digital data will be described.
Encoding of new ternary digital data separate from the current
Decoding and encoding circuit and decoding circuit
This will be described with reference to FIG. First, this new ternary data
Digital data is represented as a binary digital signal.
For example, m bits bm... B0 (bm is the most significant bit
B0 is the least significant bit).
(1st encoded data, 2nd encoded data,
Coded data) = (Tm⁺... T0⁺, Tm⁻...
T0⁻). That is, binary
Digital data is encoded into the ternary digital data described above.
For example, if the binary digital data is bm ... b0
First, this binary digital data is
Shift one bit to the bit side and set zero to the least significant bit
In addition, a bit string b (m-1).
N '⁺... T0 '⁺And Also, binary digit
The total data bm... B0 is converted to Tm '⁻... T0
´⁻And Then, the multi-bit circuit illustrated in FIG.
Ternary digital constructed according to the number of bits like a channel
Using the circuit, (Tm '⁺... T0 ' ⁺, 0) and (0,
Tm '⁻... T0 '⁻) Is added to
Digital data (Tm⁺
... T0⁺, Tm⁻... T0⁻)
You.

The above-described encoding will be described in a specific example with reference to FIG. First, it is assumed that binary data B to be encoded is B = 01110011010 in order from the most significant bit. First, this binary data is shifted by one bit toward the most significant bit, zero is added to the least significant bit, and “111001101” is obtained.
00 ", which is designated as T ' ⁺ (see FIG. 4). In addition,
Here, ^T'+ is assumed to have a comprehensive representation of the bit string Tm' ⁺ ··· T0' ^+. On the other hand, B = 011001111
010 as ^T'- to (see FIG. 4). Note that, ^T'- the bit string Tm' ^- ··· T0' ^- and what was comprehensively represents.

Next, (T'+, ⁰⁾ and (0, ^T'-) and of the addition operation, previously similar to the addition process in the three-value digital circuit described with reference to FIGS. 1 and 3 procedures Done at
The encoded data (T ⁺ , T ⁻ ) is obtained as the operation result. It should be noted that, here, ^{T +} is, Tm ⁺ the ··· T0 ^+, T ^-
Is, Tm ^- · · · T0 ^- a, which was respectively generically represents, in this embodiment, a m = 11. In a ternary digital circuit, (T ′ ⁺ , 0), (0, T ′)
^-) and the input of the data represented in the data of the left comma in parentheses () is, in the example of FIG. 3, the data represented by the symbol A, a comma in the right data in parentheses () But Figure 3
In the example, the data on the left side of the parentheses () corresponds to the input terminal X of the full adder, and the data on the right side of the parentheses () What is necessary is just to make it apply to the other input terminal Y of a full adder, respectively. FIG. 5 shows the data before the addition operation for each bit and the encoded data obtained after the operation. In the figure, a row of circled numbers is obtained by adding data in the least significant bit before the addition operation and coded data obtained after the calculation, and a circle of 11 is obtained by adding the data in the most significant bit before the addition operation and after the calculation. The encoded data shown in FIG.

FIG. 6 shows an example of a basic configuration of an encoding circuit suitable for this encoding. Hereinafter, this example of the circuit configuration will be described with reference to FIG. This encoding circuit includes a shift circuit ("SHIFTE" in FIG. 6).
R) 11 and a ternary digital circuit (denoted as “FAC” in FIG. 6) 12. The shift circuit 11 may basically have a publicly-known / well-known configuration.
It has a function of shifting one bit to the most significant bit and adding zero to the least significant bit. The result of the shift by the shift circuit 11 is input to a ternary digital circuit 12.

The ternary digital circuit 12 is shown in FIG.
Based on the number of bits of input data B
First, it is configured for multiple bits as shown in FIG.
Things. The ternary digital circuit 12 has a shift
The output data of the circuit 11 is T ' ⁺As input data
Tab B is T '⁻And (T ′⁺, 0) + (0,
T '⁻) Is calculated, and the encoded data (T⁺, T⁻)But
You can get it.

Next, a decoding method for returning the data (T ⁺ , T ⁻ ) encoded as described above to the original binary data B will be described. First, regarding the bit string of T ⁺ , "0" is replaced with "1" and "1" is replaced with "0", and the newly obtained bit string is set as T1 ⁺ . Next, an addition operation of (T1 ⁺ , 0) + (0, T ⁻ ) is performed in the same procedure as the addition processing in the ternary digital circuit described above with reference to FIGS. (T2 ⁺ , 0) is obtained. Next, T ⁺ is shifted by one bit to the most significant bit side and 1 is added to the least significant bit, and the obtained bit string is designated as T3 ⁺ . Then, the addition operation of (T2 ⁺ , 0) and (T3 ⁺ , 0) is performed in the same procedure as the addition processing in the ternary digital circuit described above with reference to FIGS. Decoded binary data B can be obtained as an operation result.

The above-described decoding will be described in a specific example with reference to FIG. First, encoded data to be decoded is encoded data (T ⁺ , T ⁺⁾ obtained in the specific example of the encoding described above with reference to FIGS. 4 and 5.
T ⁻ ) = (10000100100,00010001)
010). First, T ⁺ = 1000010010
For 0, each bit data is inverted, and T1 ⁺ = 0
1111011011 is obtained (see FIG. 7A). ^{Next, (T1 +, 0) +} (0, T -) = (0111101
The operation of (1011, 0) + (000010001010) is performed in the same procedure as the addition processing in the ternary digital circuit described above with reference to FIGS. 1 and 3, and the result of the operation is (T2 ⁺ , 0) = (0110101000
(1000000000000) (see FIG. 7A).

Next, T ⁺ = 10000100100 is calculated as follows.
While shifting by one bit to the most significant bit side,
By adding 1 to the least significant bit, a new bit string T3 ⁺ = 0
0001001001 is obtained (see FIG. 7B). Finally, (T2 ⁺ , 0) + (T3 ⁺ , 0) = (0110
1010001,0) + (00001001001,
0) is performed using a ternary digital circuit (not shown) configured according to the number of bits as in the multi-bit circuit illustrated in FIG. ,
B) as binary data decoded from 0)
011010 can be obtained (see FIG. 7B).
This binary data matches the binary data to be encoded described above with reference to FIGS. 4 and 5, and it can be confirmed that the decoding has been reliably performed.

Next, an example of the basic configuration of a decoding circuit suitable for the decoding described with reference to FIG. 7 will be described with reference to FIG. The decoding circuit includes an inverting circuit (indicated as “NOT” in FIG. 8) 13, first and second ternary digital circuits (in FIG. 8, both represented as “FAC”) 14 and 15, The shift circuit (“SH” in FIG. 8)
IFTER ") 16). The inverting circuit 13 receives one of the encoded data (T ⁺ , T ⁻ ) to be decoded, that is, T ⁺ , and outputs the inverted data, and is obtained by inversion. bit sequence T1 ⁺ is the first three-value digital circuit 14, the other coded data, i.e., T ^- are input together. The basic structure of each of the first and second ternary digital circuits 1 and 2 is as follows.
It is configured for multiple bits as in the configuration example shown in FIG. 3 according to the number of bits to be decoded using the circuit shown in FIG.

[0030] In the first three values digital circuit ^{14, (T1 +, 0)} + (0, T -) operation is made of, as a calculation result (T2 ^+, 0) are adapted to obtain , T2 ⁺ are input to a second ternary digital circuit 15. The shift circuit 16 receives T ⁺ , and the input bit string is
The bit is shifted by one bit to the most significant bit, and 1 is added to the least significant bit, so that a new bit string T
3 ⁺ is to be output. This shift circuit 1
The output of 6 is input to the second ternary digital circuit 15. In the second ternary digital circuit 15, the operation of (T2 ⁺ , 0) + (T3 ⁺ , 0) is performed, and (B, 0) is obtained as the operation result. That is, the decoded binary digital data B is output.

In the above-described encoding and decoding of binary digital data, the description has been made on the assumption that the binary digital data is positive. Next, encoding and decoding when the binary digital data is a negative number will be described. The conversion will be described using a specific example. First, the coded data (T ⁺ , T ⁻ ) described with reference to FIGS. 4 and 5 are, as it were, T ⁺ representing a positive data portion (hereinafter referred to as “positive portion”) and a negative data portion. T represents a (hereinafter referred to as "negative portion") ^- the capital can be regarded as being expressed by. When the binary digital data to be encoded is a negative number, the positive part and the negative part in the encoding procedure described with reference to FIGS. It is possible to obtain encoded data of digital data.
More specifically, first, it is assumed that, for example, the negative binary digital data B is B = -011101101010. In this case, the data portion “011110011010” excluding the code portion is subjected to the encoding process,
First, the binary digital data is shifted by one bit toward the most significant bit, zero is added to the least significant bit, and
Obtain "11100110100", T'contrary to the case of positive discussed this ahead with reference to FIGS. 4 and 5 ^- to (see FIG. 9). On the other hand, the data part “011110011010” excluding the sign part is T ′ in reverse to the case of a positive number.
⁺ (See FIG. 9).

Next, (T '⁺, 0) and (0, T '⁻)When
Is the ternary value described earlier with reference to FIGS. 1 and 3.
Perform the same procedure as the addition process in the digital circuit,
The encoded data (T⁺, T⁻) = (0
0010001010,10000100100)
(See FIG. 9). Thus, negative binary digital data
Is the code when positive binary digital data is encoded
Data (T⁺, T⁻)⁺Bit string of
And the negative part T ⁻Expressed as a replacement of the bit string of
It is.

Next, the encoded data (0001000
1010, 10000100100) will be described with reference to FIG. The decoding procedure is the same as the procedure described above with reference to FIG. 7 even if the encoded data represents a negative number. That is, first, T ⁺
With respect to = 00010001010, each bit data is inverted to obtain T1 ⁺ = 11101110101 (see FIG. 10A). Next, (T1 ⁺ , 0) + (0,
T ⁻ ) = (01111011011,0) + (0.00,
01000010) is performed in the same procedure as the addition processing in the ternary digital circuit described above with reference to FIGS. 1 and 3, and (T2 ⁺ , 0) =
(01101010001,000000000000)
(See FIG. 10A).

Next, T ⁺ = 10000100100 is calculated as follows:
While shifting by one bit to the most significant bit side,
By adding 1 to the least significant bit, a new bit string T3 ⁺ = 0
0001001001 is obtained (see FIG. 10B). Finally, (T2 ⁺ , 0) + (T3 ⁺ , 0) = (011
0100001,0) + (00001001001,
1) is performed in the same procedure as the addition processing in the ternary digital circuit described above with reference to FIGS. 1 and 3, thereby obtaining the calculation result (B ′, 0) (FIG. 1).
0 (B)). Here, B ′ = 10000110011
0 is the original negative binary digital data B = −01110
The data portion “011100” excluding the sign of “011010”
11010 ". That is, when the encoded data represents a negative number, in this decoding, the decoded data is obtained as a complement of the original binary digital data.

[0035]

As described above, according to the invention of the ternary digital circuit, the ternary digital signal is constituted so that it can be represented by a combination of the binary digital signals and used for the operation. By using a conventional binary logic element, it is possible to provide an arithmetic circuit having a relatively simple configuration and requiring less propagation of a so-called carry signal. In particular, in multi-bit processing, unlike the conventional case, the carry signal does not propagate in multiple stages, and high-speed processing can be performed. In addition, by using the ternary digital circuit according to the present invention for various digital data processing circuits configured by combining an addition operation and other operation processing, the operation rate of constituent gates can be reduced. Therefore, especially in a CMOS circuit whose power consumption is proportional to the operation rate of the constituent gates, a low power consumption CMOS circuit can be realized. Further, in the encoding method according to the present invention, the conventional binary digital data is converted into a representation of a combination of two sets of binary digital data, so that the arithmetic operation is performed by the ternary digital circuit according to the first invention. As a result, the propagation of the carry signal can be reduced as compared with the case where the operation is performed using conventional binary digital data, and more efficient data processing can be performed. Still further, in the decoding method according to the present invention, the data encoded by the encoding method according to the present invention can be decoded into the original binary digital data by a relatively simple procedure as desired. Thus, it is possible to easily use the encoded data and the original binary digital data by the encoding method according to the present invention as desired. In addition, the ternary digital circuit according to the present invention, the encoding circuit that executes the encoding method according to the present invention, and the decoding circuit that executes the decoding method according to the present invention can be easily combined with each other to provide a more complex digital circuit. A digital signal processing circuit such as a filter can be configured, thereby reducing the number of repetitions of encoding and decoding as compared with the related art, and reducing the so-called overhead required for interfacing with a binary number. This makes it possible to easily realize a high-performance digital signal processor LSI with a relatively simple configuration.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing an example of a basic circuit configuration of a ternary digital circuit according to an embodiment of the first invention.

FIG. 2 is an explanatory diagram for explaining arithmetic processing in the ternary digital circuit shown in FIG. 1;

FIG. 3 is a circuit diagram showing a circuit configuration example of a ternary digital circuit suitable for arithmetic processing of 4-bit data.

FIG. 4 is an explanatory diagram illustrating initial processing content in an encoding process according to the embodiment of the second invention.

FIG. 5 is an explanatory diagram for explaining the content of the last arithmetic processing in the encoding processing according to the embodiment of the second invention;

FIG. 6 is a configuration diagram illustrating a configuration example of an encoding circuit according to an embodiment of the third invention.

FIGS. 7A and 7B are explanatory diagrams for explaining a decoding process according to the fourth embodiment of the present invention. FIG. 7A is an explanatory diagram for explaining the contents of an initial stage of the process, and FIG. FIG. 9 is an explanatory diagram for explaining the contents of the last stage of the processing.

FIG. 8 is a configuration diagram showing a configuration example of a decoding circuit according to an embodiment of the fifth invention.

FIG. 9 is an explanatory diagram for explaining the contents of encoding processing of negative binary digital data.

FIG. 10 is an explanatory diagram for explaining the content of a decoding process performed on negative encoded data, and FIG.
FIG. 10B is an explanatory diagram illustrating the contents of the initial stage of the processing.
FIG. 9 is an explanatory diagram for explaining the content of a process termination stage. is there.

FIG. 11 is a configuration diagram illustrating an example of a circuit configuration of a conventional addition circuit.

FIG. 12 is a configuration diagram showing another example of a circuit configuration of a conventional addition circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st full adder 2 ... 2nd full adder 3 ... Correction circuit 4 ... NAND 5 ... 1st AND 6 ... 2nd AND

Claims (8)

[Claims] 1. The ternary digital data -1 is changed to (0,
1) and 0 of the ternary digital data is (0,0),
+1 of the value digital data is replaced with (1, 0) and the binary value
Based on the combination of data
The value digital data is represented by (first encoded bit string, second encoded bit string,
Coded bit sequence).
Based on the above notation method corresponding to ternary digital data
First and second data of each of the binary digital data A and B
2 are both m bits, and the binary data
Digital data A is (Am-1⁺Am-2⁺... A0⁺, Am
-1 ⁻Am-2⁻... A0⁻), The binary digital data
B is (Bm-1⁺Bm-2⁺... B0⁺, Bm-1⁻Bm-2⁻・
..B0⁻), These two binary data
Addition of digital data (Am-1⁺Am-2⁺... A0⁺,
Am-1⁻Am-2⁻... A0⁻) + (Bm-1⁺Bm-2⁺・ ・
・ B0⁺, Bm-1⁻Bm-2⁻... B0⁻) For each
Addition operation of corresponding bits of the first encoded bit sequence
And corresponding bits of each second plurality of bit strings
And perform the addition operation of each other, and the operation results
Before the combination of binary digital data obtained as
The result of addition of the two binary digital data A and B is
A ternary digital circuit for performing an arithmetic operation, comprising: first and second encoding circuits for the binary digital data A;
Combination of bits at a predetermined bit position α in the bit sequence
S (Aα⁺, Aα⁻) And the binary digital data B
1 bit set at the predetermined bit position α
Combination (Bα ⁺, Bα⁻) The unit bit to be added
A bit processing unit is provided according to the number of bits m. The unit bit processing unit has two input terminals, one carry input terminal, and one operation terminal.
A fourth terminal having a calculation force terminal and one carry output terminal;
One full adder, two input terminals, one carry input terminal and one
A fourth terminal having a calculation force terminal and one carry output terminal;
Two full adders, two input terminals and two output terminals, one input terminal
The other input is connected to the operation output terminal of the first full adder by the other input.
The output terminal is connected to the operation output terminal of the second full adder.
Operation outputs of the first and second full adders, respectively connected
Only when both terminals output a logical value High
While the logical value Low is output from the two output terminals,
The operation output terminals of the first and second full adders are both logical values
In the case of a state other than High, one output terminal
Is the same as the output state of the operation output terminal of the first full adder.
Output state, and the other output terminal is connected to the second full adder.
The output state is the same as the output state of the operation output terminal.
And a correction circuit configured to process the least significant bit of the binary digital data.
Carry input of the first and second full adders of the order bit processing unit
The terminal is held at the state of the logical value Low, while the carry of the first full adder of each of the unit bit processing units is carried.
The output terminal of the unit bit processing unit corresponding to the upper bit
The carry input terminal of the first full adder is connected to each of the unit
The carry output terminal of the second full adder of the
Of the first full adder of the unit bit processing unit corresponding to the bit
Connected to the carry input terminals, respectively to one output terminal of each of the unit bit processing units.
The output data obtained is arranged in order from the most significant bit side.
A first bit string, each of which is connected to the other output terminal of each of the unit bit processing units;
The output data obtained is arranged in order from the most significant bit side.
In the case of the second bit string, (first bit string, second bit string
Bit sequence) are the two binary digital data.
Characterized in that the result of addition of the data A and B is
Value digital circuit. 2. The correction circuit has a two-input NAND, a two-input first AND, and a two-input second AND, and has one input terminal of the NAND and the first AND of the first AND. One input terminal is connected to an operation output terminal of a first full adder, and the other input terminal of the NAND and one input terminal of the second AND are output terminals of an operation output terminal of a second full adder. And the output terminal of the NAND is connected to the first and second AND
3. The ternary signal according to claim 1, wherein the output terminal of the first AND and the output terminal of the second AND are output terminals of a unit bit processing unit. Digital circuit. 3. The method according to claim 1, wherein the binary digital data of the positive number is represented by (first
And a second coded bit sequence), wherein the binary digital data is converted to the most significant bit by one bit.
While shifting the bits, zero is added to the least significant bit to obtain a new first bit string.
0), while the bit string of the binary digital data is a second bit string, which is (0, second bit string), and (1st bit string, 0) + (0, second bit string). The addition operation is performed based on a predetermined operation rule, and the operation result is defined as (first encoded bit sequence, second encoded bit sequence).
In each bit of (0, 0) + (0, second bit string), if (0,0) + (0,0), the operation result is (0,0) and the carry is (0,0). , 0), and in the case of (0,0) + (1,0), the operation result is (1,0)
0) and carry (0, 0). In the case of (0, 0) + (0, 1), the operation result is (0, 0).
1) and the carry is (0,0). In the case of (1,0) + (1,0), the operation result is (0,0).
0), the carry is (1,0), and the data generated by the carry is added to the addition operation of the upper bits. In the case of (0,1) + (0,1), the operation result is (0,
0), the carry is (0, 1), the data generated by the carry is added to the addition operation of the upper bits, and in the case of (1, 0) + (0, 1), the calculation result is (0,
0) and carry (0, 0). 4. The method according to claim 1, wherein the binary digital data of the negative number is
And a second coded bit sequence), wherein the bit sequence of the binary digital data is defined as a first bit sequence, which is referred to as (first While the binary digital data is shifted to the most significant bit side by 1
A bit shift is performed, and a zero is added to the least significant bit to obtain a new second bit string. This is set to (0, second bit string), and (first bit string, 0) + (0, second bit string) ) Is performed based on a predetermined operation rule, and the operation result is (first encoded bit sequence, second encoded bit sequence). The predetermined operation rule is the (first bit sequence) , 0) +
In each bit of (0, second bit string),
In the case of (0,0) + (0,0), the operation result is (0,0).
0) together with the carry (0,0). In the case of (0,0) + (1,0), the calculation result is (1,0).
0) and carry (0, 0). In the case of (0, 0) + (0, 1), the operation result is (0, 0).
1) and the carry is (0,0). In the case of (1,0) + (1,0), the operation result is (0,0).
0), the carry is (1,0), and the data generated by the carry is added to the addition operation of the upper bits. In the case of (0,1) + (0,1), the operation result is (0,
0), the carry is (0, 1), the data generated by the carry is added to the addition operation of the upper bits, and in the case of (1, 0) + (0, 1), the calculation result is (0,
0) and carry (0, 0). 5. Decoding for decoding encoded data (a first encoded bit string and a second encoded bit string) obtained by the encoding method according to claim 3 into original binary digital data. A first encoding bit sequence, wherein each bit of the first encoded bit sequence is inverted, and the result is defined as a first bit sequence, which is referred to as (first bit sequence,
0), and the addition operation of the (first bit sequence, 0) + (0, second coded bit sequence) is performed based on a predetermined calculation rule.
(2nd bit string, 0) is obtained as the operation result, and the first coded bit string is shifted by one bit to the most significant bit side, and 1 is added to the least significant bit to add a new third bit string. And this is represented as (third bit string, 0), and the (second bit string, 0) + the (third bit string, 0)
0) is performed based on the operation rule, and the decoded bit string of (decoded bit string, 0) obtained as the operation result is decoded binary digital data, while the predetermined operation rule is In the case of (0,0) + (0,0) in each bit of the operation target, the operation result is set to (0,0) together with (0,0), and (0,0) + In the case of (1, 0), the calculation result is (1, 0)
0) and carry (0, 0). In the case of (0, 0) + (0, 1), the operation result is (0, 0).
1) and the carry is (0,0). In the case of (1,0) + (1,0), the operation result is (0,0).
0), the carry is (1,0), and the data generated by the carry is added to the addition operation of the upper bits. In the case of (0,1) + (0,1), the operation result is (0,
0), the carry is (0, 1), the data generated by the carry is added to the addition operation of the upper bits, and in the case of (1, 0) + (0, 1), the calculation result is (0,
0) and carry (0, 0). 6. An encoding circuit for encoding binary digital data into data represented by (first encoded bit sequence, second encoded bit sequence), wherein said binary digital data is , 1 to the most significant bit side
A shift circuit for shifting the bit and adding a zero to the least significant bit to output a first bit string; and the ternary digital circuit according to claim 1, wherein the ternary digital circuit includes The binary digital data is applied as a second bit string together with the first bit string, an operation of (first bit string, 0) + (0, second bit string) is executed, and encoded data (first code string) is obtained. (Encoded bit sequence, second encoded bit sequence). 7. Decoding for decoding coded data (first coded bit string, second coded bit string) obtained by the coding method according to claim 3 into original binary digital data. An inverting circuit that inverts the logic of each bit of the first encoded bit string and outputs the result as a first bit string; and wherein the first bit string and the second encoded bit string are input. 2. The first ternary digital circuit according to claim 1, wherein an operation result of (first bit sequence, 0) + (0, second encoded bit sequence) is obtained to obtain an operation result of (second bit sequence, 0). A shift circuit that shifts the first coded bit string by one bit to the most significant bit side, adds 1 to the least significant bit, and outputs it as a new third bit string; A third bit sequence is applied
2. The second ternary digital circuit according to claim 1, wherein (second bit string, 0) + (third bit string, 0) is operated, and (decoded bit string, 0) is output. A decoding circuit, characterized in that: 8. A multiplication circuit for performing multiplication of multi-bit ternary digital data using a full adder, wherein the ternary digital circuit according to claim 1 is used instead of the full adder. A multiplication circuit characterized by being used.