RU2476922C1 - FUNCTIONAL DESIGN OF ADDER f3(ΣCD)max OF "k" CONDITIONALLY MOST SIGNIFICANT BITS OF PARALLEL-SERIAL MULTIPLIER fΣ(ΣCD), IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF ARGUMENTS OF TERMS [1,2Sg h1] AND [1,2Sg h2] "COMPLEMENTARY CODE RU" BY ARITHMETIC AXIOM OF TERNARY NUMBER SYSTEM f(+1,0,-1) AND LOGIC DIFFERENTIATION d1/dn → f1(+←↓-)d/dn (VERSIONS OF RUSSIAN LOGIC) - Google Patents

FUNCTIONAL DESIGN OF ADDER f3(ΣCD)max OF "k" CONDITIONALLY MOST SIGNIFICANT BITS OF PARALLEL-SERIAL MULTIPLIER fΣ(ΣCD), IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF ARGUMENTS OF TERMS [1,2Sg h1] AND [1,2Sg h2] "COMPLEMENTARY CODE RU" BY ARITHMETIC AXIOM OF TERNARY NUMBER SYSTEM f(+1,0,-1) AND LOGIC DIFFERENTIATION d1/dn → f1(+←↓-)d/dn (VERSIONS OF RUSSIAN LOGIC) Download PDF

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RU2476922C1
RU2476922C1 RU2012104961/08A RU2012104961A RU2476922C1 RU 2476922 C1 RU2476922 C1 RU 2476922C1 RU 2012104961/08 A RU2012104961/08 A RU 2012104961/08A RU 2012104961 A RU2012104961 A RU 2012104961A RU 2476922 C1 RU2476922 C1 RU 2476922C1
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Лев Петрович Петренко
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Abstract

FIELD: information technology.
SUBSTANCE: one version, the functional design is realised using logic elements AND, OR.
EFFECT: faster operation.
2 cl

Description

Текст описания приведен в факсимильном виде.

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The text of the description is given in facsimile form.
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Claims (2)

1. Функциональная структура сумматора f3(ΣCD)max старших условно «k» разрядов параллельно-последовательного умножителя fΣ(ΣCD), реализующая процедуру «дешифрирования» аргументов слагаемых [1,2Sg h1] и [1,2Sg h2] в «Дополнительном коде RU» посредством арифметических аксиом троичной системы счисления f(+1,0,-1) и логического дифференцирования d1/dn → f1(+←↓-)d/dn, выполненная в виде последовательных старшего разряда «kmin+4» с формированием результирующего аргумента (1Sk h1)max+4 «Уровня 1», средних разрядов «kmin+2,3» с формированием результирующего аргумента ((1Sk h1)max+2 и (1Sk h1)max+3) → (1Sk h1)max+2,3 «Уровня 1» и двух младших разрядов «kmin+1» и «kmin→1» с формированием результирующего аргумента (1Sk h1)max+1 и (1Sk h1)max→1 «Уровня 1» соответственно, которые включают логическую функцию f1(})-ИЛИ, f3(})-ИЛИ, f5(})-ИЛИ и f2(&)-И, f8(&)-И, f14(&)-И, и логическую функцию f1(&)-И и f9(&)-И, в которой функциональная входная связь является функциональной входной связью функциональной структуры для приема аргумента max(1Sk h1) «Уровня 1» структуры аргументов слагаемых [1Sg h1] и логическую функцию f15(&)-И, в которой функциональная входная связь является функциональной входной связью функциональной структуры для приема аргумента max(2Sk h1) «Уровня 1» структуры аргументов слагаемых [2Sg h1], отличающаяся тем, что функциональные структуры средних разрядов «kmin+2,3» выполнены с формированием дополнительного результирующего аргумента (2Sk h1)max+2,3 «Уровня 2» и в них введены дополнительные логические функции f3(&)-И и f4(&)-И, при этом функциональные связи логических функций выполнены в соответствии с математической моделью вида
Figure 00000146

где 1(2Sk h1)max+1↑, 1(1Sk h1)max+1↑, 2(1Sk h1)max+1↑ и 3(1Sk h1)max+1↑ - преобразованные аргументы без изменения уровня аналогового сигнала, которые являются входными аргументами функциональной структуры второго младшего «kmin+1» разряда, которая также выполнена с формированием дополнительного результирующего аргумента (2Sk h1)max+1 «Уровня 2» и в нее введены дополнительные логические функции f5(&)-И, f6(&)-И, f7(&)-И и f2(})-ИЛИ, при этом функциональные связи логических функций выполнены в соответствии с математической моделью
Figure 00000147

а функциональная структура первого младшего «kmin→1» разряда также выполнена с формированием дополнительного результирующего аргумента (2Sk h1)max→1 «Уровня 2» и в нее введены дополнительные логические функции f10(&)-И, f11(&)-И, f12(&)-И, f13(&)-И и f4(})-ИЛИ, при этом функциональные связи логических функций выполнены в соответствии с математической моделью вида
Figure 00000148

Figure 00000149
- логическая функция f1(&)-И;
Figure 00000150
- логическая функция f1(})-ИЛИ.1. The functional structure of the adder f 3 (Σ CD ) max conditionally higher “k” bits of the parallel-serial multiplier f Σ (Σ CD ), implementing the procedure of “decoding” the arguments of the terms [ 1,2 S g h1 ] and [ 1,2 S g h2 ] in the “Additional Code RU” by means of arithmetic axioms of the ternary number system f (+ 1,0, -1) and logical differentiation d 1 / dn → f 1 ( + ← ↓ - ) d / dn , made in the form of consecutive higher category "k min + 4 " with the formation of the resulting argument ( 1 S k h1 ) max + 4 "Level 1", the average bits "k min + 2,3 " with the formation of the resulting ar gumenta (( 1 S k h1 ) max + 2 and ( 1 S k h1 ) max + 3 ) → ( 1 S k h1 ) max + 2,3 “Level 1” and the two least significant bits “k min + 1 ” and “ k min → 1 ”with the formation of the resulting argument ( 1 S k h1 ) max + 1 and ( 1 S k h1 ) max → 1 “ Level 1 ”, respectively, which include the logical function f 1 (}) - OR, f 3 (} ) -OR, f 5 (}) - OR and f 2 (&) - AND, f 8 (&) - AND, f 14 (&) - AND, and the logical function f 1 (&) - And and f 9 ( &) - And, in which the functional input link is the functional input link of the functional structure for receiving the argument max ( 1 S k h1 ) of "Level 1" of the structure of the arguments of the terms [ 1 S g h1 ] and the logical function f 15 (&) - And, in which function The input input link is the functional input link of the functional structure for receiving the max ( 2 S k h1 ) “Level 1” argument argument structure [ 2 S g h1 ], characterized in that the functional structures of the middle digits “k min + 2,3 ” are fulfilled with the formation of an additional resulting argument ( 2 S k h1 ) max + 2,3 "Level 2" and additional logical functions f 3 (&) - And and f 4 (&) - And are introduced into them, while the functional relationships of the logical functions are satisfied in accordance with the mathematical model of the form
Figure 00000146

where 1 ( 2 S k h1 ) max + 1 ↑, 1 ( 1 S k h1 ) max + 1 ↑, 2 ( 1 S k h1 ) max + 1 ↑ and 3 ( 1 S k h1 ) max + 1 ↑ - converted arguments without changing the level of the analog signal, which are input arguments of the functional structure of the second junior “k min + 1 ” bit, which is also performed with the formation of an additional resulting argument ( 2 S k h1 ) max + 1 “Level 2” and additional logical functions f 5 (&) - And, f 6 (&) - And, f 7 (&) - And and f 2 (}) - OR, while the functional relationships of logical functions are made in accordance with the mathematical model
Figure 00000147

and the functional structure of the first minor “k min → 1 ” bit is also performed with the formation of an additional resulting argument ( 2 S k h1 ) max → 1 of “Level 2” and additional logical functions f 10 (&) - И, f 11 ( &) - And, f 12 (&) - And, f 13 (&) - And and f 4 (}) - OR, while the functional relationships of logical functions are made in accordance with a mathematical model of the form
Figure 00000148

Figure 00000149
- logical function f 1 (&) - And;
Figure 00000150
- logical function f 1 (}) - OR. 2. Функциональная структура сумматора fΣ(ΣCD)max старших условно «k» разрядов параллельно-последовательного умножителя fΣ(ΣCD), реализующая процедуру «дешифрирования» аргументов слагаемых [1,2Sg h1] и [1,2Sg h2] в «Дополнительном коде RU» посредством арифметических аксиом троичной системы счисления f(+1,0,-1) и логического дифференцирования d1/dn → f1(+←↓-)d/dn, выполненная в виде последовательных разрядов старшего разряда «kmin+4» с формированием результирующего аргумента (1Sk h1)max+4 «Уровня 1», функциональных структур средних разрядов «kmin+2,3» с формированием результирующего аргумента ((1Sk h1)max+2 и (1Sk h1)max+3) → (1Sk h1)max+2,3 «Уровня 1» и двух младших разрядов «kmin+1» и «kmin→1» с формированием результирующего аргумента (1Sk h1)max+1 и (1Sk h1)max→1 «Уровня 1» и двух младших разрядов «kmin+1» и «kmin→1» с формированием результирующего аргумента (1Sk h1)max+1 и (1Sk h1)max→1 «Уровня 1» соответственно, отличающаяся тем, что функциональные структуры средних разрядов «kmin+2,3» выполнены с формированием дополнительного результирующего аргумента (2Sk h1)max+2,3 «Уровня 2» и в них введены дополнительные логические функции f1(}&)-ИЛИ-НЕ, f1(&)-И-НЕ, f2(&)-И-НЕ, f3(&)-И-НЕ и f4(&)-И-НЕ, при этом функциональные связи логических функций выполнены в соответствии с математической моделью вида
Figure 00000151

где 1(1Sk h1)max+1↑, 2(1Sk h1)max+1↑ и 3(1Sk h1)max+1↑ - преобразованные аргументы с измененным уровнем аналогового сигнала, которые являются входными аргументами функциональной структуры второго младшего «kmin+1» разряда, которая также выполнена с формированием дополнительного результирующего аргумента (2Sk h1)max+1 «Уровня 2» и в нее введены дополнительные логические функции f5(&)-И-НЕ, f6(&)-И-НЕ, f7(&)-И-НЕ, f8(&)-И-НЕ, f9(&)-И-НЕ, f10(&)-И-НЕ, f11(&)-И-НЕ и f12(&)-И-НЕ, при этом функциональные связи логических функций выполнены в соответствии с математической моделью вида
Figure 00000152

а функциональная структура первого младшего «kmin→1» разряда также выполнена с формированием дополнительного результирующего аргумента (2Sk h1)max→1 «Уровня 2» и в нее введены дополнительные логические функции f13(&)-И-НЕ, f14(&)-И-НЕ, f15(&)-И-НЕ, f16(&)-И-НЕ, f17(&)-И-НЕ, f18(&)-И-НЕ, f19(&)-И-НЕ и f20(&)-И-НЕ, при этом функциональные связи логических функций выполнены в соответствии с математической моделью вида
Figure 00000153

Figure 00000154
- логическая функция f1(}&)-ИЛИ-НЕ;
Figure 00000155
- логическая функция f1(&)-И-НЕ. 2. The functional structure of the adder f Σ (Σ CD ) max conditionally higher “k” bits of the parallel-serial multiplier f Σ (Σ CD ), implementing the procedure of “decoding” the arguments of the terms [ 1,2 S g h1 ] and [ 1,2 S g h2 ] in the “Additional Code RU” by means of arithmetic axioms of the ternary number system f (+ 1,0, -1) and logical differentiation d 1 / dn → f 1 ( + ← ↓ - ) d / dn , made in the form of consecutive digits MSB «k min + 4" to form the resulting argument (1 S k h1) max + 4 "Level 1", the functional structures of secondary discharges «k min + 2,3» forming the argument of the resulting ((1 S k h1) max + 2 and (1 S k h1) max + 3) → (1 S k h1) max + 2,3 «Level 1" and the two LSBs «k min + 1" and “k min → 1 ” with the formation of the resulting argument ( 1 S k h1 ) max + 1 and ( 1 S k h1 ) max → 1 “Level 1” and the two least significant bits “k min + 1 ” and “k min → 1 "With the formation of the resulting argument ( 1 S k h1 ) max + 1 and ( 1 S k h1 ) max → 1 " Level 1 ", respectively, characterized in that the functional structures of the middle digits" k min + 2,3 "are made with the formation of additional resulting argument (2 S k h1) max + 2,3 «Level 2" and in them additional log administered cal functions f 1 (} &) -or-NO, f 1 (k) -and-NO, f 2 (k) -and-NO, f 3 (k) -and-NO and f 4 (k) -and -NOT, while the functional relationships of logical functions are made in accordance with a mathematical model of the form
Figure 00000151

where 1 ( 1 S k h1 ) max + 1 ↑, 2 ( 1 S k h1 ) max + 1 ↑ and 3 ( 1 S k h1 ) max + 1 ↑ are converted arguments with a changed level of the analog signal, which are input arguments of the functional structure of the second junior “k min + 1 ” bit, which is also performed with the formation of an additional resulting argument ( 2 S k h1 ) max + 1 “Level 2” and additional logical functions f 5 ( & ) -I-NOT, f are introduced into it 6 ( & ) -AND-NOT, f 7 ( & ) -AND-NOT, f 8 ( & ) -AND NOT, f 9 ( & ) -AND NOT, f 10 ( & ) -AND NOT, f 11 (k) -and-NO element 12 and f (k) -and-NO, wherein the functional linkages of logical functions performed in accordance with the mathematical eskoy model type
Figure 00000152

and the functional structure of the first minor “k min → 1 ” bit is also performed with the formation of an additional resulting argument ( 2 S k h1 ) max → 1 of “Level 2” and additional logical functions f 13 ( & ) -I-NOT, f are introduced into it 14 ( & ) -AND-NOT, f 15 ( & ) -AND-NOT, f 16 ( & ) -AND-NOT, f 17 ( & ) -AND-NOT, f 18 ( & ) -AND NOT, f 19 ( & ) -I-NOT and f 20 ( & ) -I-NOT, while the functional relationships of logical functions are made in accordance with a mathematical model of the form
Figure 00000153

Figure 00000154
- logical function f 1 (} &) - OR NOT;
Figure 00000155
- the logical function f 1 (&) - AND NOT.
RU2012104961/08A 2012-02-13 2012-02-13 FUNCTIONAL DESIGN OF ADDER f3(ΣCD)max OF "k" CONDITIONALLY MOST SIGNIFICANT BITS OF PARALLEL-SERIAL MULTIPLIER fΣ(ΣCD), IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF ARGUMENTS OF TERMS [1,2Sg h1] AND [1,2Sg h2] "COMPLEMENTARY CODE RU" BY ARITHMETIC AXIOM OF TERNARY NUMBER SYSTEM f(+1,0,-1) AND LOGIC DIFFERENTIATION d1/dn → f1(+←↓-)d/dn (VERSIONS OF RUSSIAN LOGIC) RU2476922C1 (en)

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