Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Лев Петрович ПетренкоfiledCriticalЛев Петрович Петренко
Priority to RU2006144607/09ApriorityCriticalpatent/RU2363978C2/en
Publication of RU2006144607ApublicationCriticalpatent/RU2006144607A/en
Application grantedgrantedCritical
Publication of RU2363978C2publicationCriticalpatent/RU2363978C2/en
SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic elements and executing arithmetic operations, particularly summation and subtraction, in positional-sign codes. Each bit of the adder contains four OR elements, two AND elements, three NOT elements and is made in form of two channels - a channel for generating positive sum and a channel for generating conditionally negative sum.
EFFECT: faster operation.
5 dwg
Description
Текст описания приведен в факсимильном виде.
The text of the description is given in facsimile form.
Claims (1)
Устройство параллельного логического суммирования аналоговых сигналов, эквивалентных двоичной системе счисления, условно «i» разряд которого включает логическую функцию f3(})-ИЛИ, две функциональные входные связи которой являются входными связями приема аргументов слагаемых ni и mi, а функциональная выходная связь для формирования аргумента первой промежуточной суммы S1i является выходной функциональной связью условно «i» разряда и первой функциональной входной связью логической функции f2(&)-И, в которой вторая функциональная входная связь является выходной функциональной связью логической функции f3
-HE, отличающееся тем, что условно «i» разряд параллельного сумматора выполнен в виде двух каналов формирования положительной +Si и условно отрицательной -Si суммы, при этом в условно отрицательный канал введены логические функции f4(})-ИЛИ f1
-HE и f2
-HE, а в положительный канал введены логические функции f1(})-ИЛИ, f2(})-ИЛИ, f1
-HE, f2
-HE и f1
-И, при этом функциональные связи логических функций в структуре сумматора выполнены в соответствии с математической моделью вида
где
- логическая функция f(&)-И;
логическая функция f1(})-ИЛИ;
- логическая функция f
-HE изменения активности уровня аналоговых сигналов входного аргумента.
A device for parallel logical summation of analog signals equivalent to a binary number system, conditionally “i” discharge of which includes a logical function f3 (}) - OR, two functional input connections of which are input connections of receiving arguments of the terms n i and m i , and a functional output connection for the formation of the argument of the first intermediate sum S 1i is the output functional link of the conditionally “i” discharge and the first functional input link of the logical function f2 (&) - And, in which the second functional input with ligature is the output functional connection of the logical function f3
-HE, characterized in that the conditionally “i” bit of the parallel adder is made in the form of two channels for generating positive + S i and conditionally negative -S i sums, while the logical functions f4 (}) - OR f1 are introduced into the conditionally negative channel
-HE and f2
-HE, and the logical functions f1 (}) - OR, f2 (}) - OR, f1
-HE, f2
-HE and f1
-And, while the functional relationships of logical functions in the structure of the adder are made in accordance with a mathematical model of the form
Where
- logical function f (&) - And;
logical function f1 (}) - OR;
is a logical function f
-HE changes the activity level of the analog signal input argument.
RU2006144607/09A2006-12-152006-12-15Device for parallel boolean summation of analogue signals of terms equivalent to binary number system
RU2363978C2
(en)
FUNCTIONAL STRUCTURE OF ADDER fi(Σ) OF ARBITRARY "i" BIT FOR LOGIC-DYNAMIC PROCESS OF SUMMATION OF POSITIONAL ARGUMENTS OF TERMS [ni]f(2n) and [mi]f(2n) USING ARITHMETIC AXIOMS OF TERNARY NUMBER SYSTEM f(+1,0,-1) (VERSIONS OF RUSSIAN LOGIC)
FUNCTIONAL STRUCTURE OF PARALLEL ADDER FOR MULTIPLICATION, WHEREIN ARGUMENTS OFTERMS OF PARTIAL PRODUCTS ARE ARGUMENTS OF TERNARY NUMBER SYSTEM f(+1,0,-1) IN POSITIONAL-SIGN FORMAT THEREOF f(+/-) (VERSIONS)
FUNCTIONAL STRUCTURE FOR LOGIC-DYNAMIC PROCESS OF CONVERTING POSITION CONDITIONALLY NEGATIVE ARGUMENTS «-»[ni]f(2n) INTO STRUCTURE OF ARGUMENTS "COMPLEMENTARY CODE" OF POSITION-SIGN FORMAT USING ARITHMETIC AXIOMS OF TERNARY NUMBER SYSTEM f(+1,0,-1) (VERSIONS)
FUNCTIONAL STRUCTURE OF MULTIPLIER, IN WHICH INPUT ARGUMENTS HAVE FORMAT OF BINARY NUMERATION SYSTEM f(2n), AND OUTPUT ARGUMENTS ARE FORMMED IN FORMAT OF POSITION-SIGN NUMERATION SYSTEM f(+/-)
FUNCTIONAL STRUCTURE OF PRE-ADDER fΣ([mj]&[mj,0]) OF PARALLEL-SERIES MULTIPLIER fΣ(Σ) WITH PROCEDURE FOR LOGIC DIFFERENTIATION d/dn OF FIRST INTERMEDIATE SUM [S1 Σ]f(})- OR STRUCTURE OF ACTIVE ARGUMENTS OF MULTIPLICAND [0,mj]f(2n) and [mj,0]f(2n) (VERSIONS)
FUNCTIONAL DESIGN OF PARALLEL POSITION-SIGN ADDER OF ARGUMENTS OF TERMS OF TWO FORMATS OF BINARY NUMBER SYSTEM f(2n) AND POSITION-SIGN NUMBER SYSTEM f(+/-) (VERSIONS)
FUNCTIONAL STRUCTURE OF POSITION-SIGN ACCUMULATOR f(+/-) FOR COMBINATORIAL MULTIPLIER WHERE SUBPRODUCT OUTPUT ARGUMENTS ARE REPRESENTED IN BINARY FORMAT f(2n) (VERSIONS)
f3 ADDER FUNCTIONAL STRUCTURE (ΣCD) OF ARBITRARY "g" DIGIT IMPLEMENTING DECODING PROCEDURE FOR ARGUMENTS OF SUMMANDS [1,2Sg h1]f(2n) AND [1,2Sg h2]f(2n) OF POSITION FORMAT "EXTRA CODE RU" BY ARITHMETIC AXIOMS OF TERNARY NOTATION f(+1,0,-1) AND DOUBLE LOGICAL DIFFERENTIATION d1,2/dn → f1,2(+←↓-)d/dn OF ACTIVE ARGUMENTS OF "LEVEL 2" AND REMOVAL OF ACTIVE LOGICAL ZEROES "+1""-1"→"0" IN "LEVEL 1" (VERSIONS OF RUSSIAN LOGIC)
FUNCTIONAL STRUCTURE OF PROCEDURE OF CONVERTING POSITION CONDITIONALLY NEGATIVE ARGUMENTS «-»[ni]f(2n) INTO STRUCTURE OF ARGUMENTS "COMPLEMENTARY CODE" OF POSITION-SIGN FORMAT USING ARITHMETIC AXIOMS OF TERNARY NUMBER SYSTEM f(+1,0,-1) (VERSIONS)
FUNCTIONAL STRUCTURE OF SECOND LEAST SIGNIFICANT BIT ACTIVATING RESULTANT ARGUMENT (2Smin+1)f(2n) "LEVEL 2" AND (1Smin+1)f(2n) "LEVEL 1" OF ADDDER fCD(Σ)RU FOR ARGUMENTS OF TERMS ±[1,2nj]f(2n) AND ±[1,2mj]f(2n) OF "COMPLEMENTARY CODE RU" FORMAT (VERSIONS OF RUSSIAN LOGIC)
FUNCTIONAL STRUCTURE OF ADDER f2(ΣCD) OF CONDITIONAL "k" BIT OF PARALLEL-SERIAL MULTIPLIER fΣ(ΣCD), IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF INPUT STRUCTURES OF ARGUMENTS OF TERMS [1,2Sj h1]f(2n) AND [1,2Sj h2]f(2n) OF "COMPLEMENTARY CODE RU" POSITIONAL FORMAT BY APPLYING ARITHMETIC AXIOM OF TERNARY NUMBER SYSTEM f(+1,0,-1) AND LOGIC DIFFERENTIATION d1/dn → f1(+←↓-)d/dn OF ARGUMENTS IN COMBINED STRUCTURE THEREOF (VERSIONS OF RUSSIAN LOGIC)
FUNCTIONAL STRUCTURE FOR LOGIC-DYNAMIC PROCESS OF PARALLEL-SERIAL END-TO-END ACTIVATION OF fi(←«+1/-1»)k INACTIVE ARGUMENTS "0" OF SECOND INTERMEDIATE SUM [S2 i]f(2n) IN PROCEDURE FOR SUMMATION OF POSITIONAL ARGUMENTS OF TERMS [ni]f(2n) AND [mi]f(2n) (VERSIONS)
The text of the description is given in facsimile form. 
