RU2363978C2 - Device for parallel boolean summation of analogue signals of terms equivalent to binary number system - Google Patents

Device for parallel boolean summation of analogue signals of terms equivalent to binary number system Download PDF

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RU2363978C2
RU2363978C2 RU2006144607/09A RU2006144607A RU2363978C2 RU 2363978 C2 RU2363978 C2 RU 2363978C2 RU 2006144607/09 A RU2006144607/09 A RU 2006144607/09A RU 2006144607 A RU2006144607 A RU 2006144607A RU 2363978 C2 RU2363978 C2 RU 2363978C2
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functional
logical
conditionally
logical function
binary number
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RU2006144607/09A
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RU2006144607A (en
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Лев Петрович Петренко (UA)
Лев Петрович Петренко
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Лев Петрович Петренко
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Abstract

FIELD: information technology.
SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic elements and executing arithmetic operations, particularly summation and subtraction, in positional-sign codes. Each bit of the adder contains four OR elements, two AND elements, three NOT elements and is made in form of two channels - a channel for generating positive sum and a channel for generating conditionally negative sum.
EFFECT: faster operation.
5 dwg

Description

Текст описания приведен в факсимильном виде.

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The text of the description is given in facsimile form.
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Claims (1)

Устройство параллельного логического суммирования аналоговых сигналов, эквивалентных двоичной системе счисления, условно «i» разряд которого включает логическую функцию f3(})-ИЛИ, две функциональные входные связи которой являются входными связями приема аргументов слагаемых ni и mi, а функциональная выходная связь для формирования аргумента первой промежуточной суммы S1 i является выходной функциональной связью условно «i» разряда и первой функциональной входной связью логической функции f2(&)-И, в которой вторая функциональная входная связь является выходной функциональной связью логической функции f3
Figure 00000030
-HE, отличающееся тем, что условно «i» разряд параллельного сумматора выполнен в виде двух каналов формирования положительной +Si и условно отрицательной -Si суммы, при этом в условно отрицательный канал введены логические функции f4(})-ИЛИ f1
Figure 00000030
-HE и f2
Figure 00000030
-HE, а в положительный канал введены логические функции f1(})-ИЛИ, f2(})-ИЛИ, f1
Figure 00000030
-HE, f2
Figure 00000030
-HE и f1
Figure 00000030
-И, при этом функциональные связи логических функций в структуре сумматора выполнены в соответствии с математической моделью вида
Figure 00000031
Figure 00000032

где
Figure 00000033
- логическая функция f(&)-И;
Figure 00000034
логическая функция f1(})-ИЛИ;
Figure 00000035
- логическая функция f
Figure 00000030
-HE изменения активности уровня аналоговых сигналов входного аргумента. A device for parallel logical summation of analog signals equivalent to a binary number system, conditionally “i” discharge of which includes a logical function f3 (}) - OR, two functional input connections of which are input connections of receiving arguments of the terms n i and m i , and a functional output connection for the formation of the argument of the first intermediate sum S 1 i is the output functional link of the conditionally “i” discharge and the first functional input link of the logical function f2 (&) - And, in which the second functional input with ligature is the output functional connection of the logical function f3
Figure 00000030
-HE, characterized in that the conditionally “i” bit of the parallel adder is made in the form of two channels for generating positive + S i and conditionally negative -S i sums, while the logical functions f4 (}) - OR f1 are introduced into the conditionally negative channel
Figure 00000030
-HE and f2
Figure 00000030
-HE, and the logical functions f1 (}) - OR, f2 (}) - OR, f1
Figure 00000030
-HE, f2
Figure 00000030
-HE and f1
Figure 00000030
-And, while the functional relationships of logical functions in the structure of the adder are made in accordance with a mathematical model of the form
Figure 00000031
Figure 00000032

Where
Figure 00000033
- logical function f (&) - And;
Figure 00000034
logical function f1 (}) - OR;
Figure 00000035
is a logical function f
Figure 00000030
-HE changes the activity level of the analog signal input argument.
RU2006144607/09A 2006-12-15 2006-12-15 Device for parallel boolean summation of analogue signals of terms equivalent to binary number system RU2363978C2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2424549C1 (en) * 2010-03-22 2011-07-20 Лев Петрович Петренко FUNCTIONAL STRUCTURE OF PRE-ADDER fΣ([mj]&[mj,0]) OF PARALLEL-SERIES MULTIPLIER fΣ(Σ) WITH PROCEDURE FOR LOGIC DIFFERENTIATION d/dn OF FIRST INTERMEDIATE SUM [S1 Σ]f(})- OR STRUCTURE OF ACTIVE ARGUMENTS OF MULTIPLICAND [0,mj]f(2n) and [mj,0]f(2n) (VERSIONS)

Citations (3)

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Publication number Priority date Publication date Assignee Title
SU997032A1 (en) * 1981-07-22 1983-02-15 Таганрогский радиотехнический институт им.В.Д.Калмыкова Device for adding in redundancy binary notation
SU1594523A1 (en) * 1986-01-13 1990-09-23 Таганрогский радиотехнический институт им.В.Д.Калмыкова Parallel adder
RU2069009C1 (en) * 1993-12-07 1996-11-10 Научно-исследовательский институт многопроцессорных вычислительных систем при Таганрогском радиотехническом институте им.В.Д.Калмыкова Adding device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU997032A1 (en) * 1981-07-22 1983-02-15 Таганрогский радиотехнический институт им.В.Д.Калмыкова Device for adding in redundancy binary notation
SU1594523A1 (en) * 1986-01-13 1990-09-23 Таганрогский радиотехнический институт им.В.Д.Калмыкова Parallel adder
RU2069009C1 (en) * 1993-12-07 1996-11-10 Научно-исследовательский институт многопроцессорных вычислительных систем при Таганрогском радиотехническом институте им.В.Д.Калмыкова Adding device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
УЭЙКЕРЛИ Д. Проектирование цифровых устройств. Т.1. - М.: Постмаркет, 2002, с.508. *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2424549C1 (en) * 2010-03-22 2011-07-20 Лев Петрович Петренко FUNCTIONAL STRUCTURE OF PRE-ADDER fΣ([mj]&[mj,0]) OF PARALLEL-SERIES MULTIPLIER fΣ(Σ) WITH PROCEDURE FOR LOGIC DIFFERENTIATION d/dn OF FIRST INTERMEDIATE SUM [S1 Σ]f(})- OR STRUCTURE OF ACTIVE ARGUMENTS OF MULTIPLICAND [0,mj]f(2n) and [mj,0]f(2n) (VERSIONS)

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