RU2424549C1 - FUNCTIONAL STRUCTURE OF PRE-ADDER fΣ([mj]&[mj,0]) OF PARALLEL-SERIES MULTIPLIER fΣ(Σ) WITH PROCEDURE FOR LOGIC DIFFERENTIATION d/dn OF FIRST INTERMEDIATE SUM [S1 Σ]f(})- OR STRUCTURE OF ACTIVE ARGUMENTS OF MULTIPLICAND [0,mj]f(2n) and [mj,0]f(2n) (VERSIONS) - Google Patents

FUNCTIONAL STRUCTURE OF PRE-ADDER fΣ([mj]&[mj,0]) OF PARALLEL-SERIES MULTIPLIER fΣ(Σ) WITH PROCEDURE FOR LOGIC DIFFERENTIATION d/dn OF FIRST INTERMEDIATE SUM [S1 Σ]f(})- OR STRUCTURE OF ACTIVE ARGUMENTS OF MULTIPLICAND [0,mj]f(2n) and [mj,0]f(2n) (VERSIONS) Download PDF

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RU2424549C1
RU2424549C1 RU2010110851/08A RU2010110851A RU2424549C1 RU 2424549 C1 RU2424549 C1 RU 2424549C1 RU 2010110851/08 A RU2010110851/08 A RU 2010110851/08A RU 2010110851 A RU2010110851 A RU 2010110851A RU 2424549 C1 RU2424549 C1 RU 2424549C1
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conditionally
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Лев Петрович Петренко (UA)
Лев Петрович Петренко
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Abstract

FIELD: information technology. ^ SUBSTANCE: in one version of the invention, the functional structure in each bit contains elements executing logic functions OR, AND, NAND and NOR, wherein each bit is in form of two summation channels for generating a positive sum and a conditionally negative sum. ^ EFFECT: faster pre-summation process of a multiplicand in parallel-serial multiplier. ^ 4 cl

Description

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The text of the description is given in facsimile form.
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Claims (4)

1. Функциональная структура предварительного сумматора fΣ([mj]&[mj,0]) параллельно-последовательного умножителя fΣ(Σ) с процедурой логического дифференцирования d/dn первой промежуточной суммы [S1 Σ]f(})-ИЛИ структуры активных аргументов множимого [0,mj]f(2n) и [mj,0]f(2n), которая выполнена в виде положительного канала условно «j» разряда для формирования положительной результирующей суммы +S3 j и условно отрицательного канала «j» разряда для формирования условно отрицательной результирующей суммы -S3 j посредством логической функции f4(&)-И, в которой функциональная выходная связь является функциональной выходной связью условно отрицательного канала, при этом положительный канал включает логические функции f1(})-ИЛИ, f2(})-ИЛИ, f3(})-ИЛИ и логическую функцию f1(&)-И, в которой первая функциональная входная связь является функциональной выходной связью логической функции f4(})-ИЛИ, в которой первая функциональная входная связь является функциональной входной связью канала для приема аргумента mj условно «j» разряда структуры аргументов множимого, отличающаяся тем, что в положительный канал условно «j» разряда дополнительно введены логические функции f1(&)-И-НЕ, f1(}&)-ИЛИ-НЕ, f2(&)-И и f3(&)-И, при этом функциональные связи логических функций в структуре предварительного сумматора выполнены в соответствии с математической моделью вида
Figure 00000089

где
Figure 00000090
- логическая функция f1(&)-И;
Figure 00000091
- логическая функция f1(})-ИЛИ;
Figure 00000092
- логическая функция f1(&)-И-НЕ;
Figure 00000093
- логическая функция f1(}&)-ИЛИ-НЕ;
«=&1=» - логическая функция f1(&)-НЕ изменения активности входных аналоговых сигналов.1. The functional structure of the preliminary adder f Σ ([m j ] & [m j , 0]) parallel-series multiplier f Σ (Σ) with the procedure of logical differentiation d / dn of the first intermediate sum [S 1 Σ ] f (}) - OR the structure of the active arguments of the multiplied [0, m j ] f (2 n ) and [m j , 0] f (2 n ), which is made in the form of a positive channel conditionally “j” discharge to form a positive resulting sum + S 3 j and conditionally negative channel "j" of the discharge for the formation of the conditionally negative resulting sum -S 3 j through the logical function f 4 (&) - And, in which A functional output link is a functional output link of a conditionally negative channel, while the positive channel includes the logical functions f 1 (}) - OR, f 2 (}) - OR, f 3 (}) - OR, and the logical function f 1 (&) -And in which the first functional input link is the functional output link of the logical function f 4 (}) - OR, in which the first functional input link is the functional input link of the channel for receiving the argument m j conditionally “j” discharge of the structure of the arguments of the multiplicable, characterized in that in positive anal conditionally «j» discharge logic functions additionally introduced f 1 (k) -and-NO, f 1 (} &) -or-NO, f 2 (k) - and 3 and f (k) - And, the functional communications of logical functions in the structure of the preliminary adder are made in accordance with a mathematical model of the form
Figure 00000089

Where
Figure 00000090
- logical function f 1 (&) - And;
Figure 00000091
- logical function f 1 (}) - OR;
Figure 00000092
- logical function f 1 ( & ) -AND-NOT;
Figure 00000093
- logical function f 1 (} & ) -OR-NOT;
“= & 1 =” - a logical function f 1 (&) - NOT changes in the activity of input analog signals. 2. Функциональная структура предварительного сумматора fΣ([mj]&[mj,0]) параллельно-последовательного умножителя fΣ(Σ) с процедурой логического дифференцирования d/dn первой промежуточной суммы [S1 Σ]f(})-ИЛИ структуры активных аргументов множимого [0,mj]f(2n) и [mj,0]f(2n), которая выполнена в виде положительного канала условно «j» разряда для формирования положительной результирующей суммы +S3 j и условно отрицательного канала «j» разряда для формирования условно отрицательной результирующей суммы -S3 j посредством логической функции f1(&)-И, в которой функциональная выходная связь является функциональной выходной связью условно отрицательного канала, при этом положительный канал включает логические функции f1(})-ИЛИ, f2(})-ИЛИ и логическую функцию f3(})-ИЛИ, в которой первая функциональная входная связь является функциональной входной связью канала для приема аргумента mj условно «j» разряда структуры аргументов множимого, отличающаяся тем, что в положительный канал условно «j» разряда дополнительно введены логические функции f1(&)-И-НЕ, f1(}&)-ИЛИ-НЕ, f2(&)-И-НЕ, f3(&)-И-НЕ, f4(&)-И-НЕ и f5(&)-И-НЕ, при этом функциональные связи логических функций в структуре предварительного сумматора выполнены в соответствии с математической моделью вида
Figure 00000094
2. The functional structure of the preliminary adder f Σ ([m j ] & [m j , 0]) parallel-series multiplier f Σ (Σ) with the logical differentiation procedure d / dn of the first intermediate sum [S 1 Σ ] f (}) - OR the structure of the active arguments of the multiplied [0, m j ] f (2 n ) and [m j , 0] f (2 n ), which is made in the form of a positive channel conditionally “j” discharge to form a positive resulting sum + S 3 j and conditionally negative channel "j" of the discharge for the formation of the conditionally negative resulting sum -S 3 j through the logical function f 1 (&) - And, in which A swift functional output link is a functional output link of a conditionally negative channel, while a positive channel includes logical functions f 1 (}) - OR, f 2 (}) - OR and a logical function f 3 (}) - OR, in which the first functional input the link is a functional input link of the channel for receiving the argument m j conditionally “j” of the discharge of the structure of the arguments of the multiplicable, characterized in that the logical channel f 1 ( & ) -I-NOT, f 1 (} is additionally introduced into the positive channel of the conditionally “j” discharge & ) -OR-NOT, f 2 ( & ) -AND NOT, f 3 ( & ) -AND NOT, f 4 (&) - NOT AND f 5 (&) - AND NOT, while the functional relationships of logical functions in the structure of the preliminary adder are made in accordance with a mathematical model of the form
Figure 00000094
 3. Функциональная структура предварительного сумматора fΣ([mj]&[mj,0]) параллельно-последовательного умножителя fΣ(Σ) с процедурой логического дифференцирования d/dn первой промежуточной суммы [S1 Σ]f(})-ИЛИ структуры активных аргументов множимого [0,mj]f(2n) и [mj,0]f(2n), которая выполнена в виде положительного канала условно «j» разряда для формирования положительной результирующей суммы +S3 j и условно отрицательного канала «j» разряда для формирования условно отрицательной результирующей суммы -S3 j, при этом положительный канал включает логические функции f1(&)-И, f2(})-ИЛИ, f3(})-ИЛИ, f4(})-ИЛИ и логические функции f1(})-ИЛИ и f1(&)-НЕ, в которых функциональная входная связь является функциональной входной связью канала для приема аргумента mj условно «j» разряда структуры аргументов множимого, отличающаяся тем, что в положительный канал условно «j» разряда дополнительно введены логические функции f1(}&)-ИЛИ-НЕ, f2(}&)-ИЛИ-НЕ, f3(}&)-ИЛИ-НЕ и f1(&)-И-НЕ, а в условно отрицательный канал введена логическая функция f4(}&)-ИЛИ-НЕ, при этом функциональные связи логических функций в структуре предварительного сумматора выполнены в соответствии с математической моделью вида
Figure 00000095
3. The functional structure of the preliminary adder f Σ ([m j ] & [m j , 0]) parallel-series multiplier f Σ (Σ) with the logical differentiation procedure d / dn of the first intermediate sum [S 1 Σ ] f (}) - OR the structure of the active arguments of the multiplied [0, m j ] f (2 n ) and [m j , 0] f (2 n ), which is made in the form of a positive channel conditionally “j” discharge to form a positive resulting sum + S 3 j and conditionally negative channel «j» discharge for forming negative conventionally resultant sum -S 3 j, wherein the channel includes a positive logs RP G function f 1 (k) - and, f 2 (}) - OR, f 3 (}) - OR, f 4 (}) - OR and logical functions f 1 (}) - OR and f 1 (k) - NOT, in which the functional input link is the functional input link of the channel for receiving the argument m j conditionally “j” of the discharge of the structure of the arguments of the multiplicable, characterized in that the logical channel f 1 (} & ) OR is additionally introduced into the positive channel of the conditionally “j” discharge -NOT, f 2 (} & ) -OR-NOT, f 3 (} & ) -OR-NOT and f 1 ( & ) -AND NOT, and the logical function f 4 (} & ) is introduced into the conditionally negative channel - OR NOT, while the functional relationships of logical functions in the structure of pre two-adder are made in accordance with a mathematical model of the form
Figure 00000095
 4. Функциональная структура предварительного сумматора fΣ([mj]&[mj,0]) параллельно-последовательного умножителя fΣ(Σ) с процедурой логического дифференцирования d/dn первой промежуточной суммы [S1 Σ]f(})-ИЛИ структуры активных аргументов множимого [0,mj]f(2n) и [mj,0]f(2n), которая выполнена в виде положительного канала условно «j» разряда для формирования положительной результирующей суммы +S3 j и условно отрицательного канала «j» разряда для формирования условно отрицательной результирующей суммы -S3 j, при этом положительный канал включает логические функции f1(&)-И, f2(})-ИЛИ и логическую функцию f1(})-ИЛИ и f1(&)-НЕ, в которых функциональная входная связь является функциональной входной связью канала для приема аргумента mj условно «j» разряда структуры аргументов множимого, отличающаяся тем, что в положительный канал условно «j» разряда дополнительно введены логические функции f1(}&)-ИЛИ-НЕ, f2(}&)-ИЛИ-НЕ, f3(}&)-ИЛИ-НЕ, f4(}&)-ИЛИ-НЕ, f5(}&)-ИЛИ-НЕ и f6(}&)-ИЛИ-НЕ, а в условно отрицательный канал введена логическая функция f7(}&)-ИЛИ-НЕ, при этом функциональные связи логических функций в структуре предварительного сумматора выполнены в соответствии с математической моделью вида
Figure 00000096
4. The functional structure of the preliminary adder f Σ ([m j ] & [m j , 0]) parallel-series multiplier f Σ (Σ) with the logical differentiation procedure d / dn of the first intermediate sum [S 1 Σ ] f (}) - OR the structure of the active arguments of the multiplied [0, m j ] f (2 n ) and [m j , 0] f (2 n ), which is made in the form of a positive channel conditionally “j” discharge to form a positive resulting sum + S 3 j and conditionally negative channel «j» discharge for forming negative conventionally resultant sum -S 3 j, wherein the channel includes a positive logs RP G function f 1 (k) - and, f 2 (}) - OR and logical function f 1 (}) - OR 1, and f (k) is not wherein the functional relationship is the functional input channel input coupled for receiving an argument m j conditionally “j” discharge of the structure of arguments of the multiplicable, characterized in that the logical channel f 1 (} & ) -OR-NOT, f 2 (} & ) -OR- NOT, f 3 are additionally introduced into the positive channel of the conditionally “j” discharge (} & ) -OR- NOT, f 4 (} & ) -OR- NOT, f 5 (} & ) -OR- NOT and f 6 (} & ) -OR- NOT, but a logical function is introduced into the conditionally negative channel f 7 (} & ) -OR-NOT, while the functional relationships of logical functions in st The structure of the preliminary adder is made in accordance with the mathematical model of the form
Figure 00000096
RU2010110851/08A 2010-03-22 2010-03-22 FUNCTIONAL STRUCTURE OF PRE-ADDER fΣ([mj]&[mj,0]) OF PARALLEL-SERIES MULTIPLIER fΣ(Σ) WITH PROCEDURE FOR LOGIC DIFFERENTIATION d/dn OF FIRST INTERMEDIATE SUM [S1 Σ]f(})- OR STRUCTURE OF ACTIVE ARGUMENTS OF MULTIPLICAND [0,mj]f(2n) and [mj,0]f(2n) (VERSIONS) RU2424549C1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2586565C2 (en) * 2011-12-20 2016-06-10 Лев Петрович Петренко FUNCTIONAL STRUCTURE OF PRE-ADDER f1(ΣCD) OF CONDITIONAL "j" BIT OF PARALLEL-SERIAL MULTIPLIER fΣ(Σ) IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF ARGUMENTS OF PARTIAL PRODUCTS WITH STRUCTURES OF ARGUMENTS OF MULTIPLICAND [mj]f(2n) AND MULTIPLIER [ni]f(2n) IN POSITION FORMAT OF "ADDITIONAL CODE" AND FORMATION OF INTERMEDIATE SUM [1,2Sjh1]f(2n) IN POSITION FORMAT OF "ADDITIONAL CODE RU" (RUSSIAN LOGIC VERSIONS)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2586565C2 (en) * 2011-12-20 2016-06-10 Лев Петрович Петренко FUNCTIONAL STRUCTURE OF PRE-ADDER f1(ΣCD) OF CONDITIONAL "j" BIT OF PARALLEL-SERIAL MULTIPLIER fΣ(Σ) IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF ARGUMENTS OF PARTIAL PRODUCTS WITH STRUCTURES OF ARGUMENTS OF MULTIPLICAND [mj]f(2n) AND MULTIPLIER [ni]f(2n) IN POSITION FORMAT OF "ADDITIONAL CODE" AND FORMATION OF INTERMEDIATE SUM [1,2Sjh1]f(2n) IN POSITION FORMAT OF "ADDITIONAL CODE RU" (RUSSIAN LOGIC VERSIONS)

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