RU2480817C1 - FUNCTIONAL STRUCTURE OF ADDER f2(ΣCD) OF CONDITIONAL "k" BIT OF PARALLEL-SERIAL MULTIPLIER fΣ(ΣCD), IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF INPUT STRUCTURES OF ARGUMENTS OF TERMS [1,2Sj h1]f(2n) AND [1,2Sj h2]f(2n) OF "COMPLEMENTARY CODE RU" POSITIONAL FORMAT BY APPLYING ARITHMETIC AXIOM OF TERNARY NUMBER SYSTEM f(+1,0,-1) AND LOGIC DIFFERENTIATION d1/dn → f1(+←↓-)d/dn OF ARGUMENTS IN COMBINED STRUCTURE THEREOF (VERSIONS OF RUSSIAN LOGIC) - Google Patents

FUNCTIONAL STRUCTURE OF ADDER f2(ΣCD) OF CONDITIONAL "k" BIT OF PARALLEL-SERIAL MULTIPLIER fΣ(ΣCD), IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF INPUT STRUCTURES OF ARGUMENTS OF TERMS [1,2Sj h1]f(2n) AND [1,2Sj h2]f(2n) OF "COMPLEMENTARY CODE RU" POSITIONAL FORMAT BY APPLYING ARITHMETIC AXIOM OF TERNARY NUMBER SYSTEM f(+1,0,-1) AND LOGIC DIFFERENTIATION d1/dn → f1(+←↓-)d/dn OF ARGUMENTS IN COMBINED STRUCTURE THEREOF (VERSIONS OF RUSSIAN LOGIC) Download PDF

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RU2480817C1
RU2480817C1 RU2011151809/08A RU2011151809A RU2480817C1 RU 2480817 C1 RU2480817 C1 RU 2480817C1 RU 2011151809/08 A RU2011151809/08 A RU 2011151809/08A RU 2011151809 A RU2011151809 A RU 2011151809A RU 2480817 C1 RU2480817 C1 RU 2480817C1
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arguments
functional
σcd
logic
logical
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Лев Петрович Петренко
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Лев Петрович Петренко
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Abstract

FIELD: information technology.
SUBSTANCE: invention relates to computer engineering and can be used when designing arithmetic units and performing arithmetic procedures of summation of positional arguments of analogue signals of terms [ni]f(2n) and [mi]f(2n) by applying the arithmetic axiom of the ternary number system f(+1,0,-1). The functional structure is realised using logic elements AND, OR.
EFFECT: faster operation.
1 cl

Description

Текст описания приведен в факсимильном виде.

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The text of the description is given in facsimile form.
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Claims (1)

Функциональная структура сумматора f2(ΣCD) условно «k» разряда параллельно-последовательного умножителя fΣ(ΣCD), реализующая процедуру «дешифрирования» входных структур аргументов слагаемых [1,2Sj h1]f(2n) и [1,2Sj h2]f(2n) позиционного формата «Дополнительный код RU» посредством применения арифметических аксиом троичной системы счисления f(+1,0,-1) и логического дифференцирования d1/dn → f1(+←↓-)d/dn аргументов в объединенной их структуре, включающая логическую функцию f1(})-ИЛИ, в которой функциональные входные связи являются функциональными входными связями структуры, а функциональная выходная связь является функциональной входной связью логической функции f1(&)-И, а также включает логическую функцию f2(&)-И, в которой функциональные входные связи являются функциональными входными связями структуры, отличающаяся тем, что в структуру условно «k» разряда для активизации результирующего аргумента (1 S k) «Уровня 1» введены логические функции f2(})-ИЛИ, f3(})-ИЛИ, f4(})-ИЛИ и f5(})-ИЛИ, а также логические функции f3(&)-И и f4(&)-И, при этом функциональные связи логических функций в структуре сумматора выполнены в соответствии с математической моделью вида
Figure 00000195

где ↓-(2 S k h1)↓d/dn и ↓-(1 S k h2)↓d/dn - преобразованные аргументы локального переноса f(+↓-)d/dn процедуры логического дифференцирования d1/dn → f1(+←↓-)d/dn являются результирующими аргументами функциональных дополнительных структур, в которых функциональные связи выполнены в соответствии с математической моделью
Figure 00000196

в которых (1 S k)1 и (1 S k)2 - выходные аргументы являются результирующими аргументами функциональных дополнительных структур, в которых функциональные связи выполнены в соответствии с математической моделью
Figure 00000197

а для активизации результирующего аргумента (2 S k) «Уровня 2» «Дополнительного кода RU» в условно «k» разряд введены логические функции f6(})-ИЛИ, f7(})-ИЛИ, f8(})-ИЛИ, f9(})-ИЛИ, f10(})-ИЛИ, f11(})-ИЛИ, f12(})-ИЛИ, f13(})-ИЛИ, f14(})-ИЛИ, f15(})-ИЛИ и f16(})-ИЛИ, а также логические функции f7(&)-И, f8(&)-И, f9(&)-И, f10(&)-И, f11(&)-И и f12(&)-И, при этом функциональные связи логических функций в структуре сумматора выполнены в соответствии с математической моделью вида
Figure 00000198

где ↓+(1 S k h2)←d/dn и +1(2 S k h1)←d/dn, ↓+2(2 S k h1)←d/dn - преобразованные аргументы локального переноса f1(+←+)d/dn процедуры логического дифференцирования d1/dn → f1(+←↓-)d/dn являются результирующими аргументами функциональных дополнительных структур, в которых функциональные связи выполнены в соответствии с математической моделью
Figure 00000199

Figure 00000200
- логическая функция f1(&)-И;
Figure 00000201
- логическая функция f1(})-ИЛИ.     Functional structure of adder f2(ΣCD)  conditionally "k" discharge parallel-series multiplier fΣ(ΣCD), which implements the procedure of “decoding” of input structures of the arguments of the terms [1,2Sj h1] f (2n) and [1,2Sj h2] f (2n) positional format “Additional RU code” by using arithmetic axioms of the ternary number system f (+ 1,0, -1) and logical differentiation done/ dn → fone(+← ↓-)d / dn arguments in their combined structure, including the logical function fone(}) -OR, in which the functional input links are the functional input links of the structure, and the functional output link is the functional input link of the logical function fone(&) - And, and also includes the logical function f2(&) - And, in which the functional input links are the functional input links of the structure, characterized in that the structure is conditionally “k” of the discharge to activate the resulting argument (one S k) “Level 1” introduced logical functions f2(}) -OR, f3(}) -OR, ffour(}) -OR and f5(}) -OR, as well as logical functions f3(&) - And and ffour(&) - And, while the functional relationships of logical functions in the adder structure are made in accordance with a mathematical model of the form
Figure 00000195

 where ↓-(2 S k h1)↓ d / dn and ↓-(one S k h2)↓ d / dn are the transformed local transfer arguments f (+↓-)d / dn logical differentiation procedures done/ dn → fone(+← ↓-)d / dn are the resulting arguments of the functional additional structures in which the functional relationships are made in accordance with the mathematical model
Figure 00000196

in which (one S k)one and (one S k)2 - output arguments are the resulting arguments of the functional additional structures in which the functional relationships are made in accordance with the mathematical model
Figure 00000197

and to activate the resulting argument (2 S k) “Level 2” “Additional CodeRU"In the conditionally" k "category introduced logical functions f6(}) -OR, f7(}) -OR, f8(}) -OR, f9(}) -OR, f10(}) -OR, feleven(}) -OR, f12(}) -OR, f13(}) -OR, ffourteen(}) -OR, ffifteen(}) -OR and f16(}) -OR, as well as logical functions f7(&) - And, f8(&) - And, f9(&) - And, f10(&) - And, feleven(&) - And and f12(&) - And, while the functional relationships of logical functions in the adder structure are made in accordance with a mathematical model of the form
Figure 00000198

where ↓+(one S k h2)← d / dn  and+1(2 S k h1)← d / dn, ↓+2(2 S k h1)← d / dn are transformed local transfer arguments fone(+←+)d / dnlogical differentiation procedures done/ dn → fone(+← ↓-)d / dn are the resulting arguments of the functional additional structures in which the functional relationships are made in accordance with the mathematical model
Figure 00000199

Figure 00000200
          is a logical function fone(&)-AND;
Figure 00000201
          is a logical function fone(})-OR.
RU2011151809/08A 2011-12-20 2011-12-20 FUNCTIONAL STRUCTURE OF ADDER f2(ΣCD) OF CONDITIONAL "k" BIT OF PARALLEL-SERIAL MULTIPLIER fΣ(ΣCD), IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF INPUT STRUCTURES OF ARGUMENTS OF TERMS [1,2Sj h1]f(2n) AND [1,2Sj h2]f(2n) OF "COMPLEMENTARY CODE RU" POSITIONAL FORMAT BY APPLYING ARITHMETIC AXIOM OF TERNARY NUMBER SYSTEM f(+1,0,-1) AND LOGIC DIFFERENTIATION d1/dn → f1(+←↓-)d/dn OF ARGUMENTS IN COMBINED STRUCTURE THEREOF (VERSIONS OF RUSSIAN LOGIC) RU2480817C1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002014804A (en) * 2000-06-29 2002-01-18 New Japan Radio Co Ltd Ternary digital circuit
US7274211B1 (en) * 2006-03-10 2007-09-25 Xilinx, Inc. Structures and methods for implementing ternary adders/subtractors in programmable logic devices
RU2386162C2 (en) * 2008-04-29 2010-04-10 Лев Петрович Петренко FUNCTIONAL STRUCTURE OF PARALLEL ADDER FOR MULTIPLICATION, WHEREIN ARGUMENTS OFTERMS OF PARTIAL PRODUCTS ARE ARGUMENTS OF TERNARY NUMBER SYSTEM f(+1,0,-1) IN POSITIONAL-SIGN FORMAT THEREOF f(+/-) (VERSIONS)

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002014804A (en) * 2000-06-29 2002-01-18 New Japan Radio Co Ltd Ternary digital circuit
US7274211B1 (en) * 2006-03-10 2007-09-25 Xilinx, Inc. Structures and methods for implementing ternary adders/subtractors in programmable logic devices
RU2386162C2 (en) * 2008-04-29 2010-04-10 Лев Петрович Петренко FUNCTIONAL STRUCTURE OF PARALLEL ADDER FOR MULTIPLICATION, WHEREIN ARGUMENTS OFTERMS OF PARTIAL PRODUCTS ARE ARGUMENTS OF TERNARY NUMBER SYSTEM f(+1,0,-1) IN POSITIONAL-SIGN FORMAT THEREOF f(+/-) (VERSIONS)

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Дж.Уэйкерли. Проектирование цифровых устройств. - М.: ПОСТМАРКЕТ, 2002, с.508. *

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