RU2422881C1 - FUNCTIONAL OUTPUT STRUCTURE FOR PARALLEL-SERIAL MULTIPLIER fΣ(Σ) IN POSITION FORMAT OF MULTIPLICAND [mj]f(2n) AND MULTIPLIER [ni]f(2n) (VERSIONS) - Google Patents
FUNCTIONAL OUTPUT STRUCTURE FOR PARALLEL-SERIAL MULTIPLIER fΣ(Σ) IN POSITION FORMAT OF MULTIPLICAND [mj]f(2n) AND MULTIPLIER [ni]f(2n) (VERSIONS) Download PDFInfo
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- RU2422881C1 RU2422881C1 RU2010108238/08A RU2010108238A RU2422881C1 RU 2422881 C1 RU2422881 C1 RU 2422881C1 RU 2010108238/08 A RU2010108238/08 A RU 2010108238/08A RU 2010108238 A RU2010108238 A RU 2010108238A RU 2422881 C1 RU2422881 C1 RU 2422881C1
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Abstract
FIELD: information technology. ^ SUBSTANCE: in one version, the device has two logic structures, each consisting of j AND logic elements, a logic structure consisting of j+2 AND logic elements and a logic structure consisting of j+2 OR logic elements. ^ EFFECT: simple design of the multiplier and high speed of operation. ^ 4 cl
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Claims (4)
где - линейная логическая структура f1-8([&j])-И, которая включает «j» логических функций f(&)-И - линейная логическая структура f([}j+2])-ИЛИ, которая включает «j+2» логических функций f(})-ИЛИ.1. The functional input structure of a parallel-serial multiplier f Σ (Σ) in the positional format of the multiplier [m j ] f (2 n ) and the factor [n i ] f (2 n ), which includes an adder to form an intermediate sum [S j + 2 ] 0 and linear logical structures f 1 ([& j ]) - And and f 2 ([& j ]) - And from the "j" logical functions f (&) - And to form two conditionally "i + 1" and «i» partial products, in which the first function input connection are functional input connections for receiving input structure argument n i and n i + 1 multiplier [n i] f (2 n), and the second functional Rin dnye communications are functional input connections of the input structure for receiving the corresponding argument [m j] multiplicand [m j] f (2 n), characterized in that the upstream structure is further introduced linear logical structure of f ([& j + 2]) - and from "j + 2" logical functions f (&) - AND and the linear logical structure f ([} j + 2 ]) - OR from "j + 2" logical functions f (}) - OR to form the resulting sum [S j +2] (i + 1 & i) two conventionally «i + 1" and «i» successive partial products, wherein the functional relationship of the input structure parallel to serial factor f Σ (Σ) made in accordance with the mathematical model of the form
Where - linear logical structure f 1-8 ([& j ]) - And, which includes the "j" logical functions f (&) - And - linear logical structure f ([} j + 2 ]) - OR, which includes "j + 2" logical functions f (}) - OR.
где - линейная логическая структура f([& j])-И-НЕ, которая включает «j» логических функций f(&)-И-НЕ.2. Functional input structure of a parallel-serial multiplier f Σ (Σ) in the positional format of the multiplier [m j ] f (2 n ) and the factor [n i ] f (2 n ), which includes an adder to form an intermediate sum [S j + 2 ] 0 , characterized in that linear logical structures f 1 ([ & j ]) - AND-NOT, f 2 ([ & j ]) - AND-NOT from the “j” logical functions f ( & ) AND-NOT, f 1 ([ & j + 2 ]) - AND NOT from the “j + 2” logical functions f ( & ) -AND NOT and the linear logical structure f 1 ([ & j + 2 ]) -AND NOT from the "j + 2" logical functions f ( & ) -AND NOT to form the resulting sum [S j + 2 ] (i + 1 & i) of two conditionally “i + 1” and “i” consecutive partial products, while the functional connections in the input structure of the parallel-serial multiplier f Σ (Σ) are made in accordance with a mathematical model of the form
Where - the linear logical structure f ([ & j ]) - AND-NOT, which includes the "j" logical functions f ( & ) -AND-NOT.
3. The functional input structure of a parallel-serial multiplier f Σ (Σ) in the positional format of the multiplier [m j ] f (2 n ) and the factor [n i ] f (2 n ), which includes an adder to form an intermediate sum [ S j + 2 ] 0 with a changed level of the analog signal, characterized in that linear logic structures f 1 ([} j ]) - OR, f 2 ([} j ]) - OR from "j" logic functions f ( }) - OR, the linear logical structure f 1 ([} j + 2 ]) - OR from the "j + 2" logical functions f (}) - OR and the linear logical structure f 1 ([ & j + 2 ]) - AND -NOT of the "j + 2" logs eskih functions f (&) -And-NO to form the resultant sum [S j + 2] (i + 1 & i) two conventionally «i + 1" and «i» successive partial products, wherein the functional relationship of the input structure parallel to serial the multipliers f Σ (Σ) are made in accordance with a mathematical model of the form
где - линейная логическая структура f1,2([}& j])-ИЛИ-НЕ, которая включает «j» логических функций f(}&)-ИЛИ-НЕ. 4. Functional input structure of a parallel-serial multiplier f Σ (Σ) in the positional format of the multiplier [m j ] f (2 n ) and the factor [n i ] f (2 n ), which includes an adder to form an intermediate sum [ S j + 2 ] 0 with a changed analog signal level, characterized in that linear logical structures f 1 ([} & j ]) - OR-NOT, f 2 ([} & j ]) - OR-NOT from " j "of logical functions f (} & ) - OR NOT, linear logical structure f ([} & j + 2 ]) - OR NOT from" j + 2 "logical functions f (} & ) - OR NOT and linear logical structure f ([} j + 2 ]) - OR from “j + 2” logical functions f (}) - OR to form the resulting sum [S j + 2 ] (i + 1 & i) of two conditionally “i + 1” and “i” consecutive partial products, while the functional relationships in the input structure of a parallel-serial multiplier f Σ (Σ) is made in accordance with a mathematical model of the form
Where - the linear logical structure f 1,2 ([} & j ]) - OR NOT, which includes the "j" logical functions f (} & ) - OR NOT.
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RU2010108238/08A RU2422881C1 (en) | 2010-03-04 | 2010-03-04 | FUNCTIONAL OUTPUT STRUCTURE FOR PARALLEL-SERIAL MULTIPLIER fΣ(Σ) IN POSITION FORMAT OF MULTIPLICAND [mj]f(2n) AND MULTIPLIER [ni]f(2n) (VERSIONS) |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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RU2753184C1 (en) * | 2020-12-26 | 2021-08-12 | Акционерное общество Научно-производственный центр «Электронные вычислительно-информационные системы» (АО НПЦ «ЭЛВИС») | Parametrizable single-stroke binary multiplier with fixed dot in direct and auxiliary code |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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RU2753184C1 (en) * | 2020-12-26 | 2021-08-12 | Акционерное общество Научно-производственный центр «Электронные вычислительно-информационные системы» (АО НПЦ «ЭЛВИС») | Parametrizable single-stroke binary multiplier with fixed dot in direct and auxiliary code |
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