RU2378682C2 - INPUT STRUCTURE FOR PARALLEL ADDER IN POSITION-SIGN CODES f(+/-)(VERSIONS) - Google Patents
INPUT STRUCTURE FOR PARALLEL ADDER IN POSITION-SIGN CODES f(+/-)(VERSIONS) Download PDFInfo
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- RU2378682C2 RU2378682C2 RU2007146288/09A RU2007146288A RU2378682C2 RU 2378682 C2 RU2378682 C2 RU 2378682C2 RU 2007146288/09 A RU2007146288/09 A RU 2007146288/09A RU 2007146288 A RU2007146288 A RU 2007146288A RU 2378682 C2 RU2378682 C2 RU 2378682C2
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Abstract
FIELD: physics; computer engineering.
SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic devices for carrying out arithmetic operations of summation and subtraction in position-sign codes. Each bit of the adder is made in form of structure-equivalent channels - positive and conditionally negative. In one version of implementation, the ith bit of each channel contains two OR logic components, two NAND logic components, two inverter gates and an AND logic component.
EFFECT: simplification of functional structure of the adder and faster operation.
2 cl, 13 dwg
Description
Claims (2)
«=& 1=» - инвертирующая функция f1(&)-HE или функция изменения активности аналоговых сигналов.1. The input structure of the parallel adder in position-sign codes f (+/-), conditionally “i” discharge of which is made in the form of two logical functions of positive and conditionally negative summation channels of equivalent terms and each channel of “i” discharge includes input logic functions f 1 ({) -OR and f 1 (&) - AND-HE, two functional input links, which are functional links for receiving input arguments + n i and + m i or -n i and -m i , in the corresponding channels , and the output functional connections of these logical functions, which rmiruyut converted arguments first intermediate sum or and arguments changed in level of the analog signal or in the corresponding channels, are the functional input links of the output logical functions f 1 (&) - And and f 2 ( & ) -AND-NOT, which form the converted arguments of the output intermediate sums without changing the level of the analog signal or and output arguments of intermediate sums with a changed analog signal level or the output functional links of which are the output functional links of the corresponding sign of the channels, characterized in that the logical function f 2 ({) -OR or inverting functions f 1 ( & ) -HE and f 2 ( & ) -HE are additionally introduced into each channel the functional relationships of logical functions in the adder structure are made in accordance with a mathematical model of the form
“= & 1 =” is the inverting function f 1 ( & ) -HE or the function of changing the activity of analog signals.
2. The input structure of the parallel adder in position-sign codes f (+/-), conditionally “i” discharge of which is made in the form of two logical functions of positive and conditionally negative summation channels of equivalent components, and each channel “i” of the discharge includes logical functions f 1 (}) - OR and f 1 ( & ) -and, characterized in that the logical functions f 1 (} & ) -OR-NOT, f 2 (} & ) -OR-NOT and f 3 ( } & ) -OR-NOT, while the functional relationships of logical functions are made in the input structure of the adder in accordance with the mathematical model of the species
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
RU2443008C1 (en) * | 2010-07-22 | 2012-02-20 | Лев Петрович Петренко | FUNCTIONAL STRUCTURE OF A TRANSFORMER OF PRELIMINARY FA fΣ [ni]&[mi](2n) OF PARALLEL-SERIAL MULTIPLICATOR fΣ (Σ) CONDITIONALLY, OF "i" DIGIT TO SUM UP OF POSITIONAL ADDITIVE OF SUMS [ni]f(2n) AND [mi]f(2n) OF PARTIAL PRODUCTS USING ARITHMETICAL AXIOMS OF TERNARY NOTATION f(+1, 0, -1) WITH THE FORMATION OF A RESULTING SUM [SΣ]f(2n) IN A POSITIONAL FORMAT |
RU2480815C1 (en) * | 2012-04-24 | 2013-04-27 | Лев Петрович Петренко | FUNCTIONAL FIRST INPUT STRUCTURE OF CONDITIONAL "j" BIT OF ADDER fCD(Σ)RU WITH MAXIMALLY MINIMISED PROCESS CYCLE ∆tΣ FOR ARGUMENTS OF TERMS ±[1,2nj]f(2n) AND ±[1,2mj]f(2n) OF "COMPLEMENTARY CODE RU" FORMAT WITH GENERATION OF INTERMEDIATE SUM (2Sj)1 d1/dn "LEVEL 2" AND (1Sj)1 d1/dn "LEVEL 1" OF FIRST TERM IN SAME FORMAT (VERSIONS OF RUSSIAN LOGIC) |
RU2480816C1 (en) * | 2012-04-24 | 2013-04-27 | Лев Петрович Петренко | FUNCTIONAL SECOND INPUT STRUCTURE OF CONDITIONAL "j" BIT OF ADDER fCD(Σ)RU WITH MAXIMALLY MINIMISED PROCESS CYCLE ∆tΣ FOR ARGUMENTS OF TERMS ±[1,2nj]f(2n) И ±[1,2mj]f(2n) OF "COMPLEMENTARY CODE RU" FORMAT WITH GENERATION OF INTERMEDIATE SUM ±[1,2Sj]1 d1/dn OF SECOND TERM IN SAME FORMAT (VERSIONS OF RUSSIAN LOGIC) |
-
2007
- 2007-12-17 RU RU2007146288/09A patent/RU2378682C2/en active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
RU2443008C1 (en) * | 2010-07-22 | 2012-02-20 | Лев Петрович Петренко | FUNCTIONAL STRUCTURE OF A TRANSFORMER OF PRELIMINARY FA fΣ [ni]&[mi](2n) OF PARALLEL-SERIAL MULTIPLICATOR fΣ (Σ) CONDITIONALLY, OF "i" DIGIT TO SUM UP OF POSITIONAL ADDITIVE OF SUMS [ni]f(2n) AND [mi]f(2n) OF PARTIAL PRODUCTS USING ARITHMETICAL AXIOMS OF TERNARY NOTATION f(+1, 0, -1) WITH THE FORMATION OF A RESULTING SUM [SΣ]f(2n) IN A POSITIONAL FORMAT |
RU2480815C1 (en) * | 2012-04-24 | 2013-04-27 | Лев Петрович Петренко | FUNCTIONAL FIRST INPUT STRUCTURE OF CONDITIONAL "j" BIT OF ADDER fCD(Σ)RU WITH MAXIMALLY MINIMISED PROCESS CYCLE ∆tΣ FOR ARGUMENTS OF TERMS ±[1,2nj]f(2n) AND ±[1,2mj]f(2n) OF "COMPLEMENTARY CODE RU" FORMAT WITH GENERATION OF INTERMEDIATE SUM (2Sj)1 d1/dn "LEVEL 2" AND (1Sj)1 d1/dn "LEVEL 1" OF FIRST TERM IN SAME FORMAT (VERSIONS OF RUSSIAN LOGIC) |
RU2480816C1 (en) * | 2012-04-24 | 2013-04-27 | Лев Петрович Петренко | FUNCTIONAL SECOND INPUT STRUCTURE OF CONDITIONAL "j" BIT OF ADDER fCD(Σ)RU WITH MAXIMALLY MINIMISED PROCESS CYCLE ∆tΣ FOR ARGUMENTS OF TERMS ±[1,2nj]f(2n) И ±[1,2mj]f(2n) OF "COMPLEMENTARY CODE RU" FORMAT WITH GENERATION OF INTERMEDIATE SUM ±[1,2Sj]1 d1/dn OF SECOND TERM IN SAME FORMAT (VERSIONS OF RUSSIAN LOGIC) |
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