JP2005326914A - Cmos adder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CMOS adder corresponding to sign digit numbers whose manufacturing can be realized by an inexpensive and normal CMOS process, and whose low power consumption can be realized. <P>SOLUTION: This CMOS adder is provided with a first adder 1 which inputs two input signals A and B based on the ternary sign digit numbers of "+1", "0" and "-1", and outputs a first addition signal S1, a first carry section 2 which inputs the two input signals A and B, and outputs a first carry signal C1, a second adding section 3 which inputs the signal S1 and a third carry signal Ci-1 before one bit, and outputs a second addition signal SUMi, a second carry section 4 which inputs the signal S1 and a first carry signal C1i-1 before one bit, and outputs a second carry signal C2 and a third adding section 5 which inputs the signal C1 and the signal C2, and outputs a third carry signal Ci. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a CMOS adder that inputs data of a ternary sign digit number and performs addition to output an addition signal and a carry signal of a ternary sign digit number.

An example of a conventional configuration of a main circuit of a digital signal CMOS adder using a multi-valued sign digit number is configured using an NMOS transistor or a PMOS transistor each having two or more threshold voltages, or A configuration example of a current mode circuit is known (Non-Patent Documents 1 and 2).
Two authors outside Matsumoto, “Design of four-valued logic circuit using MOS transistor and capacitor memory”, IEICE Transactions, Vol. J70-D, No. 1, pp. 50-59, January 1987 Two authors, Kameyama, 2nd, "Bidirectional current mode multi-value basic arithmetic circuit based on Signed-Digit number system and its evaluation", IEICE Transactions, Vol. 7, No. 71, 1189-1198, 1988 July

  However, a CMOS adder using an NMOS transistor or a PMOS transistor each having two or more multi-value threshold voltages cannot be manufactured by a normal CMOS process, resulting in a problem that the product cost becomes high. Further, in the configuration example of the current mode circuit, a static operating current is generated, and there is a problem that low power consumption is hindered when a large number are mounted on an LSI.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a CMOS adder corresponding to the number of sign digits that can solve the above-mentioned problems and can be manufactured by an inexpensive ordinary CMOS process and can realize low power consumption.

  The CMOS adder according to the first aspect of the present invention inputs the two input signals A and B based on the ternary sign digit number of “+1”, “0”, and “−1” to obtain the first addition signal S1. A first adder for outputting, a first carry for inputting the two input signals A and B and outputting the first carry signal C1, and a third carry one bit before the signal S1 A second adder that inputs a carry signal Ci-1 and outputs a second addition signal SUMi; a second adder that inputs the signal S1 and the first carry signal C1i-1 one bit before; A CMOS adder including a second carry unit that outputs a carry signal C2 and a third adder that inputs the signal C1 and the signal C2 and outputs a third carry signal Ci. The first addition signal S1 is “−1” when one of the input signals A and B is “+1” and the other is “0”. When one of the input signals A and B is “−1” and the other is “0”, it becomes “+1”, otherwise it becomes “0”, and the first carry signal C1 is the input signal A, B Is "+1" or one is "+1" and the other is "0", "+1", and both the input signals A and B are "-1" or one is "-1" and the other is "0" “−1”, otherwise “0”, the signal SUMi is “+1” when one of the signal S1 and the signal Ci−1 is “+1” and the other is “0”, and the signal S1 When one of the signals Ci-1 is "-1" and the other is "0", the signal Ci-1 is "-1", and when the other is "0", the signal C2 has both the signal S1 and the signal C1i-1 " "+1" when the signal S1 is "+1", "-1" when both the signal S1 and the signal C1i-1 are "-1", and "0" otherwise. Ci is “+1” when one of the signal C1 and the signal C2 is “+1” and the other is “0”, and when one of the signal C1 and the signal C2 is “−1” and the other is “0” It is characterized in that “−1” and “0” otherwise.

  According to a second aspect of the present invention, in the CMOS adder according to the first aspect, the first adder includes a voltage VDD0 corresponding to ternary sign digit numbers “−1”, “0”, “+1”. , VDD1, VDD2 (VDD0 <VDD1 <VDD2), and an input unit that inputs the two signals A and B and outputs the signal S1, and includes a terminal for the voltage VDD2 and a terminal for the signal S1. And a first series circuit composed of a series circuit of three PMOS transistors, and a first circuit composed of a series circuit of three PMOS transistors connected between the terminal of the voltage VDD2 and the terminal of the signal S1. 2 series circuit, a third series circuit composed of a series circuit of three NMOS transistors connected between the terminal of the voltage VDD0 and the terminal of the signal S1, and a terminal of the voltage VDD0 A fourth series circuit composed of a series circuit of three NMOS transistors connected between the terminal of the signal S1 and two PMOSs connected between the terminal of the voltage VDD1 and the terminal of the signal S1. A fifth series circuit composed of a series circuit of a transistor and two NMOS transistors; between the terminal of the voltage VDD1 and the terminal of the signal S1, one terminal side is two PMOS transistors and NMOS transistors, and the other is Also on the terminal side, there are two PMOS transistors and NMOS transistors, a total of four connected in series, and between the terminal of the voltage VDD1 and the terminal of the signal S1, one terminal side is the PMOS transistor and NMOS. Two transistors are connected in series, and the other terminal is connected in series with two PMOS transistors and NMOS transistors. And a seventh series circuit having a central connection point connected to a central connection point of the sixth series circuit, and the gate of each PMOS transistor of the first series circuit includes the signal A signal INVAB21 obtained by inverting the signal AB obtained by inverting the signal A by a CMOS inverter using VDD2 and VDD1 as a power source, the signal B, and the signal BB obtained by inverting the signal B are input to each PMOS transistor of the second series circuit. The signal INVBB21, the signal A, and the signal AB, which are obtained by inverting the signal BB with a CMOS inverter using VDD2 and VDD1 as power sources, are input to the gate of each of the NMOS transistors in the third series circuit. Is a signal INVAB10 obtained by inverting the signal AB with a CMOS inverter using VDD1 and VDD0 as power sources, The signal B and the signal BB are respectively input, and the signal INVBB10 obtained by inverting the signal BB with a CMOS inverter using the VDD1 and VDD0 as power supplies, and the signal A, the gate of each NMOS transistor of the fourth series circuit The signal AB is input, the signals INVAB10 and INVBB10 are respectively input to the gates of the two PMOS transistors of the fifth series circuit, and the signals INVAB21 and INVBB21 are respectively input to the gates of the two NMOS transistors. The signal A is input to the gate of the PMOS transistor on the terminal side of VDD1 of the sixth series circuit, the signal AB is input to the gate of the NMOS transistor, and the gate of the PMOS transistor on the terminal side of the signal S1. Is the signal B, NMOS transistor The signal BB is input to the gate of each of the transistors, the signal AB is input to the gate of the PMOS transistor on the VDD1 terminal side of the seventh series circuit, and the signal A is input to the gate of the NMOS transistor. The signal BB is input to the gate of the PMOS transistor on the terminal side of the signal S1, and the signal B is input to the gate of the NMOS transistor.

  According to a third aspect of the present invention, in the CMOS adder according to the first aspect, the first carry section is a voltage corresponding to a ternary sign digit number “−1”, “0”, “+1”. A carry unit that inputs two signals A and B of VDD0, VDD1, and VDD2 (VDD0 <VDD1 <VDD2) and outputs the signal C1, and includes the terminal of the voltage VDD2 and the signal C1. An eighth series circuit including a series circuit of two PMOS transistors connected between the terminals and a series circuit of three PMOS transistors connected between the terminal of the voltage VDD2 and the terminal of the signal C1. A tenth series circuit consisting of a series circuit of three PMOS transistors connected between the terminal of the voltage VDD2 and the terminal of the signal C1, and the voltage VDD0 An eleventh series circuit composed of a series circuit of two NMOS transistors connected between the signal and the terminal of the signal C1, and three terminals connected between the terminal of the voltage VDD0 and the terminal of the signal C1. A twelfth series circuit comprising a series circuit of NMOS transistors, a thirteenth series circuit comprising a series circuit of three NMOS transistors connected between the terminal of the voltage VDD0 and the terminal of the signal C1, and the voltage A fourteenth series circuit composed of a series circuit of two PMOS transistors and two NMOS transistors connected between the terminal of VDD1 and the terminal of signal C1, the terminal of voltage VDD1 and the terminal of signal C1; A fifteenth series circuit composed of a series circuit of two PMOS transistors and two NMOS transistors, and the voltage VDD1 Each of the PMOS transistors of the eighth series circuit, and a sixteenth series circuit comprising a series circuit of two PMOS transistors and two NMOS transistors connected between the terminal and the terminal of the signal C1 The signal INVA21 obtained by inverting the signal A by a CMOS inverter using VDD2 and VDD1 as a power source and the signal INVB21 obtained by inverting the signal B by a CMOS inverter using VDD2 and VDD1 as power sources are respectively input to the gates of The signal INVA21, the signal B, and the signal BB obtained by inverting the signal B are input to the gates of the PMOS transistors of the ninth series circuit, respectively, and the gates of the PMOS transistors of the tenth series circuit are The signal INVB21, the signal A, and the signal AB obtained by inverting the signal A are input. Then, the gate of each NMOS transistor of the eleventh series circuit has a signal INVA10 obtained by inverting the signal A by a CMOS inverter using VDD1 and VDD0 as power supplies, and a CMOS using the signal B as power supplies from VDD1 and VDD0. The signal INVB10 inverted by the inverter is input, and the signal INVA10, the signal B, and the signal BB are input to the gates of the NMOS transistors of the twelfth series circuit, respectively. The signal INVB10, the signal A, and the signal AB are respectively input to the gates of the NMOS transistors, and the signals INVA10 and INVB10 are respectively input to the gates of the two PMOS transistors of the fourteenth series circuit. The signal I is connected to the gates of the NMOS transistors. VA21 and INVB21 are respectively input, the signals A and BB are respectively input to the gates of the two PMOS transistors of the fifteenth series circuit, and the signals B and AB are respectively input to the gates of the two NMOS transistors. The signals B and AB are respectively input to the gates of the two PMOS transistors of the sixteenth series circuit, and the signals A and BB are respectively input to the gates of the two NMOS transistors. It is characterized by that.

  According to a fourth aspect of the present invention, in the CMOS adder according to the first aspect, the second or third adder corresponds to the number of ternary sign digits “−1”, “0”, “+1”. Two signals A and B of the voltages VDD0, VDD1 and VDD2 (VDD0 <VDD1 <VDD2) (where A is the signal S1, B is the signal Ci-1, or A is the signal C1, B) Is an adder that inputs the signal C2) and outputs the signal S2 (the signal SUMi or the signal Ci), and is connected between the terminal of the voltage VDD2 and the terminal of the signal S2, and three PMOSs A seventeenth series circuit comprising a series circuit of transistors, an eighteenth series circuit comprising a series circuit of three PMOS transistors connected between the terminal of the voltage VDD2 and the terminal of the signal S2, and the voltage VDD0 A nineteenth series circuit composed of a series circuit of three NMOS transistors connected between the terminal of the signal S2 and the terminal of the signal S2, and three terminals connected between the terminal of the voltage VDD0 and the terminal of the signal S2. A twentieth series circuit composed of a series circuit of NMOS transistors, and a twenty-first circuit composed of a series circuit of two PMOS transistors and two NMOS transistors connected between the terminal of the voltage VDD1 and the terminal of the signal S2. Between the terminal of the voltage VDD1 and the terminal of the signal S2, one terminal side is two PMOS transistors and NMOS transistors, and the other terminal side is two PMOS transistors and NMOS transistors. One terminal side between the 22nd series circuit connected in series and the terminal of the voltage VDD1 and the terminal of the signal S2 Two PMOS transistors and NMOS transistors, and the other terminal side is also connected in series with a total of four PMOS transistors and NMOS transistors, and the central connection point is connected to the central connection point of the twenty-second series circuit. A signal INVA21 obtained by inverting the signal A with a CMOS inverter using VDD2 and VDD1 as power sources, and the signal B at the gate of each PMOS transistor of the seventeenth series circuit. The signal BB obtained by inverting the signal B is input, and the signal INVB21 obtained by inverting the signal B with a CMOS inverter using the VDD2 and VDD1 as power sources is input to the gates of the PMOS transistors of the eighteenth series circuit. The 19th series circuit receives the signal A and the signal AB obtained by inverting the signal A, respectively. The signal INVA10, the signal B, and the signal BB obtained by inverting the signal A with a CMOS inverter using VDD1 and VDD0 as power sources are input to the gates of the NMOS transistors, respectively. A signal INVB10, the signal A, and the signal AB obtained by inverting the signal B with a CMOS inverter using VDD1 and VDD0 as power sources are input to the gates of the transistors, respectively, and the two PMOS transistors of the twenty-first series circuit The gates of the two transistors are the signals INVA10 and INVB10, respectively, and the gates of the two NMOS transistors are the signals INVA21 and INVB21, respectively. The gate of the PMOS transistor on the VDD1 terminal side of the twenty-second series circuit The signal A, NMOS transistor The signal AB is input to the gate of the star, the signal B is input to the gate of the PMOS transistor on the terminal side of the signal S2, and the signal BB is input to the gate of the NMOS transistor, respectively. The signal AB is input to the gate of the PMOS transistor on the terminal side of the VDD1 and the signal A is input to the gate of the NMOS transistor, and the signal BB and NMOS transistor are input to the gate of the PMOS transistor on the terminal side of the signal S2. It is characterized in that the signal B is inputted to each of the gates.

  According to a fifth aspect of the present invention, in the CMOS adder according to the first aspect, the second carry section is a voltage corresponding to a ternary sign digit number “−1”, “0”, “+1”. Input two signals A and B (VDD0 <VDD1 <VDD2) of VDD0, VDD1, and VDD2 (where A is the signal S1 and B is the signal C1i-1) and outputs the signal C2. 24th series circuit comprising a series circuit of two PMOS transistors connected between the terminal of the voltage VDD2 and the terminal of the signal C2, and the terminal of the voltage VDD0 and the signal C2 Of the two PMOS transistors connected between the terminal of the voltage VDD1 and the terminal of the signal C2. A column circuit and a 26th series circuit in which a parallel circuit of two NMOS transistors is connected in series. The signal A is supplied to the gates of the PMOS transistors of the 24th series circuit with the VDD2 and VDD1. A signal INVA21 inverted by a CMOS inverter used as a power source and a signal INVB21 inverted by a CMOS inverter using VDD2 and VDD1 as a power source are input to the signal B, and the gates of the NMOS transistors of the 25th series circuit are respectively A signal INVA10 obtained by inverting the signal A by a CMOS inverter using VDD1 and VDD0 as a power source, and a signal INVB10 obtained by inverting the signal B by a CMOS inverter using VDD1 and VDD0 as power sources are input. The gates of the two PMOS transistors Serial signal INVA10, INVB10 inputs respectively, to the gates of the two NMOS transistors, wherein said signal INVA21, INVB21 has to enter respectively, as.

  The CMOS adder of the present invention includes three adders and two carry units, and supports input signals A and B with ternary sign digit numbers “+1”, “0”, and “−1”. Then, an addition signal or a carry signal with ternary sign digit numbers “+1”, “0”, “−1” is output, and a circuit configuration for realizing this is a MOS transistor in which each transistor has one threshold value. Therefore, it can be manufactured by a cheap and normal process. Further, since the static operating current can be reduced, the power consumption can be reduced, and the number of MOS transistors to be configured is small. Therefore, when many LSIs are mounted, the chip area and power consumption of the LSI are not increased.

  In the CMOS adder of the present invention, a MOS transistor having one threshold value is used, and voltages VDD2, VDD1, VDD0 (VDD2> VDD1) corresponding to the number of sign digits “+1”, “0”, “−1”. > VDD0) is input and operated, and the addition signal and carry signal are output. VDD1 = (VDD2 + VDD0) / 2. This will be described in detail below. In the following, “MP” represents a PMOS transistor, and “MN” represents an NMOS transistor.

  FIG. 1A is a block diagram illustrating a configuration of a 1-bit full adder according to the first embodiment. In this embodiment, two signals A and B composed of ternary sign digit numbers “+1”, “0”, and “−1” are input signals. Ai and Bi are input signals of the ternary sign digit number of the i-th bit, Ci-1 is a carry input signal of 1 bit before, Ci is a carry signal of the i-th bit, and SUMi is an add signal of the i-th bit. is there. S1 is an intermediate addition signal, C1 (C1i) is an intermediate carry signal, and C1i-1 is an intermediate carry signal one bit before.

  Also, 1 is a first adder (SUM1) that inputs signals Ai and Bi and outputs an intermediate addition signal S1, and 2 is a first digit that inputs signals Ai and Bi and outputs an intermediate carry signal C1. A raising unit (CA1) 3 is a second adding unit (SUM2) that receives the signal S1 and the signal Ci-1 and outputs an addition signal SUMi, and 4 is an intermediate carry signal C1i-1 that is one bit before the signal S1. Is a second carry unit (CA2) that outputs a carry signal C2 and 5 is a third adder unit (SUM2) that receives signals C1 and C2 (C1i) and outputs a carry signal Ci. is there.

  FIG. 1B is a diagram showing a truth value of the 1-bit full adder of FIG. As is clear from FIG. 1B, the intermediate addition signal S1 is “−1” when one of the input signals A and B is “+1” and the other is “0”, and one of the input signals A and B is It is “+1” when “−1” and the other is “0”, and “0” otherwise. The intermediate carry signal C1 is “+1” when both the input signals A and B are “+1” or one is “+1” and the other is “0”, and both the input signals A and B are “−1” or one is “ "-1" and "0" when the other is "0", otherwise "0".

  The addition signal SUMi is “+1” when one of the intermediate addition signal S1 and the carry signal Ci−1 is “+1” and the other is “0”, and one of the intermediate addition signal S1 and the carry signal Ci-1 is “−”. It is “−1” when the other is “0” and “0”, and “0” otherwise. The carry signal C2 is “+1” when the intermediate addition signal S1 and the intermediate carry signal C1i-1 one bit before are both “+1”, and both the intermediate addition signal S1 and the intermediate carry signal C1i-1 are “−1”. "-1" when "", and "0" otherwise. The carry signal Ci is “+1” when one of the intermediate carry signal C1 and the carry signal C2 is “+1” and the other is “0”, and one of the intermediate carry signal C1 and the carry signal C2 is “−1”. ”And“ 0 ”when the other is“ 0 ”, and“ 0 ”otherwise.

  In this way, the second and third adders 3 and 5 perform operations different from those of the first adder 1. Further, the second carry unit 4 performs an operation different from that of the first carry unit. When paying attention to the carry signal C2 of the second carry unit 4 in FIG. 1B, the carry signal Ci propagated to the upper digit is determined by the intermediate carry signal C1, and the carry signal Ci- Do not propagate 1 For this reason, when the full adders configured as shown in FIG. 1A are connected in multiple stages, propagation of the carry signal to the upper digit can be suppressed, and the calculation speed can be increased.

  FIG. 2A is a circuit diagram showing a configuration of the first addition unit (SUM1) 1 in FIG. The power supply voltages VDD2, VDD1, and VDD0 corresponding to the ternary sign digit numbers “+1”, “0”, and “−1” are, for example, VDD2 = 1.8V, VDD1 = 0.9V, and VDD0 = 0V.

  A series circuit of transistors MP1 to MP3 and a series circuit of transistors MP4 to MP6 are connected between the output terminal of the intermediate addition signal S1 and the power supply terminal of VDD2. A series circuit of transistors MN1 to MN3 and a series circuit of transistors MN4 to MN6 are connected between the output terminal of the intermediate addition signal S1 and the power supply terminal of VDD0, respectively. Further, a series circuit of transistors MP7, MP8, MN7, MN8 is connected between the output terminal of the intermediate addition signal S1 and the power supply terminal of VDD1, and further, a series circuit of transistors MP9, MN9, MP10, MN10 is connected. Further, a series circuit of transistors MP11, MN11, MP12, and MN12 is connected, and a common connection point of the transistors MN9 and MP10 is connected to a common connection point of the transistors MN11 and MP12.

  As signals applied to the gates of the respective transistors, A is the above-described signal, AB is the inverted signal of the signal A, B is the above-described signal, and BB is the inverted signal of the signal B. Further, INVAB21 is a signal obtained by inverting signal AB by a CMOS inverter composed of transistors MP101 and MN101 having the configuration shown in FIG. 6A using VDD2 and VDD1 as power supply voltages. Similarly, INVBB21 is a signal obtained by inverting the signal BB. Further, INVAB10 is a signal obtained by inverting the signal AB by a CMOS inverter composed of the transistors MP102 and MN102 having the configuration shown in FIG. 6B using VDD1 and VDD0 as power supply voltages. Similarly, INVBB10 is a signal obtained by inverting the signal BB.

  FIG. 2B is an explanatory diagram showing the truth value of the operation of the first addition unit (SUM1) 1 in FIG. When the input signal A is “−1” and B is “0”, the transistors MP1 to MP3 are all on and the intermediate addition signal S1 is “+1”. When the input signal A is “0” and B is “−1”, the transistors MP4 to MP6 are all turned on and the intermediate addition signal S1 becomes “+1”.

  When the input signal A is “+1” and B is “0”, the transistors MN1 to MN3 are all on and the intermediate addition signal S1 is “−1”. When the input signal A is “0” and B is “+1”, the transistors MN4 to MN6 are all turned on and the intermediate addition signal S1 is “−1”.

  When the combination of the input signals A and B is other than that, the transistors MP1 to MP6 and MN1 to MN6 are all turned off. When the input signal A is “0” and B is “0”, the transistors MP7, MP8, MN7, MN8 are all turned on and the intermediate addition signal S1 becomes “0”. When the input signal A is “−1” and B is “−1”, the transistors MP9, MN9, MP10, and MN10 are all turned on and the intermediate addition signal S1 becomes “0”. When the input signal A is “+1” and B is “+1”, the transistors MP11, MN11, MP12, and MN12 are all turned on and the intermediate addition signal S1 becomes “0”. When the input signal A is “−1” and B is “+1”, the transistors MP9, MN9, MP12, and MN12 are all turned on and the intermediate addition signal S1 becomes “0”. When the input signal A is “+1” and B is “−1”, the transistors MP11, MN11, MP10, and MN10 are all turned on and the intermediate addition signal S1 becomes “0”.

  FIG. 3A is a circuit diagram showing a configuration of the first carry part (CA1) 2 in FIG. A series circuit of transistors MP13 and MP14, a series circuit of transistors MP15 to MP17, and a series circuit of transistors MP18 to MP20 are connected between the output terminal of the intermediate carry signal C1 and the power supply terminal of VDD2. Further, a series circuit of transistors MN13 and MN14, a series circuit of transistors MN15 to MN17, and a series circuit of transistors MN18 to MN20 are connected between the output terminal of the intermediate carry signal C1 and the power supply terminal of VDD0, respectively. Yes. Further, between the output terminal of the intermediate carry signal C1 and the power supply terminal of VDD1, a series circuit of transistors MP21, MP22, MN21, MN22, a series circuit of transistors MP23, MN23, MP24, MN24, transistors MP25, MN25, A series circuit of MP26 and MN26 is connected to each other.

  As signals applied to the gates of the respective transistors, A, AB, B, and BB are the signals described above. Further, INVA21 is a signal obtained by inverting the signal A by a CMOS inverter composed of the transistors MP103 and MN103 having the configuration shown in FIG. 6C using VDD2 and VDD1 as power supply voltages. Similarly, INVB21 is a signal obtained by inverting the signal B. Further, INVA10 is a signal obtained by inverting the signal A by a CMOS inverter composed of the transistors MP104 and MN104 having the configuration shown in FIG. 6D using VDD1 and VDD0 as power supply voltages. Similarly, INVB10 is a signal obtained by inverting the signal B.

  FIG. 3B is an explanatory diagram showing the truth value of the operation of the first carry section (CA1) 2 of FIG. When the input signals A and B are “+1”, both the transistor MP13 and the transistor MP14 are turned on, and the intermediate carry signal C1 is “+1”. Also, when the input signal A is “+1” and B is “0”, the transistors MP15 to MP17 are all turned on and the intermediate carry signal C1 becomes “+1”. Also, when the input signal A is “0” and B is “+1”, the transistors MP18 to MP20 are all turned on and the intermediate carry signal C1 becomes “+1”.

  When the input signal A is “−1” and B is “−1”, both the transistor MN13 and the transistor MN14 are turned on, and the intermediate carry signal C1 becomes “−1”. When the input signal A is “−1” and B is “0”, the transistors MN15 to MN17 are all turned on and the intermediate carry signal C1 becomes “−1”. When the input signal A is “0” and B is “−1”, the transistors MN18 to MN20 are all turned on and the intermediate carry signal C1 is “−1”.

  When both the combinations of the input signals A and B are “0” or “+1” and “−1”, the transistors MP13 to MP20 and MN13 to MN20 are all turned off. When the input signal A is “0” and B is “0”, the transistors MP21, MP22, MN21, and MN22 are all turned on and the intermediate carry signal C1 is “0”. When the input signal A is “−1” and B is “+1”, the transistors MP23, MN23, MP24, and MN24 are all on and the intermediate carry signal C1 is “0”. When the input signal A is “+1” and B is “−1”, the transistors MP25, MN25, MP26, and MN26 are all on and the intermediate carry signal C1 is “0”.

  FIG. 4A is a circuit diagram showing the configuration of the second and third addition units (SUM2) 3 and 5 in FIG. A series circuit of transistors MP27 to MP29 and a series circuit of transistors MP30 to MP32 are connected between the output terminal of the addition signal S2 and the power supply terminal of VDD2. A series circuit of transistors MN27 to MN29 and a series circuit of transistors MN30 to MN32 are connected between the output terminal of the addition signal S2 and the power supply terminal of VDD0. Further, a series circuit of transistors MP33, MP34, MN33, MN34 is connected between the output terminal of the addition signal S2 and the power supply terminal of VDD1, and further, a series circuit of transistors MP35, MN35, MP36, MN36 is connected. Further, a series circuit of transistors MP37, MN37, MP38, and MN38 is connected, and a common connection point of the transistors MN35 and MP36 is connected to a common connection point of the transistors MN37 and MP38.

  As signals applied to the gates of the respective transistors, A, AB, B, BB, INVA21, INVB21, INVA10, and INVB10 are the same as those described with reference to FIG. However, the signals A and B here correspond to the signal S1 and the signal Ci-1 in FIG. 1A in the case of the second adder 3, and the signals C1 and C2 in the case of the third adder 5. It corresponds to.

  FIG. 4B is an explanatory diagram showing the truth values of the operations of the second and third addition units (SUM2) 3 and 5 in FIG. When the input signal A is “+1” and B is “0”, the transistors MP27 to MP29 are all turned on and the addition signal S2 becomes “+1”. When the input signal A is “0” and B is “+1”, the transistors MP30 to MP32 are all turned on and the addition signal S2 becomes “+1”.

  When the input signal A is “−1” and B is “0”, the transistors MN27 to MN29 are all turned on and the addition signal S2 becomes “−1”. Also, when the input signal A is “0” and B is “−1”, the transistors MN30 to MN32 are all turned on and the addition signal S2 becomes “−1”.

  When the combination of the input signals A and B is other than that, the transistors MP27 to MP32 and MN27 to MN32 are all turned off. When the input signal A is “0” and B is “0”, the transistors MP33, MP34, MN33, and MN34 are all turned on and the addition signal S2 becomes “0”. When the input signal A is “−1” and B is “−1”, the transistors MP35, MN35, MP36, and MN36 are all turned on and the addition signal S2 becomes “0”. When the input signal A is “+1” and B is “+1”, the transistors MP37, MN37, MP38, and MN38 are all turned on and the addition signal S2 becomes “0”. When the input signal A is “−1” and B is “+1”, the transistors MP35, MN35, MP38, and MN38 are all turned on and the addition signal S2 becomes “0”. Further, when the input signal A is “+1” and B is “−1”, the transistors MP37, MN37, MP36, and MN36 are all turned on and the addition signal S2 becomes “0”.

  FIG. 5A is a circuit diagram showing a configuration of the carry section (CA2) 4 in FIG. A series circuit of transistors MP39 and MP40 is connected between the output terminal of the carry signal C2 and the power supply terminal of VDD2. A series circuit of a transistor MN39 and a transistor MN40 is connected to the output terminal of the carry signal C2 and the power supply terminal of VDD0. Further, a series circuit in which a parallel circuit of transistors MN41 and MN42 and a parallel circuit of transistors MP41 and MP42 are connected in series is connected between the output terminal of the carry signal C2 and the power supply terminal of VDD1.

  As signals applied to the gates of the respective transistors, INVA21, INVB21, INVA10, and INVB10 are the same as those described with reference to FIG. However, the signals A and B here correspond to the signal S1 and the signal C1i-1 in FIG.

  FIG. 5B is an explanatory diagram showing the truth value of the operation of the second carry section (CA2) 4 in FIG. When the input signals A and B are “+1”, both the transistors MP39 and MP40 are turned on, and the carry signal C2 becomes “+1”. When the input signals A and B are “−1”, the transistors MN39 and MN40 are both turned on and the carry signal C2 becomes “−1”.

  When the combination of the input signals A and B is other than that, the transistors MP39, MP40, MN39, and MN40 are all turned off. When the input signal A is “+1” and B is “0”, both the transistors MN41 and MP42 are turned on and the carry signal C2 becomes “0”. When the input signal A is “0” and B is “+1”, both the transistors MN41 and MP41 are turned on and the carry signal C2 becomes “0”. When the input signal A is “0” and B is “0”, the transistors MN41, MP41, MN42, and MP42 are all turned on and the carry signal C2 becomes “0”. When the input signal A is “0” and B is “−1”, both the transistors MN41 and MP41 are turned on, and the carry signal C2 becomes “0”. When the input signal A is “−1” and B is “0”, both the transistors MN42 and MP42 are turned on and the carry signal C2 becomes “0”. When the input signal A is “−1” and B is “+1”, both the transistors MN41 and MP42 are turned on, and the carry signal C2 becomes “0”. When the input signal A is “+1” and B is “−1”, both the transistors MN42 and MP41 are turned on and the carry signal C2 becomes “0”.

(a) is a block diagram of the CMOS adder according to the first embodiment, and (b) is an explanatory diagram showing a truth value during the operation. (a) is a block diagram of the first addition unit (SUM1) 1 of the second embodiment, and (b) is an explanatory diagram showing a truth value during the operation. (a) is a block diagram of the first carry part (CA1) 2 of the third embodiment, and (b) is an explanatory diagram showing a truth value during the operation. (a) is a block diagram of the second and third addition units (SUM2) 3 and 5 of the fourth embodiment, and (b) is an explanatory diagram showing a truth value during the operation. (a) is a block diagram of the second carry part (CA2) 4 of the fifth embodiment, and (b) is an explanatory diagram showing a truth value during the operation. (a)-(d) is a circuit diagram of a CMOS inverter.

Explanation of symbols

1: 1st addition part (SUM1)
2: First carry part (CA1)
3: Second addition unit (SUM2)
4: Second carry part (CA2)
5: Third adder (SUM2)

Claims (5)

A first adder that inputs two input signals A and B based on a ternary sign digit number of “+1”, “0”, and “−1” and outputs a first addition signal S1;
A first carry unit that inputs the two input signals A and B and outputs a first carry signal C1;
A second adder that inputs the signal S1 and a third carry signal Ci-1 one bit before and outputs a second addition signal SUMi;
A second carry unit that inputs the signal S1 and the first carry signal C1i-1 one bit before and outputs a second carry signal C2;
A CMOS adder comprising a third adder that inputs the signal C1 and the signal C2 and outputs a third carry signal Ci;
The first addition signal S1 is “−1” when one of the input signals A and B is “+1” and the other is “0”, and one of the input signals A and B is “−1” and the other is “1”. “+1” when “0”, “0” otherwise,
The first carry signal C1 is “+1” when both the input signals A and B are “+1” or one is “+1” and the other is “0”, and both the input signals A and B are “−1”. "Or" -1 "when one is" 0 "and the other is" 0 ", otherwise" 0 "
The signal SUMi is "+1" when one of the signal S1 and the signal Ci-1 is "+1" and the other is "0", and one of the signal S1 and the signal Ci-1 is "-1" and the other "-1" when is "0", "0" otherwise,
The signal C2 is “+1” when both the signal S1 and the signal C1i−1 are “+1”, “−1” when both the signal S1 and the signal C1i-1 are “−1”, and otherwise. “0”,
The signal Ci is “+1” when one of the signal C1 and the signal C2 is “+1” and the other is “0”, one of the signal C1 and the signal C2 is “−1”, and the other is “0”. "-1" for, "0" otherwise
A CMOS adder characterized by being configured as described above. The CMOS adder according to claim 1, wherein the first adder is
Two signals A and B of voltages VDD0, VDD1 and VDD2 (VDD0 <VDD1 <VDD2) corresponding to ternary sign digit numbers “−1”, “0” and “+1” are input and An adder for outputting a signal S1,
A first series circuit comprising a series circuit of three PMOS transistors connected between the terminal of the voltage VDD2 and the terminal of the signal S1;
A second series circuit comprising a series circuit of three PMOS transistors connected between the terminal of the voltage VDD2 and the terminal of the signal S1;
A third series circuit comprising a series circuit of three NMOS transistors connected between the terminal of the voltage VDD0 and the terminal of the signal S1;
A fourth series circuit comprising a series circuit of three NMOS transistors connected between the terminal of the voltage VDD0 and the terminal of the signal S1;
A fifth series circuit composed of a series circuit of two PMOS transistors and two NMOS transistors connected between the terminal of the voltage VDD1 and the terminal of the signal S1,
Between the terminal of the voltage VDD1 and the terminal of the signal S1, one terminal side is connected in series with two PMOS transistors and NMOS transistors, and the other terminal side is connected in series with two PMOS transistors and NMOS transistors. A sixth series circuit;
Between the terminal of the voltage VDD1 and the terminal of the signal S1, one terminal is connected in series with two PMOS transistors and NMOS transistors, and the other terminal is connected in series with two PMOS transistors and NMOS transistors. And a seventh series circuit having a central connection point connected to a central connection point of the sixth series circuit,
At the gate of each PMOS transistor of the first series circuit, signal INVAB21 obtained by inverting signal AB obtained by inverting signal A by a CMOS inverter using VDD2 and VDD1 as power sources, signal B, and signal B are inverted. Each signal BB is input,
The signal INVBB21, the signal A, and the signal AB obtained by inverting the signal BB with a CMOS inverter using VDD2 and VDD1 as power sources are input to the gates of the PMOS transistors of the second series circuit,
The signal INVAB10, the signal B, and the signal BB obtained by inverting the signal AB with a CMOS inverter that uses the VDD1 and VDD0 as power sources are input to the gates of the NMOS transistors of the third series circuit, respectively.
The signal INVBB10, the signal A, and the signal AB obtained by inverting the signal BB with a CMOS inverter using VDD1 and VDD0 as power sources are input to the gates of the NMOS transistors of the fourth series circuit,
The signals INVAB10 and INVBB10 are input to the gates of the two PMOS transistors of the fifth series circuit, respectively, and the signals INVAB21 and INVBB21 are input to the gates of the two NMOS transistors, respectively.
The signal A is input to the gate of the PMOS transistor on the VDD1 terminal side of the sixth series circuit, the signal AB is input to the gate of the NMOS transistor, and the gate of the PMOS transistor on the terminal side of the signal S1. The signal B and the signal BB are input to the gates of the NMOS transistor,
The signal AB is input to the gate of the PMOS transistor on the terminal side of the VDD1 in the seventh series circuit, the signal A is input to the gate of the NMOS transistor, and the gate of the PMOS transistor on the terminal side of the signal S1. The signal B is input to the signal BB and the gate of the NMOS transistor, respectively.
A CMOS adder characterized by being configured as described above. The CMOS adder according to claim 1, wherein the first carry section is
Two signals A and B of voltages VDD0, VDD1 and VDD2 (VDD0 <VDD1 <VDD2) corresponding to ternary sign digit numbers “−1”, “0” and “+1” are input and A carry unit for outputting a signal C1,
An eighth series circuit comprising a series circuit of two PMOS transistors connected between the terminal of the voltage VDD2 and the terminal of the signal C1;
A ninth series circuit comprising a series circuit of three PMOS transistors connected between the terminal of the voltage VDD2 and the terminal of the signal C1;
A tenth series circuit comprising a series circuit of three PMOS transistors connected between the terminal of the voltage VDD2 and the terminal of the signal C1;
An eleventh series circuit comprising a series circuit of two NMOS transistors connected between the terminal of the voltage VDD0 and the terminal of the signal C1;
A twelfth series circuit comprising a series circuit of three NMOS transistors connected between the terminal of the voltage VDD0 and the terminal of the signal C1;
A thirteenth series circuit comprising a series circuit of three NMOS transistors connected between the terminal of the voltage VDD0 and the terminal of the signal C1;
A fourteenth series circuit comprising a series circuit of two PMOS transistors and two NMOS transistors connected between the terminal of the voltage VDD1 and the terminal of the signal C1;
A fifteenth series circuit comprising a series circuit of two PMOS transistors and two NMOS transistors connected between the terminal of the voltage VDD1 and the terminal of the signal C1;
A sixteenth series circuit comprising a series circuit of two PMOS transistors and two NMOS transistors connected between the terminal of the voltage VDD1 and the terminal of the signal C1;
The gate of each PMOS transistor of the eighth series circuit is a signal INVA21 obtained by inverting the signal A with a CMOS inverter using VDD2 and VDD1 as power sources, and the signal B is a CMOS inverter using VDD2 and VDD1 as power sources. Each inverted signal INVB21 is input,
The signal INVA21, the signal B, and the signal BB obtained by inverting the signal B are input to the gates of the PMOS transistors of the ninth series circuit,
The signal INVB21, the signal A, and the signal AB obtained by inverting the signal A are input to the gates of the PMOS transistors of the tenth series circuit,
The gate of each NMOS transistor of the eleventh series circuit is a signal INVA10 obtained by inverting the signal A with a CMOS inverter using VDD1 and VDD0 as power sources, and the signal B is a CMOS inverter using VDD1 and VDD0 as power sources. Each inverted signal INVB10 is input,
The signal INVA10, the signal B, and the signal BB are input to the gates of the NMOS transistors of the twelfth series circuit,
The signal INVB10, the signal A, and the signal AB are respectively input to the gates of the NMOS transistors of the thirteenth series circuit,
The signals INVA10 and INVB10 are respectively input to the gates of the two PMOS transistors of the fourteenth series circuit, and the signals INVA21 and INVB21 are respectively input to the gates of the two NMOS transistors.
The signals A and BB are respectively input to the gates of the two PMOS transistors of the fifteenth series circuit, and the signals B and AB are respectively input to the gates of the two NMOS transistors.
The signals B and AB are respectively input to the gates of the two PMOS transistors of the sixteenth series circuit, and the signals A and BB are respectively input to the gates of the two NMOS transistors.
A CMOS adder characterized by being configured as described above. 2. The CMOS adder according to claim 1, wherein the second or third adder is:
Two signals A and B of voltages VDD0, VDD1 and VDD2 (VDD0 <VDD1 <VDD2) corresponding to ternary sign digit numbers “−1”, “0” and “+1” (where A is The signals S1 and B are signals Ci-1, or A is the signal C1 and B is the signal C2), and the signal S2 (the signal SUMi or the signal Ci) is output.
A seventeenth series circuit comprising a series circuit of three PMOS transistors connected between the voltage VDD2 terminal and the signal S2 terminal;
An eighteenth series circuit comprising a series circuit of three PMOS transistors connected between the terminal of the voltage VDD2 and the terminal of the signal S2.
A nineteenth series circuit comprising a series circuit of three NMOS transistors connected between the terminal of the voltage VDD0 and the terminal of the signal S2.
A twentieth series circuit composed of a series circuit of three NMOS transistors connected between the terminal of the voltage VDD0 and the terminal of the signal S2,
A twenty-first series circuit comprising a series circuit of two PMOS transistors and two NMOS transistors connected between the terminal of the voltage VDD1 and the terminal of the signal S2,
Between the terminal of the voltage VDD1 and the terminal of the signal S2, one terminal side is connected in series with two PMOS transistors and NMOS transistors, and the other terminal side is connected in series with two PMOS transistors and NMOS transistors. A twenty-second series circuit;
Between the terminal of the voltage VDD1 and the terminal of the signal S2, one terminal side is connected in series with two PMOS transistors and NMOS transistors, and the other terminal side is connected with two PMOS transistors and NMOS transistors, for a total of four, And a 23rd series circuit having a central connection point connected to a central connection point of the 22nd series circuit,
The signal INVA21 obtained by inverting the signal A by a CMOS inverter using VDD2 and VDD1 as a power source, the signal B, and the signal BB obtained by inverting the signal B are input to the gates of the PMOS transistors of the seventeenth series circuit, respectively. And
A signal INVB21 obtained by inverting the signal B by a CMOS inverter using VDD2 and VDD1 as a power source, the signal A, and a signal AB obtained by inverting the signal A are input to the gates of the PMOS transistors of the eighteenth series circuit, respectively. And
The signal INVA10, the signal B, and the signal BB obtained by inverting the signal A with a CMOS inverter using the VDD1 and VDD0 as power sources are input to the gates of the NMOS transistors of the nineteenth series circuit,
The signal INVB10, the signal A, and the signal AB obtained by inverting the signal B with a CMOS inverter using the VDD1 and VDD0 as power sources are input to the gates of the NMOS transistors of the twentieth series circuit, respectively.
The signals INVA10 and INVB10 are input to the gates of the two PMOS transistors of the twenty-first series circuit, respectively, and the signals INVA21 and INVB21 are input to the gates of the two NMOS transistors, respectively.
The signal A is input to the gate of the PMOS transistor on the terminal side of the VDD1 in the twenty-second series circuit, the signal AB is input to the gate of the NMOS transistor, and the gate of the PMOS transistor on the terminal side of the signal S2. The signal B and the signal BB are input to the gates of the NMOS transistor,
The signal AB is input to the gate of the PMOS transistor on the terminal side of the VDD1 in the 23rd series circuit, the signal A is input to the gate of the NMOS transistor, and the gate of the PMOS transistor on the terminal side of the signal S2. The signal B is input to the signal BB and the gate of the NMOS transistor, respectively.
A CMOS adder characterized by being configured as described above. 2. The CMOS adder according to claim 1, wherein the second carry section is
Two signals A and B of voltages VDD0, VDD1 and VDD2 (VDD0 <VDD1 <VDD2) corresponding to ternary sign digit numbers “−1”, “0” and “+1” (where A is The signals S1 and B are carry units for inputting the signal C1i-1) and outputting the signal C2,
A 24th series circuit comprising a series circuit of two PMOS transistors connected between the terminal of the voltage VDD2 and the terminal of the signal C2,
A 25th series circuit comprising a series circuit of two NMOS transistors connected between the terminal of the voltage VDD0 and the terminal of the signal C2,
A 26th series circuit in which a parallel circuit of two PMOS transistors and a parallel circuit of two NMOS transistors connected in series are connected between the terminal of the voltage VDD1 and the terminal of the signal C2. ,
The gate of each PMOS transistor of the twenty-fourth series circuit is a signal INVA21 obtained by inverting the signal A with a CMOS inverter using VDD2 and VDD1 as a power source, and the signal B is a CMOS inverter using VDD2 and VDD1 as power sources. Each inverted signal INVB21 is input,
The gate of each NMOS transistor of the twenty-fifth series circuit is a signal INVA10 obtained by inverting the signal A by a CMOS inverter using VDD1 and VDD0 as power supplies, and the signal B is a CMOS inverter using VDD1 and VDD0 as power supplies. Each inverted signal INVB10 is input,
The signals INVA10 and INVB10 are input to the gates of the two PMOS transistors of the 26th series circuit, respectively, and the signals INVA21 and INVB21 are input to the gates of the two NMOS transistors, respectively.
A CMOS adder characterized by being configured as described above.

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