JP4444044B2 - CMOS driver circuit and CMOS inverter circuit - Google Patents

Description

  The present invention relates to a CMOS driver circuit that performs waveform shaping by inputting ternary sign digit number data and a CMOS inverter circuit that performs signal inversion simultaneously with waveform shaping.

As a conventional configuration example of a CMOS driver circuit that handles a digital signal using a multi-valued sign digit number, an example in which NMOS transistors or PMOS transistors each having two or more threshold voltages are used, or a current mode circuit (See, for example, Non-Patent Documents 1 and 2).
Matsumoto, et al., “Design of 4-level logic circuit using MOS transistor and capacitor memory”, IEICE Transactions, Vol. J70-D, No. 1, pp. 50-59, January 1987 Kameyama, et al., “Bidirectional current-mode multivalued basic arithmetic circuit based on Signd-Digit number system and its evaluation”, Journal of Electronic Information and Communications, Vol. J71-D, No. 7, pp. 1189-1198 , July 1988

  However, a CMOS driver circuit using an NMOS transistor or a PMOS transistor each having two or more multi-value threshold voltages cannot be manufactured by a normal CMOS process, resulting in a problem that the product cost becomes high. Further, in the configuration example of the current mode circuit, a static operating current is generated, and there is a problem that low power consumption is hindered when many are mounted on the LSI.

  An object of the present invention is to provide a CMOS driver circuit which solves the above problems and can be manufactured by a low-cost ordinary CMOS process and has a low power consumption and corresponds to the number of sign digits. Another object is to provide a CMOS inverter circuit having similar characteristics by developing the CMOS driver circuit.

  The invention according to claim 1 is a CMOS driver circuit for inputting any one of voltages VDD0, VDD1 and VDD2 (VDD0 <VDD1 <VDD2) corresponding to the number of ternary sign digits, and shaping and outputting the waveform. The first inverter (INV1) connected between the power supply terminal of VDD2 and the power supply terminal of VDD1 and having the input side connected to the input terminal, and between the power supply terminal of VDD1 and the power supply terminal of VDD0 A second inverter (INV2) connected and connected on the input side to the input terminal, a first precharging PMOS transistor (MP4) connected in parallel between the power supply terminal and the output terminal of the VDD1, and a second 1 precharging NMOS transistor (MN4) and connected in series between the power supply terminal of VDD2 and the output terminal. A second precharging PMOS transistor (MP5) and an output PMOS transistor (MP3), a second precharging NMOS transistor (MN5) connected between the power supply terminal of VDD0 and the output terminal, and An output NMOS transistor (MN3), an output side of the first inverter (INV1) is connected to a gate of the output PMOS transistor (MP3), and an output side of the second inverter (INV2) is the output. The first precharge control terminal (CK) is connected to the gate of the first precharge PMOS transistor (MP4) and the second precharge NMOS transistor (MN5). A second precharge control terminal (C B) is connected to the gate of the first precharging NMOS transistor (MN4) and the gate of the second precharging PMOS transistor (MP5), and when the first precharge control terminal (CK) is precharged The voltage of VDD0 is controlled to the voltage of VDD2 at the time of non-precharging, and the second precharge control terminal (CKB) is controlled to the voltage of VDD2 at the time of precharging and to the voltage of VDD0 at the time of non-precharging. It is characterized by that.

  The invention according to claim 2 is a CMOS inverter circuit that inputs any one of voltages VDD0, VDD1, and VDD2 (VDD0 <VDD1 <VDD2) corresponding to the number of ternary sign digits, shapes the waveform, inverts it, and outputs it. A first inverter (INV3) connected between the power supply terminal of VDD2 and the power supply terminal of VDD1 and having an input side connected to the input terminal; and the power supply terminal of VDD1 and the power supply terminal of VDD0 A second inverter (INV4) whose input side is connected to the input terminal, and a first precharging PMOS transistor (MP10) connected in parallel between the power supply terminal of VDD1 and the output terminal And between the first precharge NMOS transistor (MN10) and the power supply terminal of VDD2 and the output terminal. A line-connected output PMOS transistor (MP9), an output NMOS transistor (MN9) connected between the power supply terminal of VDD0 and the output terminal, and the input terminal and output NMOS transistor (MN9). A transfer PMOS transistor (MP8) connected between the gate, a transfer NMOS transistor (MN8) connected between the input terminal and the gate of the output PMOS transistor (MP9), and the VDD2 A second precharging PMOS transistor (MP11) connected between a power supply terminal and the gate of the output PMOS transistor (MP9), a power supply terminal of VDD0 and a gate of the output NMOS transistor (MN9); The second precharging NMOS transistor (MN 1), the output side of the first inverter (INV3) is connected to the gate of the transfer PMOS transistor (MP8), and the output side of the second inverter (INV4) is connected to the transfer NMOS transistor (MN8). ), The first precharge control terminal (CK) is connected to the gate of the first precharge PMOS transistor (MP10) and the gate of the second precharge PMOS transistor (MP11), A second precharge control terminal (CKB) is connected to the gate of the first precharge NMOS transistor (MN10) and the gate of the second precharge NMOS transistor (MN11), and the first precharge control terminal (CKB) is connected. When the terminal (CK) is precharged, the voltage is VDD0 or VDD1. The second precharge control terminal (CKB) is controlled to a voltage of VDD2 or VDD1 at the time of precharge and to a voltage of VDD0 at the time of non-precharge. Features.

  The CMOS driver circuit and the CMOS inverter circuit of the present invention can be manufactured by a low-cost normal process because each transistor only needs to be a MOS transistor having one threshold value. In addition, since the number of MOS transistors required for the configuration is small, the power consumption is small, and when many LSI transistors are mounted, the chip area and power consumption of the LSI are not increased.

  In the CMOS driver circuit of the present invention, ten MOS transistors having one threshold value are used, and voltages VDD2, VDD1, VDD0 (VDD2) corresponding to the sign digit numbers “+1”, “0”, “−1” are used. > VDD1> VDD0) to shape the waveform. In the CMOS inverter circuit, 12 MOS transistors having one threshold value are used, and the same voltage is input to perform waveform shaping and signal inversion. This will be described in detail below.

  FIG. 1 is a circuit diagram showing a configuration of a CMOS driver circuit according to the first embodiment. In this embodiment, VDD2, VDD1, and VDD0 are prepared as power supply voltages corresponding to ternary sign digit numbers “+1”, “0”, and “−1”, respectively. For example, VDD2 = 1.8V, VDD1 = 0.9V, and VDD0 = 0V. The CMOS driver circuit of the present embodiment is configured such that an input signal based on the number of sign digits is waveform-shaped and any one of the above-described VDD2, VDD1, and VDD0 is output as an output signal. Hereinafter, “MP” represents a PMOS transistor, and “MN” represents an NMOS transistor.

  INV1 and INV2 are CMOS inverters whose input sides are commonly connected to the input terminal IN. The inverter INV1 includes transistors MP1 and MN1 using VDD2 and VDD1 as power supply voltages, and the inverter INV2 includes transistors MP2 and MN2 using VDD1 and VDD0 as power supply voltages. A series circuit of an output transistor MP3 and a precharge transistor MP5 is connected between the power supply terminal of VDD2 and the output terminal OUT. A series circuit of an output transistor MN3 and a precharge transistor MN5 is connected between the power supply terminal VDD0 and the output terminal OUT. Further, precharging transistors MP4 and MN4 are connected in parallel between the power supply terminal of VDD1 and the output terminal OUT. The output side of the inverter INV1 is connected to the gate of the transistor MP3, and the output side of the inverter INV2 is connected to the gate of the transistor MN3. A precharge control terminal CK is connected to the gates of the precharge transistors MP4 and MN5, and a precharge signal CKB is connected to the gates of the precharge transistors MN4 and MP5.

  When the precharge control terminals CK and CKB are CK = “− 1” and CKB = “+ 1”, the precharge transistors MP4 and MN4 are turned on, so that the output terminal OUT has a signal level “0” (= Precharged to VDD1). At this time, the precharging transistors MP5 and MN5 are turned off and no power supply voltage is applied to the output transistors MP3 and MN3.

  After the precharge is completed, the precharge control terminals CK and CKB change to CK = “+ 1” and CKB = “− 1”, the precharge transistors MP4 and MN4 are turned off, and the precharge transistors MP5 and MP5 are turned off. Since MN5 conducts, the power supply voltage is applied to the output transistors MP3 and MN3. At this time, the outputs of the inverters INV1 and INV2 control the gates of the output transistors MP3 and MN3.

  When the input terminal IN is “+1”, the output of the inverter INV1 is “0”, the output of the inverter INV2 is “−1”, the output transistor MP3 is turned on, and the output transistor MN3 is turned off. Thus, “+1” is output to the output terminal OUT.

  When the input terminal IN is “−1”, the output of the inverter INV1 is “+1”, the output of the inverter INV2 is “0”, the output transistor MP3 becomes non-conductive, and the output transistor MN3 becomes conductive. Accordingly, “−1” is output to the output terminal OUT.

  Further, when the input terminal IN is “0”, the output of the inverter INV1 is “+1”, the output of the inverter INV2 is “−1”, the output transistors MP3 and MN3 are both non-conductive, and the output terminal OUT is precharged. Does not change from “0”.

  As described above, the MOS driver circuit of this embodiment, when a signal having a sign digit number of “+1”, “0”, “−1” is input, the waveform is shaped and “+1”, “0”, “ -1 "is output as a signal having a sign digit number. FIG. 2 shows the truth value of the operation of this MOS driver circuit.

  Since the CMOS driver circuit of this embodiment is a MOS transistor in which each transistor has one threshold value, it can be manufactured by an inexpensive ordinary process. In addition, since the number of MOS transistors constituting the circuit is as small as 10, the power consumption is small, and when a large number of MOS transistors are mounted on the LSI, the chip area and power consumption of the LSI are not increased.

  FIG. 3 is a circuit diagram showing a configuration of the CMOS inverter circuit according to the second embodiment. INV3 and INV4 are CMOS inverters whose input sides are commonly connected to the input terminal IN. The inverter INV3 includes transistors MP6 and MN6 that use VDD2 and VDD1 as power supply voltages, and the inverter INV4 includes transistors MP7 and MN7 that use VDD1 and VDD0 as power supply voltages. MP9 is an output transistor connected between the power supply VDD2 and the output terminal OUT, and MN9 is an output transistor connected between the power supply VDD0 and the output terminal OUT. A transfer transistor MP8 is connected between the input terminal IN and the gate of the output transistor MN9, and a transfer transistor MN8 is connected between the input terminal IN and the output transistor MP9. The output side of the inverter INV3 is connected to the gate of the transfer transistor MP8, and the output side of the inverter INV4 is connected to the gate of the transfer transistor MN8. Further, precharging transistors MP10 and MN10 are connected in parallel between the power supply terminal of VDD1 and the output terminal OUT. A precharge transistor MP11 is connected between the power supply terminal of VDD2 and the gate of the output transistor MP9, and a precharge transistor MN11 is connected between the power supply terminal of VDD0 and the gate of the output transistor MN9. Has been. A precharge control terminal CK is connected to the gates of the precharge transistors MP10 and MP11, and a precharge control terminal CKB is connected to the gates of the precharge transistors MN10 and MN11.

  When the precharge control terminals CK and CKB are CK = “− 1” or “0” and CKB = “+ 1” or “0”, the precharge transistors MP10, MP11, MN10, and MN11 are turned on. The output terminal OUT is precharged to the signal level “0” (= VDD1). At this time, the output transistors MP9 and MN9 are turned off.

  After the precharge is completed, the precharge control terminals CK and CKB change to CK = “+ 1” and CKB = “− 1”, and the precharge transistors MP10, MP11, MN10, and MN11 become non-conductive and output The transistors MP9 and MN9 can accept the voltages from the transistors MP8 and MN8.

  When the input terminal IN is “+1”, the output of the inverter INV3 is “0”, the output of the inverter INV4 is “−1”, the transfer transistor MP8 is turned on, and the transfer transistor MN8 is turned off. Therefore, the output transistor MN9 becomes conductive, the output transistor MP9 becomes nonconductive, and “−1” is output to the output terminal OUT.

  When the input terminal IN is “−1”, the output of the inverter INV3 is “+1”, the output of the inverter INV4 is “0”, the transfer transistor MP8 becomes non-conductive, and the transfer transistor MN8 becomes conductive. Therefore, the output transistor MP9 becomes conductive, the output transistor MN9 becomes nonconductive, and “+1” is output to the output terminal OUT.

  Further, when the input terminal IN is “0”, the output of the inverter INV3 is “+1”, the output of the inverter INV4 is “−1”, the transfer transistors MP8 and MN8 are both non-conductive, and the output transistors MP9, Both MN9s become non-conductive, and the output terminal OUT does not change from the precharged “0”.

  As described above, in the MOS inverter circuit according to the present embodiment, when a signal having the number of sign digits of “+1”, “0”, and “−1” is input, the waveform is shaped and inverted to “−1”, “ It is output as a signal with the sign digit number of “0” and “+1”. FIG. 4 shows the truth value of the operation of this CMOS inverter circuit.

  Since the CMOS inverter circuit of this embodiment is a MOS transistor in which each transistor has one threshold value, it can be manufactured by an inexpensive ordinary process. In addition, since the number of MOS transistors constituting the circuit is as small as 12, the power consumption is small, and when a large number of MOS transistors are mounted on the LSI, the chip area and power consumption of the LSI are not increased.

3 is a circuit diagram of a CMOS driver circuit according to Embodiment 1. FIG. FIG. 6 is an explanatory diagram of truth values of the operation of the CMOS driver circuit according to the first embodiment. 6 is a circuit diagram of a CMOS inverter circuit of Example 2. FIG. It is explanatory drawing of the truth value of operation | movement of the CMOS inverter circuit of Example 2. FIG.

Claims (2)

A CMOS driver circuit that inputs any one of voltages VDD0, VDD1, and VDD2 (VDD0 <VDD1 <VDD2) corresponding to the number of ternary sign digits, shapes the waveform, and outputs the signal.
A first inverter connected between the power supply terminal of VDD2 and the power supply terminal of VDD1 and having an input side connected to the input terminal, and connected between the power supply terminal of VDD1 and the power supply terminal of VDD0 and the input side connected A second inverter connected to the input terminal; a first precharge PMOS transistor and a first precharge NMOS transistor connected in parallel between the power supply terminal of the VDD1 and the output terminal; A second precharging PMOS transistor and an output PMOS transistor connected in series between the power supply terminal of VDD2 and the output terminal, and a second connected between the power supply terminal of VDD0 and the output terminal. A precharging NMOS transistor and an output NMOS transistor,
The output side of the first inverter is connected to the gate of the output PMOS transistor, the output side of the second inverter is connected to the gate of the output NMOS transistor, and a first precharge control terminal is connected to the first PMOS transistor. The gate of the precharge PMOS transistor and the gate of the second precharge NMOS transistor are connected, and the second precharge control terminal is the gate of the first precharge NMOS transistor and the second precharge PMOS transistor. Connected to the gate of
The first precharge control terminal is controlled to a voltage of VDD0 during precharge, a voltage of VDD2 during non-precharge, the second precharge control terminal is controlled to a voltage of VDD2 during precharge, and VDD0 during non-precharge. A CMOS driver circuit characterized by being controlled by a voltage of. A CMOS inverter circuit that inputs any one of voltages VDD0, VDD1, and VDD2 (VDD0 <VDD1 <VDD2) corresponding to the number of ternary sign digits, shapes the waveform, inverts it, and outputs it.
A first inverter connected between the power supply terminal of VDD2 and the power supply terminal of VDD1 and having an input side connected to the input terminal, and connected between the power supply terminal of VDD1 and the power supply terminal of VDD0 and the input side connected A second inverter connected to the input terminal; a first precharge PMOS transistor and a first precharge NMOS transistor connected in parallel between the power supply terminal of the VDD1 and the output terminal; An output PMOS transistor connected between the power supply terminal of VDD2 and the output terminal, an output NMOS transistor connected between the power supply terminal of VDD0 and the output terminal, the input terminal, and the output A transfer PMOS transistor connected between the gate of the NMOS transistor, the input terminal and the output P A transfer NMOS transistor connected between the gate of the OS transistor, a second precharge PMOS transistor connected between the power supply terminal of the VDD2 and the gate of the output PMOS transistor, and the VDD0 A second precharging NMOS transistor connected between a power supply terminal and the gate of the output NMOS transistor;
The output side of the first inverter is connected to the gate of the transfer PMOS transistor, the output side of the second inverter is connected to the gate of the transfer NMOS transistor, and a first precharge control terminal is connected to the first PMOS transistor. The gate of the precharge PMOS transistor and the gate of the second precharge PMOS transistor are connected, and the second precharge control terminal is the gate of the first precharge NMOS transistor and the second precharge NMOS transistor. Connected to the gate of
The first precharge control terminal is controlled to a voltage of VDD0 or VDD1 when precharged, is controlled to a voltage of VDD2 when not precharged, and the second precharge control terminal is controlled to a voltage of VDD2 or VDD1 when precharged. A CMOS inverter circuit characterized by being controlled to a voltage of VDD0 during precharging.

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