JP4370229B2 - CMOS logic circuit - Google Patents

Description

  The present invention inputs a plurality of signals selected from voltages VDD0, VDD1, and VDD2 (VDD0 <VDD1 <VDD2) corresponding to ternary sign digit numbers “−1”, “0”, and “+1” and performs a logical operation. The present invention relates to a CMOS logic circuit that outputs the data.

An example of a conventional configuration example of a main circuit of a CMOS logic circuit of a digital signal using a multi-valued sign digit number is configured by using an NMOS transistor or a PMOS transistor each having two or more threshold voltages, or A configuration example of a current mode circuit is known (for example, see Non-Patent Documents 1 and 2).
Matsumoto, et al., “Design of 4-level logic circuit using MOS transistor and capacitor memory”, IEICE Transactions, Vol. J70-D, No. 1, pp. 50-59, January 1987 Kameyama, et al., “Bidirectional current mode multivalued basic arithmetic circuit based on Signd-Digit number system and its evaluation”, IEICE Transactions, Vol.7, No.7, 1189-1198 Mitsugu, July 1988

  However, a CMOS logic circuit using NMOS transistors and PMOS transistors each having two or more multi-value threshold voltages cannot be manufactured by a normal CMOS process, resulting in a problem that the product cost is high. Further, in the configuration example of the current mode circuit, a static operating current is generated, and there is a problem that power consumption is hindered when a large number of LSIs are mounted on the LSI.

  An object of the present invention is to provide a CMOS logic circuit that solves the above problems and can be manufactured by an inexpensive ordinary CMOS process and has a low power consumption and corresponds to the number of sign digits.

  The CMOS logic circuit of the invention according to claim 1 is a signal selected from voltages VDD0, VDD1, VDD2 (VDD0 <VDD1 <VDD2) corresponding to ternary sign digit numbers “−1”, “0”, “+1”. Is a CMOS logic circuit that inputs a plurality of signals and outputs a logical operation, and a first precharging PMOS transistor (MPSW2) connected between a power supply terminal and an output terminal of the VDD2 and a plurality of the signals Is connected between the power supply terminal of VDD0 and the output terminal, and a series circuit composed of a first logic block (10) composed of a plurality of PMOS transistors that inputs a calculation result to the output terminal. A plurality of NMOs that receive the first precharge NMOS transistor (MNSW0) and a plurality of the signals and output the operation results to the output terminal A series circuit comprising a second logic block (20) comprising transistors, a second precharging PMOS transistor (MPSW1) connected in parallel between the power supply terminal and the output terminal of the VDD1, and a second A precharge NMOS transistor (MNSW1), and the first precharge PMOS transistor (MPSW2) and the first precharge NMOS transistor (MNSW0) are non-conductive during precharge and conductive during non-precharge. The second precharging PMOS transistor (MPSW1) and the second precharging NMOS transistor (MNSW1) are controlled to be conductive when precharged and nonconductive when not precharged. To do.

  According to a second aspect of the present invention, in the CMOS logic circuit according to the first aspect, as the plurality of signals inputted to the first logic block, the number of ternary sign digits “−1”, “0”, The signal * that is one of the voltages VDD0, VDD1, and VDD2 corresponding to “+1”, the inverted signal * B of the signal *, and the first CMOS inverter that operates using the VDD2 and the VDD1 as power supply voltages. The signal INV * 21 obtained by inputting * and the signal INV * B21 obtained by inputting the inverted signal * B to the second CMOS inverter that operates using the VDD2 and VDD1 as power supply voltages are used. As the plurality of signals input to the logic block, the signal *, the inverted signal * B of the signal *, the VDD1 and the VDD0 are used as power supply voltages. A signal INV * 10 obtained by inputting the signal * to the third CMOS inverter, and a signal obtained by inputting the inverted signal * B to the fourth CMOS inverter that operates using the VDD1 and VDD0 as power supply voltages. INV * B10 is used.

  According to the CMOS logic circuit of the present invention, each transistor only needs to be a MOS transistor having one threshold value, so that it can be manufactured by an inexpensive ordinary process. In addition, since the static operating current can be reduced, less power is consumed, and the number of MOS transistors is small and the logic design is easy to automate. When many LSIs are mounted, the chip area and power consumption of the LSI The product design can be completed in a short time without increasing the cost.

  In the CMOS logic circuit of the present invention, a MOS transistor having one threshold value is used, and voltages VDD0, VDD1, VDD2 (corresponding to ternary sign digit numbers “−1”, “0”, “+1”) Calculation is performed by inputting a plurality of signals of VDD0 <VDD1 <VDD2), and the calculation result is output. This will be described in detail below. In the following, “MP” represents a PMOS transistor, and “MN” represents an NMOS transistor.

FIG. 1 is a circuit diagram showing a configuration of a CMOS logic circuit according to the first embodiment. In this embodiment, VDD2, VDD1, and VDD0 are prepared as power supply voltages corresponding to ternary sign digit numbers “+1”, “0”, and “−1”, respectively. For example, VDD2 = 1.8V, VDD1 = 0.9V, VDD0 = 0V. In FIG. 1, 10 is an input signal IN1 based on the number of sign digits . , INN are also a first logic block composed of PMOS transistors for inputting similar signals and calculating them, and 20 is a second logic block composed of similar NMOS transistors. The output sides of the first and second logic blocks 10 and 20 are connected to a common output terminal OUT.

  The signal * described above is a ternary sign digit number “+1”, “0”, or “−1”, the signal * B is an inverted signal of the signal *, and the signal INV * 21 is VDD2. The signal INV * B21 is a signal obtained by inputting the signal * to the first CMOS inverter that operates with the power supply voltage of VDD1 and VDD1, and the signal INV * B21 receives the inverted signal * B for the second CMOS inverter that operates with the power supply voltage of VDD2 and VDD1. The signal INV * 10 is a signal obtained by inputting the signal * to the third CMOS inverter that operates using VDD1 and VDD0 as power supply voltages. The signal INV * B10 is obtained by using VDD1 and VDD0 as power supply voltages. This is a signal obtained by inputting the inverted signal * B to the fourth CMOS inverter operating as.

  In FIG. 1, INVPS2 and INVPS1 are precharge CMOS inverters that operate using VDD2 and VDD1 or VDD0 as power supply voltages. The signals of the first precharge control terminal CK controlled to "+1" or "-1" Reverse transfer. INVNS0 and INVNS1 are precharge CMOS inverters that operate using VDD2 or VDD1 and VDD0 as power supply voltages, and are controlled to be “−1” or “+1” in a reverse phase relationship with the first precharge control terminal CK. The signal of the precharge control terminal CKB is inverted and transferred. MPSW2 is a first precharging PMOS transistor, MNSW0 is a first precharging NMOS transistor, MPSW1 is a second precharging PMOS transistor, and MNSW1 is a second precharging NMOS transistor. The transistors MPSW1 and MNSW2 are connected between the power supply terminal of VDD1 and the output terminal OUT, the transistor MPSW2 is connected between the power supply terminal of VDD2 and the first logic block 10, and the transistor MNSW0 is connected to the power supply terminal of VDD0 and the second power supply terminal. Each is connected to the logic block 20.

  When the first precharge control signal CK is “−1” and the second precharge control signal CKB is “+1”, the precharge transistors MPSW1 and MNSW1 are turned on and the output terminal OUT is set to “0”. Precharge to (VDD1). At this time, the precharging transistors MPSW2 and MNSW0 are non-conductive, and the power supply voltage VDD2 or VDD0 is not applied to the first logic block 10 and the second logic block 20.

  After the output terminal OUT is precharged to “0”, the first precharge control signal CK changes to “+1”, the second precharge control signal CKB changes to “−1”, and the precharge transistors MPSW1, MNSW1 becomes non-conductive, precharge transistors MPSW2 and MNSW0 become conductive, and the power supply voltage of VDD2 or VDD0 is applied to the first logic block 10 and the second logic block 20, respectively.

Next, when the input signal *, * B, INV * 21, INV * B21, INV * 10, INV * B10 is input, a conduction path is formed in the logic block 10, and no conduction path is formed in the logic block 20. The output terminal OUT becomes “+1” (= VDD2).

In addition, when the input signal *, * B, INV * 21, INV * B21, INV * 10, INV * B10 is input, a conduction path is formed in the logic block 20, and no conduction path is formed in the logic block 10. The output terminal OUT becomes “−1” (= VDD0).

Furthermore, when the input signal *, * B, INV * 21, INV * B21, INV * 10, INV * B10 is input , no conduction path is formed in the logic block 10 and no conduction path is formed in the logic block 20. In the output terminal OUT, precharged “0” (= VDD1) is held.

  As described above, in the CMOS logic circuit of this embodiment, after the output terminal OUT is precharged to “0”, the input signals *, * B, INV * 21, INV * B21, INV * 10, and INV * B10 are used. , “+1”, “0”, “−1” by inputting an arbitrary signal within the number of sign digits, the conduction path formation / non-conduction path formation of the first and second logic blocks 10 and 20 is performed. Depending on the combination, a dynamic operation in which a signal having a sign digit number of “−1”, “0”, or “+1” is output from the output terminal OUT is performed, so that high-speed and high-precision calculation is possible.

  Since the CMOS logic circuit of this embodiment is a MOS transistor in which each transistor has one threshold value, it can be manufactured by an inexpensive ordinary process. In addition, since the number of MOS transistors to be configured is small and power consumption can be reduced, when many LSI transistors are mounted, the chip area and power consumption of the LSI are not increased.

  FIG. 2A is a block diagram illustrating a configuration of a 1-bit full adder according to the second embodiment. In this embodiment, two signals Ai and Bi, which are any of ternary sign digit numbers “+1”, “0”, and “−1”, are used as input signals. Ai and Bi are input signals of the ternary sign digit number of the i-th bit, Ci-1 is a carry input signal from the previous bit, Ci is a carry signal of the i-th bit, and SUMi is an addition signal of the i-th bit. It is. S1 is an intermediate addition signal, C2 is an intermediate carry signal, C1i-1 is an intermediate carry signal from the previous bit, and C1i (C1) is an i-th intermediate carry signal.

  Reference numeral 1 denotes a first adder (SUM1) that inputs signals Ai and Bi and outputs a signal S1. Reference numeral 2 denotes a first carry unit that inputs signals Ai and Bi and outputs a signal C1i (C1). (CA1) 3 is a second adder (SUM2) that inputs the signal S1 and the signal Ci-1 and outputs the signal SUMi (S2), and 4 is the signal S1 and the signal C1i-1 that are input. The second carry part (CA2) 5 for output is a third adder part (SUM2) for inputting the signal C1i (C1) and the signal C2 and outputting the signal Ci, and each is described in the first embodiment. It is composed of a CMOS logic circuit.

  FIG. 2B is a diagram showing a truth value of the 1-bit full adder of FIG. 2A. As is apparent from FIG. 2B, the intermediate addition signal S1 is “−1” when one of the two signals Ai and Bi is “+1” and the other is “0”, and one of the signals Ai and Bi is “−1”. ”And“ 0 ”when the other is“ 0 ”, and“ 0 ”otherwise.

  The carry part signal C1 is “+1” when both the signals Ai and Bi are “+1” or one is “+1” and the other is “0”, and both the signals Ai and Bi are “−1” or one is “−1”. ”And“ 0 ”when the other is“ 0 ”, and“ 0 ”otherwise.

  The addition signal SUMi is “+1” when one of the intermediate addition signal S1 and the intermediate carry signal Ci−1 from the lower bit is “+1” and the other is “0”, and the intermediate addition signal S1 and the intermediate digit from the lower bit When one of the raising signals C1i-1 is “−1” and the other is “0”, it is “−1”, and otherwise it is “0”.

  The carry signal C2 is “+1” when both the intermediate addition signal S1 and the lower intermediate carry signal C1i-1 are “+1”, and both the intermediate addition signal S1 and the lower intermediate addition signal C1i-1 are “−”. “-1” when “1”, and “0” otherwise.

  The carry signal Ci is “+1” when one of the intermediate carry signal C2 and the intermediate carry signal C1i (C1) is “+1” and the other is “0”, and the intermediate carry signal S1 and the intermediate carry signal C1i ( When one of C1) is “−1” and the other is “0”, it is “−1”, and otherwise “0”.

  Thus, the second and third adders 3 and 5 perform different operations from the first adder 1. Further, the second carry unit 4 performs an operation different from that of the first carry unit 2. When paying attention to the carry signal C2 of the second carry unit 4 in FIG. 2B, the carry signal Ci propagated to the upper digit is determined by the carry signal C1i, and the carry signal Ci-1 from the lower bit is propagated. I won't let you. For this reason, when the full adders configured as shown in FIG. 2A are connected in multiple stages, propagation of the carry signal to the upper digit can be suppressed and the calculation speed can be increased.

  FIG. 3A is a circuit diagram in which the first addition unit (SUM1) 1 in FIG. 2A is configured by the CMOS logic circuit described in the first embodiment of FIG. The power supply voltages VDD2, VDD1, and VDD0 corresponding to the ternary sign digit numbers “+1”, “0”, and “−1” are, for example, VDD2 = 1.8V, VDD1 = 0.9V, and VDD0 = 0V. In relation to FIG. 2A, description will be made assuming that signals Ai = A and Bi = B. Also, the same components as those in FIG.

  The first logic block 10 in this embodiment includes a series circuit of transistors MP1 to MP3 connected between the precharging transistor MPSW2 and the output terminal of the intermediate addition signal S1, and a series circuit of transistors MP4 to MP6. It is configured. The second logic block 20 includes a series circuit of transistors MN1 to MN3 connected between the precharging transistor MNSW0 and the output terminal of the intermediate addition signal S1, and a series circuit of transistors MN4 to MN6. ing.

  As signals applied to the gates of the respective transistors, A is the above-described signal, AB is the inverted signal of the signal A, B is the above-described signal, and BB is the inverted signal of the signal B. Further, INVAB21 is a signal obtained by inverting the signal AB by a CMOS inverter composed of the transistors MP101 and MN101 having the configuration shown in FIG. 7A using VDD2 and VDD1 as power supply voltages. Similarly, INVBB21 is a signal obtained by inverting the signal BB. Further, INVAB10 is a signal obtained by inverting the signal AB by a CMOS inverter composed of the transistors MP102 and MN102 having the configuration shown in FIG. 7B using VDD1 and VDD0 as power supply voltages. Similarly, 1NVBBIO is a signal obtained by inverting the signal BB.

  FIG. 3B is an explanatory diagram showing the truth value of the operation of the first addition unit (SUM1) 1 in FIG. 3A. When the input signal A is “−1” and B is “0”, the PMOS transistors MP1 to MP3 are all turned on and the intermediate addition signal S1 becomes “+1”. When the input signal A is “0” and B is “−1”, the PMOS transistors MP4 to MP6 are all turned on and the intermediate addition signal S1 becomes “+1”.

  When the input signal A is “+1” and B is “0”, the NMOS transistors MN1 to MN3 are all turned on and the intermediate addition signal S1 becomes “−1”. When the input signal A is “0” and B is “+1”, the NMOS transistors MN4 to MN6 are all turned on and the intermediate addition signal S1 becomes “−1”.

  When the combination of the input signals A and B is other than that, the transistors MP1 to MP6 and MN1 to MN6 are all turned off, and the signal level “0” (VDD1) precharged in advance to the output terminal of the intermediate addition signal S1 is held. Is done.

  4A is a circuit diagram in which the first carry part (CA1) 2 in FIG. 2A is configured by the CMOS logic circuit described in the first embodiment of FIG. In relation to FIG. 2A, description will be made assuming that signals Ai = A and Bi = B. Also, the same components as those in FIG.

  The first logic block 10 in this embodiment includes a series circuit of transistors MP7 to MP8 connected between the precharging transistor MPSW2 and the output terminal of the intermediate carry signal C1, and a series circuit of transistors MP9 to MP11. And a series circuit of transistors MP12 to MP14. The second logic block 20 includes a series circuit of transistors MN7 to MN8, a series circuit of transistors MN9 to MN11 connected between the precharging transistor MNSW0 and the output terminal of the intermediate carry signal C1, and a transistor It consists of a series circuit of MN12 to MN14.

  As signals applied to the gates of the respective transistors, A, AB, B, and BB are the signals described above. Further, INVA21 is a signal obtained by inverting signal A by a CMOS inverter composed of transistors MP103 and MN103 having the configuration shown in FIG. 7C using VDD2 and VDD1 as power supply voltages. Similarly, INVB21 is a signal obtained by inverting the signal B. Further, INVA10 is a signal obtained by inverting the signal A by a CMOS inverter composed of the transistors MP104 and MN104 having the configuration shown in FIG. 7D using VDD1 and VDD0 as voltage voltages. Similarly, INVB10 is a signal obtained by inverting the signal B.

  FIG. 4B is an explanatory diagram showing the truth value of the operation of the first carry section (CA1) 2 of FIG. 4A. When the signals A and B are “+1”, the transistors MP7 and MP8 are both turned on, and the intermediate carry signal C1 becomes “+1”. When the signal A is “+1” and B is “0”, the transistors MP9 to MP11 are all turned on and the carry signal C1 becomes “+1”. Also, when the signal A is “0” and B is “+1”, the transistors MP12 to MP14 are all turned on and the intermediate carry signal C1 becomes “+1”.

  When the signal A is “−1” and B is “−1”, the transistors MN7 and MN8 are both turned on and the intermediate carry signal C1 becomes “−1”. When the signal A is “−1” and B is “0”, the transistors MN9 to MN11 are all turned on and the intermediate carry signal C1 becomes “−1”. When the signal A is “0” and B is “−1”, the transistors MN12 to MN14 are all turned on, and the intermediate carry signal C1 becomes “−1”.

  In other combinations of signals A and B, the transistors MP7 to MP14 and MN7 to MN14 are all turned off. Therefore, the signal level “0” (VDD1) precharged in advance at the output terminal of the intermediate carry signal C1 is held.

  FIG. 5A is a circuit diagram in which the second addition unit (SUM2) 3 in FIG. 2A is configured by the CMOS logic circuit described in the first embodiment of FIG. In relation to FIG. 2A, description will be made assuming that signals S1 = A and Ci-1 = B. Also, the same components as those in FIG. The third addition unit (SUM2) 4 has the same configuration.

  The first logic block 10 in this embodiment includes a series circuit of transistors MP15 to MP17 connected between the precharging transistor MPSW2 and the output terminal of the addition signal S2, and a series circuit of transistors MP18 to MP20. Has been. The second logic block 20 includes a series circuit of transistors MN15 to MN17 connected between the precharging transistor MNSW0 and the output terminal of the addition signal S2, and a series circuit of transistors MN18 to MN20. Yes.

  FIG. 5B is an explanatory diagram showing the truth value of the operation of the second addition unit (SUM2) 3 in FIG. 5A. When the signal A is “+1” and B is “0”, the PMOS transistors MP15 to MP17 are all turned on, and the addition signal S2 becomes “+1”. Also when the signal A is “0” and B is “+1”, the PMOS transistors MP18 to MP20 are all turned on, and the addition signal S2 becomes “+1”.

  When the signal A is “−1” and B is “0”, the NMOS transistors MN15 to MN17 are all turned on, and the addition signal S2 becomes “−1”. Also, when the input signal A is “0” and B is “−1”, the NMOS transistors MN18 to MN20 are all turned on, and the addition signal S2 becomes “−1”.

  In other combinations of signals A and B, the transistors MP15 to MP20 and MN15 to MN20 are all turned off. Therefore, the signal level “0” (VDD1) precharged in advance at the output terminal of the addition signal S2 is held.

  6A is a circuit diagram in which the second carry part (CA2) 4 in FIG. 2A is configured by the CMOS logic circuit described in the first embodiment of FIG. In relation to FIG. 2A, description will be made assuming that signals S1 = A and C1i-1 = B. Also, the same components as those in FIG.

  The first logic block 10 in this embodiment is composed of a series circuit of transistors MP21 to MP22 connected between the precharging transistor MPSW2 and the output terminal of the carry signal C2. The second logic block 20 is composed of a series circuit of transistors MN21 to MN22 connected between the precharging transistor MNSW0 and the output terminal of the carry signal C2.

  As signals applied to the gates of the respective transistors, INVA21, INVB21, INVA10, and INVB10 are the same as described above.

  FIG. 6B is an explanatory diagram showing the truth value of the operation of the second carry section (CA2) 4 of FIG. 6A. When the signals A and B are “+1”, the transistors MP21 to MP22 are all turned on, and the carry signal C2 becomes “+1”. When the signals A and B are “−1”, the transistors MN21 to MN22 are all turned on, and the carry signal C2 becomes “−1”.

  When the combination of signals A and B is other than that, the transistors MP21, MP22, MN21, and MN22 are all turned off. Therefore, the signal level “0” (VDD1) precharged in advance at the output terminal of the addition signal C2 is held.

1 is a circuit diagram of a CMOS logic circuit of Example 1. FIG. 6 is a block diagram of a full adder according to Embodiment 2. FIG. It is explanatory drawing which shows the truth value at the time of operation | movement of the full adder of Example 2. FIG. FIG. 10 is a block diagram of a first addition unit (SUM1) in Embodiment 3. It is explanatory drawing which shows the truth value at the time of operation | movement of the 1st addition part (SUM1) of Example 3. FIG. It is a block diagram of the 1st carry part (CA1) of Example 4. It is explanatory drawing which shows the truth value at the time of operation | movement of the 1st carry part (CA1) of Example 4. FIG. FIG. 10 is a block diagram of a second addition unit (SUM2) of Example 5. It is explanatory drawing which shows the truth value of the 2nd addition part (SUM2) of Example 5. FIG. It is a block diagram of the 2nd carry part (CA2) of Example 6. It is explanatory drawing which shows the truth value at the time of operation | movement of the 2nd carry part (CA2) of Example 6. FIG. (a)-(d) is a circuit diagram of a CMOS inverter.

Explanation of symbols

10: 1st logic block 20: 2nd logic block 1: 1st addition part (SUM1)
2: First carry part (CA1)
3: Second addition unit (SUM2)
4: Second carry part (CA2)
5: Third adder (SUM2)

Claims (2)

CMOS that inputs a plurality of signals selected from voltages VDD0, VDD1, and VDD2 (VDD0 <VDD1 <VDD2) corresponding to ternary sign digit numbers “−1”, “0”, and “+1”, and outputs them by performing a logical operation. A logic circuit,
A first precharging PMOS transistor connected between the power supply terminal and the output terminal of the VDD2 and a plurality of PMOS transistors for inputting a plurality of the signals and outputting a calculation result to the output terminal. A series circuit consisting of a logic block of
A first precharge NMOS transistor connected between the power supply terminal of VDD0 and the output terminal, and a plurality of NMOS transistors that input the plurality of signals and output the operation result to the output terminal. A series circuit composed of two logic blocks;
A second precharge PMOS transistor and a second precharge NMOS transistor connected in parallel between the power supply terminal of the VDD1 and the output terminal;
The first precharging PMOS transistor and the first precharging NMOS transistor are controlled to be non-conductive at the time of precharging and to be conductive at the time of non-precharging,
The second precharge PMOS transistor and the second precharge NMOS transistor are controlled to be conductive when precharged and nonconductive when not precharged.
A CMOS logic circuit characterized by that. The CMOS logic circuit of claim 1, wherein
The signal that is one of voltages VDD0, VDD1, and VDD2 corresponding to the ternary sign digit numbers “−1”, “0”, and “+1” as the plurality of signals that are input to the first logic block * An inverted signal * B of the signal *, a signal INV * 21 obtained by inputting the signal * to a first CMOS inverter that operates using the VDD2 and VDD1 as power supply voltages, and the VDD2 and VDD1 as power supplies. A signal INV * B21 obtained by inputting the inverted signal * B to the second CMOS inverter operating as a voltage,
As the plurality of signals to be input to the second logic block, the signal *, an inverted signal * B of the signal *, and a third CMOS inverter that operates using the VDD1 and the VDD0 as power supply voltages. A signal INV * 10 obtained by inputting * and a signal INV * B10 obtained by inputting the inverted signal * B to a fourth CMOS inverter that operates using the VDD1 and VDD0 as power supply voltages,
A CMOS logic circuit characterized by that.

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