JP6524374B2 - Multi-value numerical discriminant circuit, multi-value OR logic discriminant circuit based on the principle of fuse algebra, and multi-level AND logic discriminant circuit based on the principle of fuse algebra - Google Patents

Description

◆ ◆ ◆ title of the Inventions ◆ ◆ ◆
◆ ◆ “Circuit for differentiating fixed one of the numerical-values used in maltivalue (d) circuits”,
◆ ◆ “Circuit for differentiating maltival OR logic based on the principles of Hooji algebra”,
◆ ◆ and “Circuit for differentiating maltival and logic based on the principles of Hooji algebra”,

■ ■ ■ ■ ■ ■ ■ technology field
The first aspect of the invention (claim 1) relates to “compare with the conventional multi-value numerical value discrimination circuit, and the resistance such as“ resistance or [transistor in resistance mode ”] is used as the component means from“ the input terminal to the output terminal Since all the constituent means can be constituted only by a normally-off gate insulation type transistor [eg, MOS, FET, etc.] in the switching mode like CMOS.FET, it is unnecessary to use the means. The present invention relates to a "multi-value numerical discrimination circuit" which can also save power consumption in a steady state.
The multi-value numerical discrimination circuit of the first invention can also be used as a numerical discrimination circuit or the like in “• multi-valued logic circuit based on Houji algebra principle” or “other multi-valued logic system”. It can also be used as a numerical value discrimination circuit or the like in a multilevel logic circuit based on
Further, the multi-value for numerical determination circuit of the first invention, the multi-level AND logic determination times as "multi-level OR logic determination circuit based on a Fuji algebra principles" of the second invention based on "Fuji algebra principles of the third aspect of the present invention it is also possible to use the road. "
Houji algebra (Hooji algebra) is a multi-valued logic system created by the present inventors, but the details will be described in the paragraph numbers [ 0100 to 0156 to 0163 ] described later.

  The "multi-value OR logic discriminator based on the principle of the hood algebra" according to the second invention (claim 2) utilizes the multi-value numerical discriminator for multi-value according to the first invention "the multi-level OR logic based on the principle of the hood algebra" Relates to a circuit for determining

The “multi-level AND logic discriminator circuit based on the principle of the hood algebra” according to the third invention (claim 3) applies “the multi-level AND logic base on the principle of the hood algebra” by applying the numerical discriminator circuit for multi-level according to the first invention. Is a circuit that determines

● In addition, the techniques of "Hojiji Algebra" and "Various multi-valued logic circuits based on the principle of Huge Algebra" which are not yet widely known, and with "Synchronous latching function of Patents 16 and 17" In order to be able to treat the technique etc. of "multi-level logic means and multi-level hazard removal means" in the same manner as the technical common sense in the explanation of the present invention, their principles and techniques are described in paragraph numbers [ 0100 to 0163 ]. The present inventors explain in detail in Paragraph No. [ 0164 to 0284 ] and Paragraph No. [ 0284 to 0297 ] respectively.
Among them, in particular, with regard to “the multi-valued logic complete circuit based on the principle of fugi algebra”, the inventor explains in detail in paragraph numbers [ 0134 to 0147 , 0150 to 0163 , 0295 to 0296 , 0314 to 0317 ], Are already disclosed in the following patent documents 14, 16-20. However, the use of the name "Hooji algebra" is from Patent Document 14.
● In addition, the inventor of the present invention is described in paragraph numbers [ 0297 to 0302 ] for "expansion, extensibility and universality of fugi algebras", and in particular, "expansion and extensibility of fugi algebras to optical multivalued logic circuits". explain in detail.
● And, "The true three-dimensional IC that the inventor thinks! ? "What is the potential technology needed for its preparation!" ? The present inventors point out in Paragraph No. [0362 to 0363] the "cooling method of three-dimensional IC".

Unexamined-Japanese-Patent No. 2012-034345 (Multi-value hazard removal circuit. February 16, 2012 publication.) Japanese Patent Laid-Open No. 2012-075084 (Multi-level logic means having synchronous latching function and multi-level hazard removal circuit.) JP-A-2014-135709 (Multi-level logic means having synchronous latching function, multi-level hazard removal means, etc. The same invention as the above-mentioned Patent Document 16) JP-A 2014-179977 (Multi-value NOT two-step connection means based on the principle of Fuge Algebra, multi-value NOT · EVEN two-step connection means based on the principle of Fuge Algebra, multi-value EVEN two-step connection means based on the principle of Fuge Algebra , And, multi-value EVEN · NOT two-step connection means based on the principle of the fuse algebra.) JP-A-2015-026878 (important is a numerical discrimination circuit and a numerical discrimination circuit having a numerical value holding function. The same invention as the present invention) JP-A-2015-122743 (Numerical discriminator circuit for multi-level logic circuit based on principle of hoody algebra, etc. It has a function to suppress unnecessary vibration of its input signal.)

■ ■ ■ ■ ■ 1st invention to 3rd invention background art

First, as preliminary knowledge, "How to call each logic level of multiple levels (temporary, Kamei)" and "The numerical value determination and each threshold potential of each logic level (or each threshold voltage)" explain.
■■ How to call each multilevel logic level (Kana or Kamei) ■■
In the case of a binary circuit (eg, binary logic circuit, binary arithmetic circuit, binary memory, binary storage means, binary digital system, etc.), the two logical values are, for example, "0" and "1". Because there is only one, the terms "L level and H level" can be used to represent each logic level regardless of positive logic and negative logic. In fact, in positive logic, substantially L means "logic level of logic value 0" and H level means "logic level of logic value 1", while in negative logic, logic L level is substantially "logic “H” means “logical level of numerical value 1”, and “H” means “logical level of logical numerical value 0”.
Further, in the case of a ternary circuit, since the three logical values include, for example, “0”, “1” and “2”, for example, “L level, M” can be used to represent each logic level regardless of positive logic and negative logic. The terms "level, H level" can be used.
Furthermore, in the case of a four-valued circuit, since the four logical values include, for example, "0", "1", "2" and "3", the representation of each logic level is The terms L level, M ₀ level, M ₁ level, H level can be used.
Similarly, in the case of a five-valued circuit, since there are "0", "1", "2", "3", and "4" in the five logical values, each logic level regardless of positive logic or negative logic. For example, the terms "L level, M ₀ level, M ₁ level, M ₂ level, H level" can be used to represent.

However, in the case of "a composite multi-level digital circuit in which a plurality of multi-level circuits having different multi-level numbers (= N of N) are mixed" or "multi-level numbers are different from each other" In the case of “an irregular multi-value digital circuit” in which a plurality of “1 and a plurality of logical variables” are mixed (for example, described in paragraph number [ 0154 ] described later), those terms are confused. I will.
Eg, H-level three-state circuit corresponds to M ₁ level 4 value circuit, H level 4 value circuit corresponds to M ₂ level of 5-value circuit.
In that case, "logic level name and logical value" corresponding to each power supply line with "the largest multi-value number N (= N value of N.) to be used" as the reference of the whole circuit. Is fixed or unified to “the largest multi-level number N logic level name and logical value to be used”, for example, abbreviation of “logical level 2 logical level” corresponding to the power supply line V ₂ It will be somewhat cleaner if it is called "logical 2 level" and further abbreviated "L ₂ level".
Therefore, in the case of a 10-value circuit, for example, "logical levels 0 to 9" corresponding to "power line V ₀ to power line V ₉ " one by one are called "L ₀ level to L ₉ level", "each logic level one-to-one by corresponding each" constant potential or constant voltage "" is toward the L ₀ level to L ₉ level, go high if positive logic, so that becomes lower if negative logic .
In this case, “If a binary circuit is configured in the 10-valued circuit, it is configured between the power supply line V ₀ and the power supply line V _1. If a ternary circuit is configured, the power supply line V ₀ to the power supply line V ₂ If you configure it in the meantime and configure a 4-value circuit, configure it between the power supply line V ₀ to the power supply line V ₃ ......... If you configure a 9-value circuit, the power supply line V ₀ to the power supply line V ₈ It is a straightforward idea to configure them in such a way as to "configure it in between".

However, there is also a method of anomalous configuration that is not the case as follows. For example, selected and used "second power supply line in need" from the "power supply lines V _{0 ~} power supply line V _9" when configuring the binary circuit in the 10 value circuit. The selection is not only numerically “0 and 1” (that is, power supply lines V ₀ and V ₁ ) but also numerical values “4 and 5” (that is, power supply lines V ₄ and V) in the entire circuit of 10 values. ₅ ), numbers “8 and 9” (ie power supply lines V ₈ and V ₉ ), numbers “3 and 7” (ie power supply lines V ₃ and V ₇ ), numbers “5 and 9” (ie power supply lines V ₅ and It means selection of the combination of various numerical values such as V ₉ ), numerical values “0 and 9” (ie, power supply lines V ₀ and V ₉ ), and the magnitude of the power supply voltage for the binary circuit.
However, since there are only L level and H level in each binary circuit, if it is only in the binary circuit, it is binary new, for example, in the case of positive logic, L level is 0, H level is 1 It may be considered as, but will be considered as "L 2 two _0-level ~L ₉ level in" the whole circuit including the 10 value circuit.
In short, there is no confusion if these matters are considered purely as an electronic circuit, but there are, for example, "difference in the magnitude of the power supply voltage" and "difference in the height of the power supply potential". On the other hand, considering the correspondence between each power supply line and each power supply potential and each multi-level logic value for each multi-level number, “difference in each multi-level number” or “which power line corresponds to reference numerical value 0” It is complicated and easy to be confused because the element "?"
Therefore, the logical level of each value of multi-value is "L ₀ level, L ₁ level, L ₂ level ..." or "..., L _-2 level, L _-1 level, L ₀ level, L _{0 1} level, L ₂ level... "(In the case of code symmetric expression) and so on.
★★★ Name of each logical level corresponding to each logical value one by one (Kana, Kamei) ★ ★ ★

■ ■ ■ ■ their numerical value determination and each threshold potential (or each threshold voltage) of each logic level ■ ■ ■
■ ■ In the case of a binary circuit ■ ■
■ Input threshold potential (or input threshold voltage) of each logic level ■
We will describe the method of numerical judgment of positive logic. In the binary circuit, “L level input voltage (or input potential)” is substantially a “plus” based on zero power supply voltage (or zero power supply potential) predetermined by the “international standard, international standard specification, etc. Side input threshold voltage (or positive side input threshold potential), and “H level input voltage (or input potential)” is substantially determined in advance by “the international standard, international specification, etc. The negative input threshold voltage (or negative input threshold potential) based on the positive power supply voltage + V _DD (or positive power supply potential + V _DD ).
Also, in the binary circuit, "L level output voltage (or output potential)" is substantially based on "zero power supply voltage (or zero power supply potential)" previously determined by "international standard, international standard specification, etc." Positive-side output threshold voltage (or positive-side output threshold potential), and “H-level output voltage (or output potential)” substantially means “by its international standard, international specification, etc. It is a predetermined negative output threshold voltage (or negative output threshold potential) based on positive power supply voltage + V _DD (or positive power supply potential + V _DD ).
Furthermore, “L level input voltage (or input potential)” is set higher than “L level output voltage (or output potential)” by the noise margin on the L side, and “H level input voltage (or input potential)”. Is set to be lower than “H level output voltage (or output potential)” by the amount of noise margin on the H side. In other words, “H and L level both output voltages (or both output potentials)” have “H and L level both input voltages (or both input potentials)” for “H side and L side noise margin”. It is set to hold it from above and below.

“Introduction to logic circuits”, p. 126 to p. 128 “6.4 IC characteristics (1) Signal voltage value and noise margin”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd., September 28, 2001. “A well understood digital electronic circuit”, p. 76 to p. 80 '[1] logic level ~ [2] noise margin'. Author: Sekine Keitaro, Inc. Ohm company published on July 25, 1997. “Introductory Lecture on Transistor Circuit 5: Concept of Digital Circuit”, p. 46 to p. 47 “4.6 Notes on using logic circuit [1] Logic voltage level and noise margin”. Supervision: Yoshifumi Amamiya, Norii Kojima (Tsuneori). Author: Kenshi Shimizu (Masaru). Published by Ohm Co., Ltd. May 20, 1982. "Pulse digital circuit", p. 125 to p. 130 "5. Basic characteristics of circuit 5 ・ 1 Amplitude characteristics of pulse digital circuit. Author: Kawamata Minoru. Published by Nikkan Kogyo Shimbun Inc. on February 15, 1995. "Pulse and digital circuit", p. 128 "threshold levels" and p. 129 "Logical levels". Editor: Masao Yoneyama. Writing: Ohara Shigeyuki, Yoshikawa (Kikikawa) Sumio, Shibasaki Toshio, Takahashi Shiro. Published by Tokai University Press on April 5, 2001.

■ Circuit threshold voltage (or circuit threshold potential) ■
A binary circuit which is usually called "threshold voltage (or threshold potential)" is, for example, in the case of a CMOS buffer circuit or a CMOS inverter circuit, "a boundary at which the operation state of PMOS and NMOS is inverted", or "a circuit threshold Value voltage (or circuit threshold potential).
However, in the case of these CMOS inverter circuits, etc., the binary value discrimination circuit built in them doubles as "the output changeover switch circuit which switches the output to high or low" or the binary value discrimination circuit thereof. Since an output switching circuit or the like is connected to the subsequent stage, the output voltage with respect to the input voltage is uniquely determined.
However, if the output switch circuit section has "an open output or open output such as open collector or open drain or an output method such as open output" as in each invention, a pull-up or down resistance is added to the output terminal. Unlike the above, if the connection is left unconnected, the "output voltage with respect to the input voltage" is not uniquely determined by the conventional method.
Also, the circuit threshold voltage varies depending on the characteristics of each component transistor, but both H level and L level input voltages are set so as to sandwich "all the circuit threshold voltages varying" from above and below with a margin. Be done. This is true for both positive logic and negative logic.
つ ま り ● ● That is, “input threshold voltage (or input threshold potential) of logic level 1 logic level” and “input threshold voltage (or input threshold potential) of logic level 0 logic level” “Is set so as to sandwich“ all the circuit threshold voltages (or circuit threshold potentials) that vary ”from above and below with a margin. ●●
■ Device threshold voltage ■
Then, there is what is called "on / off threshold voltage" or simply "element threshold voltage" of the semiconductor device.
***
The threshold voltages of these "circuits and elements" are uniquely determined by the magnitude of the power supply voltage and the characteristics of the respective semiconductor elements.

"Introduction to logic circuit", p. 126 to p. 128 “6.4 IC characteristics (1) Signal voltage value and noise margin”. In particular ● “Figure 6.15 LS-TTL input and output voltages”. Above, "A well understood digital electronic circuit", p. 76 to p. 80 '[1] logic level ~ [2] noise margin'. In particular, ● “Figure 4.5 Logic levels”. “Introduction course for transistor circuits 5: Concept of digital circuit”, p. 43 to p. 46 "4.3 diode-transistor logic circuit (DTL) to 4.5 current switched logic circuit (CML)". In particular, ● "Figure 4 · 10 DTL-NAND input and output characteristics" and "Figure 4 · 13 TTL-NAND input and output characteristics". “Introduction to practical use series CMOS circuit usage [1]”, “element threshold voltage” on page 44 and “circuit threshold voltage” on page 50. Author: Suzuki Eighty Two (Yasoji). Published by October 15, 1997, the Industrial Research Association.

■ ■ In the case of multi-level circuit ■ ■
■ Input threshold potential (or input threshold voltage) of each logic level ■
On the other hand, positive logic is used to determine whether a multi-value (N value) input value is "a value defined as corresponding to the lowest logic level {eg, 0,-(n-1), etc.}". If the signal potential corresponding to the input numerical value is lower than “a predetermined positive potential threshold potential based on the constant potential corresponding to the lowest logic level (eg, DC power supply potential 0)”, then The input value is determined to be "the lowest logic level value".
However, at the present time, in the case of multiple values, “the minimum threshold level plus side threshold potential” is not determined in advance specifically by the international standard, international standard specification, etc. (?), So it is natural However, each researcher and each developer of the multi-valued circuit decides in advance the “minimum logic level plus side threshold potential”. In the future, if “potential mode (or voltage mode) multi-value circuit” is to be used for general purpose, “the minimum logic level plus side threshold potential according to the international standard, international standard specification, etc. "Will be determined in advance. This is also true for the following "each threshold potential".
In addition, the method to determine whether the multi-value (N value) input numerical value is “numeric value defined to correspond to the highest logic level {example: (n−1) etc. numerical value N = numerical value n.}” In the case of positive logic, the signal potential corresponding to the input value is “predetermined negative threshold based on the constant potential corresponding to the highest logic level (eg DC power supply potential + v _{n −1} ) If it is higher than "potential", the input numerical value is determined to be "the numerical value of the highest logic level".
Furthermore, each multi-value (N value) input numerical value is defined as “each numerical value defined to correspond one-to-one with each intermediate logic level between the lowest and highest logic levels {eg: 1 to (n−2), − (N−2) to 0 to (n−2).} ”, The signal potential of the input numerical value corresponds to“ a constant potential v corresponding to one or more intermediate logic levels ”. (N−2) or (2 n−3) “plus-side threshold values predetermined based on _{1 to} v _n−2 or constant potential v − _{n + 2 to} v _{0 to} v _n−2 ” respectively If there is one between each of the potential and the minus side threshold potential ", the input numerical value is determined to be" the numerical value of the intermediate logic level corresponding to that one ".
In the case of negative logic, only the lowest logic level and the highest logic level are directly affected because the plus side and the minus side of each threshold potential mentioned above are only opposite. Since each of the intermediate logic levels has one positive threshold potential and one negative threshold potential (two in total), the result of the change is the same even if each plus and minus are opposite. is there. After all, the threshold potential of the lowest logic level is changed from the positive side to the negative side, and the threshold potential of the highest logic level is only changed from the negative side to the positive side.

For example, in the case of a 10-value circuit of logical values 0 to 9, the positive logic is as follows.
The region of L ₀ level is a region lower than “the first constant potential which is the lowest potential {example: DC power supply potential 0 (= v ₀ etc., etc.) plus-side threshold potential based on the basis}”.
★ The region of each level of L _{1 to} L ₈ is sequentially between “the positive threshold potential and the negative threshold potential with reference to each constant potential of the second constant potential to the ninth constant potential”. Area of
★ The region of L ₉ level is a region higher than “the minus side threshold potential based on the 10th constant potential which is the maximum potential (example: DC power supply potential + v ₉ etc.)”.
In general, it is normal to think that it will be set as follows by "international standard specification / international standard specification" etc., but it is not the exception (eg, when using a bipolar transistor etc. like TTL, upper and lower asymmetry There is also). Each negative side threshold potential of L ₁ level to L ₉ level is “constant potential of its logic level”, “constant potential of its logic level,” and “constant potential of logic level one lower than the constant potential of its logic level” The positive threshold potential of L ₀ level to L ₈ level is set to “one of the potentials of the logic level one level above the constant potential of the logic level”. And one of the middle potential of the constant potential of the logic level and the constant potential of the logic level.
Incidentally, in the case of a 10-value circuit of negative logic value 0-9, for example, it becomes as follows.
The region of L ₀ level is a region higher than “the first constant potential which is the maximum potential {example: DC power supply potential 0 (= v _0, etc., etc.) minus threshold potential on the basis of}”.
★ The region of each level of L _{1 to} L ₈ is sequentially between “the positive threshold potential and the negative threshold potential with reference to each constant potential of the second constant potential to the ninth constant potential”. Area of
★ The region at L ₉ level is lower than “the 10th constant potential of the lowest potential (example: DC power supply potential − v ₉ etc.) plus threshold potential on the basis of”.
Japanese Patent Application Laid-Open No. 2004-0332702 (Multi-valued logic circuit based on a hoody algebra) JP 2005-198226 (ibid) JP 2005-236985 (ibid)

As a result, "the threshold potential (or threshold voltage when determining that" it is a numerical value of ... "" and "the threshold when determining as" not being that numerical value "and" clearly " The potentials (or threshold voltages) are not the same, do not match.
In detail, when quantifying the continuous "potential or voltage" physical quantity, for example, "numerical value 0, 1", "numerical value 4, 5", "numerical value 8, 9" This is because it is difficult to use each other in order to eliminate each other's potential region (or each other's voltage region). And it is in order to give tolerance to a noise signal. This is to prevent the discrimination value from becoming 0 or 1 due to a noise signal to be superimposed on the input signal to be determined from this.
It is a matter of course in binary circuits, but if it is positive logic, "the threshold potential (or threshold voltage when it is determined to be" numerical value 0 ") is the L-level input potential (or input voltage) On the other hand, “the threshold potential (or threshold voltage) at the time of“ determining clearly as “the number is not 0” ”is“ the threshold potential (at the time when it is determined as “the number 1” Or, since the threshold voltage is equal to the input potential (or input voltage) at H level, that is, both threshold potentials do not match.

For this reason, for example, in order to be clearly determined that the input numerical value of the 10-value circuit is not the numerical value "0", it is determined that the input numerical value is any one of the numerical values "1 to 9". Therefore, it is necessary to determine that the signal potential of the input numerical value is necessarily higher than the negative side threshold potential of the L ₁ level.
In this case, “potential region 1 with no numerical value 1 or 2”, “potential region with no numerical value 2 or 3”,..., “Potential region with no numerical value 7 or 8” and “numerical value 8” The nine potential regions are included in the “potential region for determining that any one of the numerical values“ 1 to 9 ””, but there is no problem at all. This is because these "potential regions" with no problem are "potential regions where it can be said clearly that the numerical value is not 0".
Therefore, "the threshold potential for being determined" clearly "that the input numeric value is the numeric value" 0 " is the plus side threshold potential of the L ₀ level, but" the input numeric value is the numeric value " If it is not “0” , “the threshold potential to be determined clearly” is the negative threshold potential of the L ₁ level, and the two threshold potentials do not match.

Similarly, in order to be clearly determined that the input numerical value of the 10-value circuit is not the numerical value "9", the input numerical value is determined to be any one of the numerical values "0 to 8". since it is there, the signal potential of the input numerical value must be determined always to be lower than the positive threshold potential of L ₈ level.
Therefore, "the threshold potential to be determined" clearly "that the input numerical value is the numerical value" 9 " is the minus side threshold potential of the L ₉ level, but" the input numerical value is the numerical value " If it is not 9 ” , “ the threshold potential for being determined clearly ”is the plus side threshold potential of L ₈ level, and both threshold potentials do not match.
Similarly, in order to be clearly determined that the input numerical value of the 10-value circuit is not the numerical value “1”, the input numerical value is one of the numerical values “0, 2 to 9”. Since it is necessary to be determined, if the signal potential of the input numerical value is always determined to be lower than the positive threshold potential of L ₀ level or higher than the negative threshold potential of L ₂ level It must be determined.
Therefore, "the input value" clearly and is a number "1", "threshold potential two for the determination" is L ₁ level plus, is a threshold potential of the negative sides, "the The two threshold potentials for “clearly” judging that the input numerical value is not “1” are “L ₀ level plus side threshold potential” and “L ₂ level minus side threshold Therefore, the two "threshold potentials" do not match.
In the same way, the same two “threshold potential potentials” for “clearly” determination do not match in each of the numerical values “2 to 8”.

■ Circuit threshold potential (or circuit threshold voltage) considered in multiple values ■
Similar to the case of the binary circuit, the case where the output potential with respect to the input potential of the multilevel circuit is uniquely determined will be specifically described. For example, the case of a 10-valued CMOS buffer circuit in which the input numerical value and the output numerical value are the same will be described as follows.
Reference: 6-value buffer circuit shown in FIG. 11 of JP-A-2006-252742.
_Just as there is a circuit threshold potential (or circuit threshold voltage) between potential zero and potential + v _{DD in} a binary circuit, “between potential v ₀ and potential v ₁ ”, “potential” in a 10-value circuit v between ₁ and potential _{v 2} "," between the potential _{v 2} and the potential _{v 3} ", ........., during the" potential _{v 7} and the potential _{v 8} "," between the potential _{v 8} and the potential _{v 9} ', respectively It can be considered that there is one circuit threshold potential. That is, there are a total of nine circuit threshold potentials in the 10-value circuit.
Also, as described above, with respect to each logic level area that will be set in the future “International Standard / International Standard Specification” etc., _one negative side input threshold potential is provided for each of L _{1 to} L ₉ levels. each set, each L ₀ level ~L ₈ levels would be a plus-side input threshold potential is set one by one.

For this reason, the relationship between each circuit threshold potential and "the positive side input threshold potential of each logic level, the negative side input threshold potential of each logic level" is the same as in the case of the binary circuit described below. It is believed to be in the street.
***
2 で は ● In a binary circuit, “input threshold voltage (or input threshold potential) of logical level 1 logic level” and “input threshold voltage (or input threshold potential) of logical level 0 logic level Is set so as to sandwich "all the circuit threshold voltages (or circuit threshold potentials) that vary" from above and below with a margin. ● → → Paragraph number [0012] mentioned above.
***
Similarly, the following is also true for multi-level circuits.
◆ 1) “L ₀ level positive side input threshold potential and L ₁ level negative side input threshold potential” “all circuit threshold potential between potential v ₀ and potential v ₁ ” from above and below It is set to sandwich with a margin.
◆ 2) “L ₁ level positive side input threshold potential and L ₂ level negative side input threshold potential” “all circuit threshold potential between potential v ₁ and potential v ₂ ” from above and below It is set to sandwich with a margin.
◆ 3) “L ₂ level positive side input threshold potential and L ₃ level negative side input threshold potential” “all circuit threshold potentials between potential v ₂ and potential v ₃ ” It is set to sandwich with a margin.
◆ 4) ..................................................................................................
◆ 5) ..................................................................................................
◆ 6) ..................................................................................................
◆ 7) ......................................................................................................
◆ 8) “L ₇ level positive side input threshold potential and L ₈ level negative side input threshold potential” “all circuit threshold potentials between potential v ₇ and potential v _{8 that} are dispersed” from the top and bottom It is set to sandwich with a margin.
◆ 9) from the upper and lower "L ₈ level plus side input threshold potential and L ₉ level minus side input threshold potential of" is "all circuit threshold potential between the variations in potential v ₈ · potential v _9" It is set to sandwich with a margin.
● Caution ● However, if the output switch circuit section has "an open output such as open collector or open drain or an output method such as open output" as in the present invention, the output terminal is pulled up or down Since “the output voltage with respect to the input voltage” is not uniquely determined unlike the above if the resistor or the like is not connected, the circuit threshold potential can not be obtained by the conventional method. → → Paragraph number [0024] described later.
“Introduction to logic circuits”, p. 126 to p. 128 “6.4 IC characteristics (1) Signal voltage value and noise margin”. In particular, Figure 6.15 LS-TTL Input and Output Voltages. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd., September 28, 2001.

The background art of the first to third inventions of the main subject will now be described.
■■ Overview ■■
N-valued multi-valued circuits (example: circuits using multi-valued technology etc., such as multi-valued logic circuits, multi-valued arithmetic circuits, multi-valued memories, multi-valued memory circuits, etc.) Integer {e.g., "0, 1, 2, ..., (n-2), (n-1)" and the like. Or (2N-1) consecutive integers {eg, "-(n-1),-(n-2), ..., -2, -1, 0, 1, 2, ..., (n- 2), (n-1) etc. In the case of code symmetric representation. Use}. Numeric N = Numeric n.
There are, for example, 14 examples of the circuits of FIGS. 3 to 16 as the conventional multi-value numerical value discrimination circuit and “various multi-value logic discrimination circuits based on the principle of the hood algebra applying it”. Each circuit is provided at the input portion of the multilevel circuit, and the multilevel numerical value discrimination circuit determines whether the input numerical value is the integer value m or not, and the multilevel logic discrimination circuit The multi-value OR logic, the multi-value AND logic, the multi-value NAND logic, or “whether the input numerical value of is for the integer value m, all the integer values m, and at least one of them is the integer value m” , It discriminates by multi-value NOR logic.

However, in each circuit of FIGS. 3-16, predetermined number {example: N pieces, (2N-1) pieces. Of the continuous integers of}, three continuous integers are represented by m−1, m, m + 1, and three direct current power source potentials (= constant potentials) defined to correspond one by one to these three integers in order in _{v m-1, v m,} v m + 1 expressed in these 3 power source potential one by supplying the power supply line (= constant potential supply means) _{V m-1} 3 pieces of sequentially, V _{m, V m + 1} in Is represented.
Of course, these things are similarly applied to the power supply potentials v _{0 to} v _{n -1} and the power supply lines V _{0 to} V _{n -1} which are defined to correspond to the continuous integers "0 to (n-1)" one by one. it is a continuous integer "- (n-1) ~0~ ( n-1) " and first power supply potential is defined as the corresponding one by pairs _{1 v -n + 1 ~v 0 ~v} n-1 and the power supply line V _{- The} same applies to _{n + 1 to} V _{0 to} V _n-1 (in the case of code symmetric representation).
As a matter of course, in each of the circuits of FIGS. 3 to 16, one DC power source (means) exists directly or equivalently between each of “two power supply lines adjacent to each other at potential level”.

Also, although normally “1 ≦ m ≦ n−2” or “−n + 2 ≦ m ≦ n−2” (in the case of code symmetry expression), the number of power supply lines and the number of parts thereof may be increased. , “0 ≦ m ≦ n−1” or “−n + 1 ≦ m ≦ n−1” (in the case of code symmetry expression). Or, there is no need to stick to these things.
Furthermore, the difference between the output terminal Tout in each of FIGS. 3 to 8 and the output terminal Tout in each of FIGS. 9 to 16 is that the output signals of the two become opposite to each other with respect to the same input signal.
Then, the multi-value number is a predetermined natural number of 3 or more, and the multi-value number is hereinafter represented by N or n (≧ 3). (In addition, 3 is also included in 3 or more in Japanese, but 3 is not included in "more than 3" in English, so the word "3 or 3 or more" is included just in case to make a mistake in English translation. I use it.)
And both circuits of FIG. 3 and FIG. 4, both circuits of FIG. 5 and FIG. 6, both circuits of FIG. 7 and FIG. 8, both circuits of FIG. 9 and FIG. 10, both circuits of FIG. Both circuits of FIG. 14 and each of both circuits of FIGS. 15 and 16 are, as seen, in a mutually complementary relationship with respect to voltage polarity or voltage direction.
A multivalue numerical value discrimination circuit in each circuit of FIG. 6 and FIG. 10 of JP-A-2004-020322.

■ ■ Description of the operation of the multivalue numerical value discrimination circuit shown in Figs. 3 to 4 ■ ■
The multi-value numerical value discrimination circuit of FIG. 3 is simple both in circuit configuration and circuit operation, but its numerical value discrimination operation is as follows. However, the magnitude of the (on / off) threshold voltage v _th 92 of the transistor 92 is smaller than the both power supply potential difference “v _{m + 1} −v _{m −1} ”, that is, the potential difference between both power supply potentials v _{m + 1} and v _m−1 .
The on / off threshold voltage of the transistor 84 is obtained by adding the positive (on / off) threshold voltage “voltage” of the transistor 84 to the power supply potential v _m−1 of the input potential v _in of the input terminal Tin. When it exceeds “●”, the transistor 84 is turned on, and when it is lower, the transistor 84 is turned off. Then, the input potential v _in is “the on / off threshold voltage of the transistor 81 obtained by adding the negative (on / off) threshold voltage“ voltage ”of the transistor 81 to the power supply potential v _{m + 1.} When it is lower, the transistor 81 is turned on, and when it is higher, the transistor 81 is turned off.
As a result, if the input potential v _in is between the on / off threshold potential of the transistor 84 and the on / off threshold potential of the transistor 81, the transistor 92 is also on because the transistors 81 and 84 are simultaneously on. The output terminal Tout outputs the power supply potential v _{m -1} . On the other hand, if the input potential v _in is not between the two on / off threshold potentials, one of the transistors 81 and 84 is off, so the transistor 92 is off and the output terminal Tout is opened (output open or output open Open output).

In this case, since the output terminal Tout is not connected with a pull-up resistor or a load resistor and there is no output voltage at the time of the open output, input / output voltage characteristics (or input / output transfer characteristics) as in the prior art The circuit threshold potential (or circuit threshold voltage) can not be determined in a conventional manner.
Thus, after all, the provisional ON-OFF threshold electrostatic transistor 84 "position" and ● as a circuit threshold potential of the minus side of the "Numeric m corresponding to the power supply line V _m" Preliminary to handle, the transistor 81 oN-oFF threshold electrostatic "position" inevitably provisionally treated as circuit threshold potential of the plus side of the "value along the power supply line V _m m" and ●.
Thus, when the power supply potential v supply potential v _m is the circuit threshold potential there two above and below the _m is an intermediate power supply voltage, in the case the power supply potential v _m is the highest or the lowest power supply potential As in the binary circuit, the circuit threshold potential becomes one.
After that, if this multi-value numerical value discrimination circuit is widely used, can these provisional circuit threshold potentials be formally recognized as it is, or another method in which the formal circuit threshold potentials are different Engineers in the world have no choice but to decide based on international standards, international standards, etc.

“Introductory Lecture on Transistor Circuit 5: Concept of Digital Circuit”, p. 43 to p. Forty-five "4-3 diode-transistor logic circuits (DTL)" and "4-4 transistor-transistor logic circuits (TTL)". In particular, ● "Figure 4 · 13 TTL-NAND input / output characteristics" and its descriptive text. Supervision: Yoshifumi Amamiya, Norii Kojima (Tsuneori). Author: Kenshi Shimizu (Masaru). Published by Ohm Co., Ltd. May 20, 1982. "Pulse digital circuit", p. 125 to p. 130 "5. Basic characteristics of circuit 5 ・ 1 Amplitude characteristics of pulse digital circuit. In particular, (a) to (d) in FIG. Author: Kawamata Minoru. Published by Nikkan Kogyo Shimbun Inc. on February 15, 1995. "Pulse and digital circuit", p. 128 “Threshold levels” and Figure 4.5. Editor: Masao Yoneyama. Writing: Ohara Shigeyuki, Yoshikawa (Kikikawa) Sumio, Shibasaki Toshio, Takahashi Shiro. Published by Tokai University Press on April 5, 2001.

The above “circuit operation and circuit threshold potential (or circuit threshold voltage)” applies to the multi-value numerical discrimination circuit in FIG. 4 as well, but this circuit uses P-channel transistor 85. Because they differ, they differ in the following points.
A) The magnitude of the (on / off) threshold voltage v _th 85 of the transistor 85 is smaller than the potential difference between the two power sources “v _{m + 1} −v _{m −1} ”, that is, the potential difference between the two power source potentials v _{m + 1} and v _m−1 .
B) When the input potential v _in is between the on / off threshold potential of the transistor 84 and the on / off threshold potential of the transistor 81, the output terminal Tout outputs the power supply potential v _{m + 1} .
C) A pull-down resistance or a load resistance is connected to the output terminal Tout.

When using each of the numerical value discrimination circuits in FIG. 3 and FIG. 4 as the numerical value discrimination unit in the “multi-valued logic circuit based on the principle of hoody algebra”, both of the numerical value discrimination circuits in FIG. It is determined whether or not the input numerical value corresponding to the input potential v _in inputted to the numerical value discrimination circuit / specific specific value m of the numerical value discrimination circuit. For this reason, if each of the numerical values 0 to (n-1) is to be determined using the numerical value determination circuit of FIG. 3 or 4, it is necessary to at least n.
On the other hand, in the case of multi-value logic system of code symmetric representation, if each of the numerical values (-n + 1) to (n-1) is to be discriminated, at least (2n-1) of them are required.
As for the specific value, in the "multi-valued logic circuit based on the principle of Fuge algebra", the inventor has introduced the concept of a specific value, and is the input numerical value the same as the input specific value m _in ? Whether this is the case or not is determined, and in accordance with the determination result, the output specific value m _out is output as the multilevel logic output, or the output is released. Usually, both specific values are identical, represented by m.
Further, each of the multi-value numerical value determination circuits shown in FIGS. 3 and 4 can be used as they are simply as a “multi-value EVEN logic circuit (output reverse conduction type) based on the principle of Fourier algebra”. In this case, in the logical operation, if the input numerical value N _in is the numerical value m, the circuit of FIG. 3 outputs the numerical value “m−1” and the circuit of FIG. 4 outputs the numerical value “m + 1”. Otherwise, both outputs are open. → → (Open output)

Next, the correspondence with the through current in the binary circuit will be described. For example, the value m is determined using the multi-value numerical value determination circuit of FIG. 3 and the value "m + 1" is determined using the multi-value numerical value determination circuit of FIG. Consider a simple combined / multivalued logic circuit where terminals Tin and both output terminals are connected to form a common output terminal Tout.
Depending on the relationship between the circuit threshold potential (or circuit threshold voltage) on the plus side of numerical value m and the circuit threshold potential (or circuit threshold voltage) on the negative side of numerical value “m + 1” There are cases where the through current flows to both transistors 85, 92, etc.
A) When the former (numerical value m) is set higher than the latter (numerical value “m + 1”), both numerical potential regions overlap, so the input numerical value N _in is from numerical value m to numerical value “ When changing to m + 1, or when the input numerical value N _in changes _{in the} opposite direction, through current flows in both transistors 85, 92 and so on. In this case, it is usual that the through current does not become a large power supply short circuit current.
B) When both are set so that both threshold potentials are at the same level, both numerical potential areas are in contact with each other at the same potential, so one of the two transistors 85, 92, etc. As long as the reverse recovery time on the other side is not longer than the forward recovery time, the through current does not flow even if the input numerical value N _in changes as described above.
◆ c) If the former (numerical value m) is set lower than the latter (numerical value “m + 1”), the two numerical potential regions do not overlap at all, so the input numerical value N _in is as described above. Even if the through current changes, the through current becomes more difficult to flow than in the case of ◆ b) above or does not flow at all.

However, it is confirmed that the circuit threshold potential (or circuit threshold voltage) on the plus side of the numerical value m is “the power supply potential v _{m + 1} in the circuit of FIG. The on / off threshold voltage of the transistor 81, which is the sum of the negative (on / off) threshold voltage "voltage" ◆ The circuit threshold on the negative side of the value "m + 1" potential (or circuit threshold voltage) replaced by m = m + 1 in the circuit of "Figure 4 is a, that the new-supply potential v _m of the transistor 84 plus the (on-off) threshold electric" pressure "◆ The on / off threshold voltage of the added new transistor 84 is "●".
Further, a researcher, a developer, and the like who use the multi-value numerical value determination circuit shown in FIGS.

The both-multivalue OR logic discrimination circuit shown in FIGS. 5 and 6 applies the both- and multi-value numerical value discrimination circuits shown in FIGS. 3 and 4 to discriminate "multi-value OR logic based on the principle of Fourier algebra".
It is determined whether at least one of the three input numerical values input to the input terminals Tin1 to Tin3 is the numerical value m or not (that is, whether all three of the input numerical values are values other than the numerical value m). If at least one of the three input numerical values is the numerical value m, the circuit of FIG. 5 outputs the potential v _m−1 from the output terminal Tout, and the circuit of FIG. 6 outputs the potential v _{m + 1} . Otherwise, both circuits open the output terminal Tout.

The both-multi-value AND logic determination circuit of FIGS. 7 and 8 applies the both- and multi-value numerical value determination circuits of FIGS. 3 and 4 to determine "multi-value AND logic based on the principle of Fourier algebra".
It is determined whether all three input numerical values input to the input terminals Tin1 to Tin3 are numerical values m or not (that is, at least one of the three input numerical values is a numerical value other than the numerical value m). If all the three input numerical values are the numerical value m, the circuit of FIG. 7 outputs the potential v _m−1 from the output terminal Tout, and the circuit of FIG. 8 outputs the potential v _{m + 1} . Otherwise, both circuits open the output terminal Tout.

■ ■ Description of the operation of the multivalue numerical value discrimination circuit shown in Figs. 9 and 10 ■ ■
The multi-value numerical value discrimination circuit of FIG. 9 is also simple in circuit configuration and circuit operation, but its numerical value discrimination operation is as follows.
Input pin input voltage v _in the Tin is in "Power potential v _m of transistor 332 plus the (on-off) threshold power" pressure "on-off threshold power" position of the transistor 332 which is obtained by adding the ◆ "● Transistor 332 turns on and transistor 332 turns off. On the other hand, the input potential v _in is “the on / off threshold voltage of the transistor 331 obtained by subtracting the positive (on / off) threshold voltage“ voltage ”of the transistor 331 from the power supply potential v _m. If it falls below, the transistors 331 and 333 turn on, and if it exceeds the transistors 331 and 333 turn off.
As a result, if the input potential v _in is between the on / off threshold potential of the transistor 331 and the on / off threshold potential of the transistor 332, the transistors 331 to 333 are simultaneously off, so the output The terminal Tout bar is open (output open or open output). On the other hand, if the input potential v _in is not between the two on / off threshold potentials, the output terminal Tout outputs the power supply potential v _m because one of the transistors 331 333 or the transistor 332 is on. That is, this circuit pulls its output potential v _out to the power supply potential v _m .
Note that the multi-value numerical value determination circuit of FIG. 9 can also be used as it is as a simple “multi-value EVEN logic circuit (output reverse conduction type) based on the principle of Fourier algebra”. In this case, logically, if the input numerical value N _in is the numerical value m, the output is open (open output), otherwise the numerical value m is output.

In this case, no pull-up resistance or load resistance is connected to the output terminal Tout bar, and there is no output voltage at the time of the open output, so input / output voltage characteristics (or input / output transfer characteristics as in the prior art) Can not be determined, so it is not possible to determine the circuit threshold potential (or circuit threshold voltage) in a conventional manner.
Thus, after all, the provisional ON-OFF threshold electrostatic transistor 331 "position" and ● as a circuit threshold potential of the minus side of the "Numeric m corresponding to the power supply line V _m" Preliminary to handle, the transistor 332 oN-oFF threshold electrostatic "position" inevitably provisionally treated as circuit threshold potential of the plus side of the "value along the power supply line V _m m" and ●.
Thus, when the power supply potential v supply potential v _m is the circuit threshold potential there two above and below the _m is an intermediate power supply voltage, in the case the power supply potential v _m is the highest or the lowest power supply potential As in the binary circuit, the circuit threshold potential becomes one.
After that, if this multi-value numerical value discrimination circuit is widely used, can these provisional circuit threshold potentials be formally recognized as it is, or another method in which the formal circuit threshold potentials are different Engineers in the world have no choice but to decide based on international standards, international standards, etc.
The above “circuit operation and circuit threshold potential (or circuit threshold voltage)” similarly applies to the multi-value numerical value determination circuit of FIG. However, the circuit of FIG. 10 is in a complementary relationship with the multi-value numerical value discrimination circuit of FIG. 9, and the pull-down resistance, the load resistance, etc. are connected to the output terminal Tout. Further, when the circuit of FIG. 10 is used as a “multi-level EVEN logic circuit (output reverse conduction type) based on the principle of hoodie algebra”, if the input numerical value N _in is numerically m, the output is logically If it is open (open output), otherwise it outputs the value m.

The four multi-level NAND logic determination circuits of FIGS. 11 to 14 determine “multi-level NAND logic based on the principle of the hood algebra” by applying the double / multi-level numerical value determination circuit of FIGS.
It is determined whether all three input numerical values input to the input terminals Tin1 to Tin3 are numerical values m or not (that is, at least one of the three input numerical values is a numerical value other than the numerical value m). If all three of the input numerical values are the numerical value m, each circuit opens the output terminal Tout bar. Otherwise, each circuit outputs the potential v _m from the output terminal Tout.

  The multi-value numerical value discrimination circuit shown in FIG. 13 is obtained by simplifying the circuit configuration shown in FIG. 11 to reduce the number of parts, and the multi-value numerical value determination circuit shown in FIG. 14 simplifies the circuit structure shown in FIG. It is the one with a reduced score.

The double / multi-value NOR logic discrimination circuit of FIGS. 15 and 16 applies the double / multi-value numerical value determination circuit of FIGS. 9 and 10 to decide “multi-value NOR logic based on the principle of the hood algebra”.
It is determined whether at least one of the three input numerical values input to the input terminals Tin1 to Tin3 is the numerical value m or not (that is, whether all three of the input numerical values are values other than the numerical value m). If at least one of the three input numerical values is the numerical value m, each circuit opens the output terminal Tout bar. Otherwise, each circuit outputs the potential v _m from the output terminal Tout.

■ ■ Relationship between logic level threshold potential and provisional circuit threshold potential ■ ■
In digital circuits, noise margin must be taken into consideration, so as in the case of binary circuits, “plus side of logic level area considering noise margin with respect to circuit threshold potential (or circuit threshold voltage) It is necessary to set the threshold potential (or threshold voltage) on the negative side.
For example, the logic level region of numerical value (m-1) is "between the negative threshold potential and the positive threshold potential with respect to power supply potential v _m-1 ", and the logic level region of numerical value m is a "power supply potential v _m between negative threshold potential and positive threshold potential relative to the" numeric (m + 1) negative threshold that the logic level region based on the "supply potential v _{m + 1} of It is set as "between the value potential and the positive side threshold potential". Of course, it is set to each numerical value of numerical value "0- (n-1)" or numerical value "(-n + 1)-(n-1)" (in the case of code symmetrical expression).
However, since each circuit threshold potential (or each circuit threshold voltage) varies depending on the characteristics of each component transistor etc., “minus side threshold potential of logic level L _{m + 1} of numerical value“ m + 1 ”” The positive side threshold potential of logic level L _m of numerical value m is set so that "all circuit threshold potentials that vary between both power supply potentials v _{m + 1} · v _m " from above and below with margin (noise margin) And “the negative threshold voltage of the logic level L _m of the numerical value m” and the “positive threshold voltage of the logic level L _{m −1} of the numerical value“ m−1 ”are“ both power supply potentials v _m · v _The circuit threshold potentials all dispersed between _m-1 are set to be sandwiched from above and below with a margin (noise margin).
However, at present, in the case of multiple values, “the threshold potential of each logic level” has not yet been specifically decided according to the international standard, international standard specification, etc. (!?), So it is natural Each researcher and each developer of the multi-level circuit decides in advance its own "threshold potential at each logic level". In the future, if “potential mode (or voltage mode) multi-value circuit” is to be used for general purpose, “the threshold potential of each logic level” is set according to the international standard, international standard specification, etc. It will be decided.

Therefore, in each of the “multi-value numerical value determination circuits in FIGS. 3, 4, 9, and 10” and “each-multi-value logic determination circuit in FIGS. 5 to 8 and FIGS. The following four threshold potentials (or threshold voltages) relate to the determination.
◆ a) Negative threshold voltage of logic level L _{m + 1} of integer “m + 1” ◆ b) “positive threshold voltage and negative threshold voltage of logic level L _m of integer m”
C) Logic threshold L _m-1 plus-side threshold potential of integer “m−1” And, _{in order} for the numerical discrimination circuit to determine whether the input numerical value N _in is the same as the numerical value m, An input potential v _in corresponding to the input numerical value N _in input to the terminal Tin is “minus threshold potential and plus side threshold with respect to the power supply potential v _m (corresponding to the logic level L _m ) It is determined whether or not there is an electric potential. On the other hand, for the numerical value discrimination circuit to determine that the input numerical value N _in is not the same as the numerical value m, the input potential v _in is referred to as “the power supply potential v _{m −1} (corresponding to the logic level L _{m −1} ) It is determined whether the threshold voltage is lower than the positive threshold voltage or higher than the negative threshold voltage based on the power supply voltage v _{m + 1} (corresponding to the logic level L _{m + 1} ).
However, when the numerical value m is "the numerical value corresponding to the lowest logic level L ₀ or L- _{n + 1} (in the case of code symmetry expression)", the minus side threshold potential is not necessary, but the circuit configuration is complicated. As long as the number of parts is increased, the negative threshold potential may be left. On the other hand, when the numerical value m is “the numerical value corresponding to the highest logic level L _n−1 ”, the plus side threshold potential is not necessary, but the circuit configuration becomes complicated and the number of parts increases. If it does not matter, the plus side threshold potential may be left.

■ ■ Problem of the background art of the first invention ■ ■
However, in each of the multi-value numerical value discrimination circuits of FIGS. 3, 4, 9, 10, each circuit has at least one resistor in its circuit component, so that it has a switching operation mode like a CMOS circuit. The switch is a switch (3 terminal switch) like a CMOS circuit because it is not composed only of a normally-off type transistor and the output switch section of any circuit is open drain (or open collector). ) Not configured.
In each of the multi-valued numerical value discrimination circuits of FIGS. 3, 4, 9, and 10, “the resistance that consumes power and generates heat in the steady state” is from the input terminal Tin to the output terminal Tout or Tout bar. It is used as one of the components. As much as possible, I would like to construct a multi-value numeric discrimination circuit using only "switching means including a transistor in the switching operation mode" like a CMOS circuit.

■ ■ Problem of the background art of the second invention ■ ■
However, in each of the circuits shown in FIGS. 5 and 6 to which each of the multi-value numerical value determination circuits of FIGS. 3 and 4 is applied, each circuit component has a plurality of resistors. Therefore, it is not composed of only the normally-off type transistor in the switching operation mode as in the CMOS circuit, and the output switch section of either circuit is open drain (or open collector). It is not configured as a changeover switch (= 3 terminal switch) like a CMOS circuit.
In each of the multi-value OR logic determination circuits of FIGS. 5 and 6, “a resistor that consumes power and generates heat in a steady state” is used as one of its components between the input terminal Tin and the output terminal Tout. There is. As much as possible, we would like to construct a multi-value OR logic discrimination circuit with only "switching means including a transistor in the switching operation mode" like a CMOS circuit.

■ ■ Problem of the background art of the third invention ■ ■
However, in “each of FIG. 7 and FIG. 8 each of FIG. 8 and FIG. 8 of FIG. 8 to which each multi-value numerical value discrimination circuit is applied” of FIG. Therefore, it is not composed of only the normally-off type transistor in the switching operation mode as in the CMOS circuit, and the output switch section of either circuit is open drain (or open collector). It is not configured as a changeover switch (= 3 terminal switch) like a CMOS circuit.
In each of the multi-level AND logic determination circuits of FIGS. 7 and 8, “a resistor that consumes power and generates heat in a steady state” is used as one of its components between the input terminal Tin and the output terminal Tout. There is. As much as possible, I would like to construct a multi-level AND logic discrimination circuit with only "switching means including a transistor in a switching operation mode" like a CMOS circuit.

Japanese Patent Application Laid-Open No. 2004-020322 (Multi-valued logic circuit based on new and multi-valued logic "Fuji Algebra", ◆ considered as dropped) → → Reference: Paragraph number [0150] described later. Japanese Patent Application Laid-Open No. 2005-198226 (Multi-valued logic circuit based on new and multi-valued logic "Fuji Algebra") → → ● Divided into Patent No. 4900785 and ◎ following · Patent Document 9. Japanese Patent Application Laid-Open No. 2005-236985 (Multi-valued logic circuit based on new and multi-valued logic "Fuge algebra") → → ● Patent No. 4643297 JP-A-2006-190239 ("Information processing means having an unauthorized intrusion operation preventing function" to which multi-valued logic is applied ") ((Spontaneous withdrawal. This is a situation requiring an emergency such as a cyber attack in recent years, etc.) The present inventors voluntarily withdrawn this.) → → 分割 Divided into Patent Document 10 below. JP-A-2006-228388 → → ● Patent No. 4800642 (multi-value storage means and multi-stable circuit). Japanese Patent Application Laid-Open No. 2005-116168 of the same invention of the prior application is ◆ withdrawal. Patent Document 1: JP-A-2006-252742->-Patent No. 4800 657 (multi-value storage means and multi-stable circuit), and ◎ Division into the following · Patent Document 11.

Patent No. 2006-345468 → → ● Patent No. 4643376 (Multi-level storage means, Multi-level transfer gate means, Multi-level synchronous latch means and Multi-level synchronous signal generating means). Patent No. 2007-035233 → → ● Patent No. 4800706 (multi-level decoding means, multi-level storage circuit, and multi-level information processing means) and division into: JP, 2011-097637, → → → ● The division application of the patent 5363511 (multi-valued logic circuit) and the above-mentioned patent documents 2. JP-A-2011-103124 ("Information processing means having an unauthorized intrusion operation preventing function" to which multi-value logic is applied ", (◆ Spontaneous withdrawal. This is also the same reason as the original application.), Division of the above Patent Document 4 application. JP-A-2011-172254 → → ● Patent No. 5249 379 (multi-directional bidirectional switching means), division application of the above-mentioned · patent document 6. Further divided into the following · Patent Document 15 below. JP-A-2011-204349 (multi-state buffer means, multi-level multiplexer means and multi-level demultiplexer means) ((Spontaneous drop-off. The following high-order patent for multi-level buffer means). Division application of literature 8. Unexamined-Japanese-Patent No. 2011-229069 (Multi-level hazard elimination circuit, ◆ considered withdrawing.)

JP 2012-034345 (Multi-Level Hazard Removal Circuit. Published February 16, 2012. ◆ Considered withdrawal.) JP, 2012-069236, → → → ● Division application of patent 5139568 (multi-value buffer means) and the above-mentioned * patent documents 11. Japanese Patent Laid-Open Publication No. 2012-075084 (Multi-valued logic means having a synchronous latching function, etc. published on April 12, 2012. ◆ deemed withdrawal.) JP-A-2014-135709 (Multi-level logic means having a synchronous latching function, etc. The same invention as JP-A-2006-147324. Prior to the publication of JP-A-2006-324118 and JP-A-2006-112922, filed "Priority Claim Based on Priority Claim"). Japanese Patent Application Laid-Open No. 2014-179977 (Multiple-valued NOT two-step connection means etc. based on the principle of Fuge algebra) JP-A-2015-026878 (important is a numerical discrimination circuit having a numerical discrimination circuit and a numerical value holding function.) JP-A-2015-122743 (Numerical discriminator circuit for multi-level logic circuit based on principle of hoody algebra, etc. It has a function to suppress unnecessary vibration of its input signal.)

“Introduction to logic circuits”, p. 126 to p. 128 “6.4 IC characteristics (1) Signal voltage value and noise margin”. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd., September 28, 2001. “A well understood digital electronic circuit”, p. 76 to p. 80 '[1] logic level ~ [2] noise margin'. Author: Sekine Keitaro, Inc. Ohm company published on July 25, 1997. “Introductory Lecture on Transistor Circuit 5: Concept of Digital Circuit”, p. 46 to p. 47 “4.6 Notes on using logic circuit [1] Logic voltage level and noise margin”. Supervision: Yoshifumi Amamiya, Norii Kojima (Tsuneori). Author: Kenshi Shimizu (Masaru). Published by Ohm Co., Ltd. May 20, 1982. "Pulse digital circuit", p. 125 to p. 130 "5. Basic characteristics of circuit 5 ・ 1 Amplitude characteristics of pulse digital circuit. Author: Kawamata Minoru. Published by Nikkan Kogyo Shimbun Inc. on February 15, 1995. "Pulse and digital circuit", p. 128 "threshold levels" and p. 129 "Logical levels". Editor: Masao Yoneyama. Writing: Ohara Shigeyuki, Yoshikawa (Kikikawa) Sumio, Shibasaki Toshio, Takahashi Shiro. Published by Tokai University Press on April 5, 2001. “Introduction to practical use series CMOS circuit usage [1]”, “element threshold voltage” on page 44 and “circuit threshold voltage” on page 50. Author: Suzuki Eighty Two (Yasoji). Published by October 15, 1997, the Industrial Research Association. "Mathematical science February issue (1980, No. 200) Feature: Multivalued Logic", published by Science Co., Ltd. on February 1, 1959.

"High-tech classroom multi-level logic circuit IC integration degree increase binary numbers and three values also go", Nikkei Sangyo Shimbun (Tokyo version) published November 22, 1985. Writing: Ishizuka Kohiko. "Multi-value information processing-post-binary electronics-" Authors: Tatsuo Higuchi, Michitaka Kameyama (Michitaka), Shokodo (Shikokodo) published in June 1989. “The Attic Reference Room Multi-Valued Logic” on pages 374-375 of “Transistor Technology September, 1997”. Published by CQ Publishing Co., Ltd. on September 1, 1997. Writing: Inoue Hidekazu. "Revision electrical circuit theory standard electrical engineering course" p. 115 to p. 120 “Transient phenomenon of 8 · 3 R-L-C circuit” → “When applying DC electromotive force to 8 · 3 · 1 R-L-C circuit”. Author: Teruo Suesaki, Hiroshi Amano, Corona Co., Ltd. published the 21st edition on March 20, 1944. ◆ a) damped oscillation ◆ b) over damping ◆ c) critical damping "The Institute of Electrical Engineers of Japan Nomenclature No. 9 Power Electronics Authors: "Special Committee on Electrical Standards for Electrical Engineering", "Subcommittee for Semiconductor Power Converters for Electrical Engineering, Editors", Editor: Electrical Society, Inc., Corona Corp. February 28, 2000 Revised version 1st print issued. "Bidirectional switch, bi-directional controllable switch, reverse conducting switch, reverse blocking switch". Note that "valve" has almost the same meaning as "switch". P. 79-88 (binary pulse trigger system). Japan Riko Publishing Co., Ltd. published 4th edition on April 25, 2008. Author: Nakamura Tsugio.

■■ Problems to be solved by the first invention ■■
However, in each of the multi-value numerical value discrimination circuits of FIGS. 3, 4, 9, 10, each circuit has at least one resistor in its circuit component, so that it has a switching operation mode like a CMOS circuit. The switch is a switch (3 terminal switch) like a CMOS circuit because it is not composed only of a normally-off type transistor and the output switch section of any circuit is open drain (or open collector). ) Not configured.
In each of the multi-valued numerical value discrimination circuits of FIGS. 3, 4, 9, and 10, “the resistance that consumes power and generates heat in the steady state” is from the input terminal Tin to the output terminal Tout or Tout bar. It is used as one of the components. If possible, it is desirable to configure a multi-value numeric value discrimination circuit using only "switching means including a transistor in a switching operation mode" like a CMOS circuit.
(1) Therefore, it is desirable to construct a multi-value numerical value discrimination circuit without using resistance means such as a resistor or a transistor in the current limiting mode (or resistance mode) at least from the input terminal to the output terminal. (Problems to be solved by the first invention)

In addition, although it calls it an input terminal and an output terminal (equivalent to the entrance means in Claim 1, an exit means.) For convenience of explanation, in fact, it does not exist as a terminal, but it may be a mere conducting wire, an electrode, etc. in many cases. . This is similar to, for example, a base terminal of a transistor, a base electrode, a base lead, or simply called a base.
Also, there are, for example, the following two transistors as current limit mode transistors.
a) Normally-off FET with its drain and gate connected.
b) Normally-on FET with its gate and source connected.

■ ■ Problem to be solved by the second invention ■ ■
However, in each of the circuits shown in FIGS. 5 and 6 to which each of the multi-value numerical value determination circuits of FIGS. 3 and 4 is applied, each circuit component has a plurality of resistors. Therefore, it is not composed of only the normally-off type transistor in the switching operation mode as in the CMOS circuit, and the output switch section of either circuit is open drain (or open collector). It is not configured as a changeover switch (= 3 terminal switch) like a CMOS circuit.
In each of the multi-value OR logic determination circuits of FIGS. 5 and 6, “a resistor that consumes power and generates heat in a steady state” is used as one of its components between the input terminal Tin and the output terminal Tout. There is. If possible, we would like to construct a multi-value OR logic discrimination circuit with only "switching means including a transistor in the switching operation mode" like a CMOS circuit.
(1) Therefore, it is desirable to construct a multi-value OR logic discrimination circuit without using resistance means such as a resistor or a transistor in the current limiting mode (or resistance mode) at least from the input terminal to the output terminal. (Problems to be solved by the second invention)

In addition, although it calls it an input terminal and an output terminal (equivalent to the entrance means in Claim 1, an exit means.) For convenience of explanation, in fact, it does not exist as a terminal, but it may be a mere conducting wire, an electrode, etc. in many cases. . This is similar to, for example, a base terminal of a transistor, a base electrode, a base lead, or simply called a base.
Also, there are, for example, the following two transistors as current limit mode transistors.
a) Normally-off FET with its drain and gate connected.
b) Normally-on FET with its gate and source connected.

■■ Problems to be solved by the third invention ■■
However, in “each of FIG. 7 and FIG. 8 each of FIG. 8 and FIG. 8 of FIG. 8 to which each multi-value numerical value discrimination circuit is applied” of FIG. Therefore, it is not composed of only the normally-off type transistor in the switching operation mode as in the CMOS circuit, and the output switch section of either circuit is open drain (or open collector). It is not configured as a changeover switch (= 3 terminal switch) like a CMOS circuit.
In each of the multi-level AND logic determination circuits of FIGS. 7 and 8, “a resistor that consumes power and generates heat in a steady state” is used as one of its components between the input terminal Tin and the output terminal Tout. There is. If possible, we would like to construct a multi-level AND logic discrimination circuit with only "switching means including a transistor in the switching operation mode" like a CMOS circuit.
(2) Therefore, it is desirable to construct a multilevel AND logic discrimination circuit without using resistance means such as a resistor or a transistor in the current limiting mode (or resistance mode) at least from the input terminal to the output terminal. (Problems to be solved by the third invention)

In addition, although it calls it an input terminal and an output terminal (equivalent to the entrance means in Claim 1, an exit means.) For convenience of explanation, in fact, it does not exist as a terminal, but it may be a mere conducting wire, an electrode, etc. in many cases. . This is similar to, for example, a base terminal of a transistor, a base electrode, a base lead, or simply called a base.
Also, there are, for example, the following two transistors as current limit mode transistors.
a) Normally-off FET with its drain and gate connected.
b) Normally-on FET with its gate and source connected.

Means for Solving the Problems of the First Invention (Claim 1)
That is, the first invention is
"Multiple constant potential supply means" supplying one "one same number of constant potentials" defined as one to one with "three or more predetermined integers" respectively In the value circuit,
Of the three or more predetermined integers, three consecutive integers are represented by m−1, m, m + 1,
Among the same number of constant potentials, three constant potentials corresponding to the three consecutive integers are sequentially called v _m−1 , v _m and v _{m + 1} ,
Assuming that three constant potential supply means for supplying the three constant potentials among the same number of constant potential supply means are referred to as V _m−1 , V _m and V _{m + 1} in order.
When the first binary NOT circuit is formed by connecting two control electrode insulated transistors to be switched in series between both constant potential supply means V _{m + 1} · V _m , the high potential side transistor is made bi-directional,
When forming a second binary NOT circuit by connecting two control electrode insulated transistors to be switched in series between the two constant potential supply means V _m · V _{m -1} , the low potential side transistor is bi-directional West,
Connecting the input terminals of the two binary NOT circuits together to form an entrance means,
The absolute value of the threshold voltage is smaller than the potential difference between both constant potentials v _{m + 1} · v _{m -1} between both output terminals of the two binary NOT circuits, and the potential difference between both constant potentials v _{m + 1} · v _m A normally-off, control-electrode-insulated fifth transistor, which is larger than the potential difference between the two fixed potentials v _m · v _m -1, a portion between the control terminal and the main terminal forming a pair for driving signal input " Are connected such that “when the high potential side transistor and the low potential side transistor are turned on, the fifth transistor is turned on, that is, in the forward bias direction”,
It is a multivalue numerical value discrimination circuit in which the remaining main terminals of the fifth transistor are used as the exit means.

  In addition, although it calls an input terminal and an output terminal for convenience of explanation, in fact, it does not exist as a terminal, but it may be a mere conducting wire, an electrode, etc. in many cases. This is similar to, for example, a base terminal of a transistor, a base electrode, a base lead, or simply called a base.

Thus, in terms of circuit operation, the input signal potential input to the inlet means is "the circuit threshold potential between v _{m + 1} · v _m " and "the circuit threshold potential between v _m · v _{m -1} If the value is between “1”, the high potential side transistor of the first binary NOT circuit and the low potential side transistor of the second binary NOT circuit are turned on. Since the potential difference (= voltage) between the two constant potentials vm _{+ 1} and vm _-1 is applied between the main terminals, the fifth transistor is on.

At this time, the input numerical value is determined to be an integer m, and the output potential of the exit means is a constant potential v if the polarity of the drive forward bias voltage (eg, gate forward bias voltage) of the fifth transistor is positive. a _m-1, a constant potential if negative _{v m + 1.}
Reference: The transistor 96 (N-channel type) in FIG. 1 and the transistor 95 (P-channel type) in FIG.
However, “the circuit threshold potential between v _{m + 1} and v _m ” is the circuit threshold potential of the first binary NOT circuit and “the circuit threshold potential between v _m and v _{m −1} ” Is the circuit threshold potential of the second binary NOT circuit.

However, the input signal potential input to the inlet means is "the circuit threshold potential between both constant potentials v _{m + 1} · v _m " and "the circuit threshold potential between both constant potentials v _m · v _{m -1} " Between the control terminal and the main terminal of the fifth transistor, since a potential difference of “between both constant potentials v _{m + 1} and v _m or between both constant potentials v _m and v _{m −1} ” is applied, The fifth transistor is off and the outlet means is open. At this time, it is determined that the input numerical value is not an integer m.
Specifically, when the input signal potential is higher than “the circuit threshold potential between both constant potentials v _{m + 1} and v _m ”, the low potential side transistor of each binary NOT circuit is turned on, so the fifth A part of the charging energy between the control terminal and the main terminal of the transistor is regenerated between the two constant potential supply means V _m · V _m-1 via the two low potential side transistors, and between the control terminal and the main terminal both constant potential _{v m} · _{v m-1} between the potential difference (= voltage) is applied. Thus, the fifth transistor is off and the outlet means are open. (Open output or output open)

On the other hand, when the input signal potential is lower than “the circuit threshold potential between the two constant potentials v _m · v _{m −1} ”, the high potential side transistor of each binary NOT circuit is turned on, so the fifth some of the charging energy between the control terminal and a main terminal of the transistor is regenerated via the two high-side transistor between the two constant potential supply means V _{m + 1 ·} V _m, Ryojo between a control terminal, the main terminals A potential difference (= voltage) between potentials v _{m + 1} and v _m is applied. Thus, the fifth transistor is off and the outlet means are open. (Open output or output open)

  As a result, there is no need to use resistance means such as resistance or transistors in the current limit mode (or resistance mode) between the inlet means (eg: input terminal etc.) and the outlet means (eg: output terminal etc.) We were able to construct a value discrimination circuit for value. (Effect of the first invention)

The means for solving the problems of the second invention (claim 2)
That is, the second invention is
When the multivalue numerical value discrimination circuit according to the first invention described in the paragraph [005 4 ] is provided between the two constant potential supply means _{Vm + 1} · _Vm-1 by a predetermined number, all the exit means are the same -Either the down function or the pull up function is
When connecting all its outlet means and providing a new common outlet means, its pull function (ie its pull-down function or pull-down function) between each of the outlet means before its connection and its common outlet means It is a "multi-value OR logic discriminator based on the principle of Fuge algebra" which is aligned in the direction of the up function and connected one by one.

As a result, a "multi-value OR logic determination circuit based on the principle of Fourier algebra" having the predetermined number of entry means (eg, input terminal etc.) is formed.
Since the multivalue numerical value discrimination circuit of the first invention is applied in the construction, the transistor in the resistance or current limit mode (or resistance mode) is provided between the inlet means and the outlet means (eg, output terminal etc.) It was possible to construct a "multi-level OR logic discriminator based on the principle of the fuse algebra" without using resistance means etc. (Effects of the Second Invention)

The means for solving the problems of the third invention (claim 3)
That is, the third invention is
In the multivalue numerical value discrimination circuit according to the first aspect of the invention described in the paragraph [005 4 ],
When the predetermined number is represented by k,
“A series circuit of k bidirectional control electrode insulated transistors for switching operation and a parallel circuit of k control electrode insulated transistors for switching operation” are disposed between both constant potential supply means V _{m + 1} · V _m Of the positive logic binary NOR circuit connected in series with the high potential side and the first binary NOT circuit,
Between the two constant potential supply means V _m · V _m-1 ““ a parallel circuit of k bidirectional control electrode insulated transistors to operate switch ”and“ a series circuit of k control electrode isolated transistors to operate switch ” Replace the second binary NOT circuit with the positive logic binary NAND circuit connected in series with the former on the high potential side,
“Multi-value based on the principle of the hood algebra” in which k input terminals of each of the k input terminals of the binary NOR circuit and each of k input terminals of the binary NAND circuit are connected one by one to form k entrance means AND logic determination circuit.

As a result, a "multi-level AND logic determination circuit based on the principle of Fourier algebra" having the predetermined number of entry means (eg, input terminal etc.) is formed.
Since the multivalue numerical value discrimination circuit of the first invention is applied in the construction, the transistor in the resistance or current limit mode (or resistance mode) is provided between the inlet means and the outlet means (eg, output terminal etc.) It was possible to construct a "multi-level AND logic discriminator based on the principle of the fuse algebra" without using resistance means such as. (Effect of the third invention)

The effect of the first invention
As a result, there is no need to use resistance means such as resistance or transistors in the current limit mode (or resistance mode) between the inlet means (eg: input terminal etc.) and the outlet means (eg: output terminal etc.) It is possible to configure a value determination circuit for value.

The effect of the second invention
As a result, between the inlet means (eg: input terminal etc.) and the outlet means (eg: output terminal etc.), without using resistance means such as resistors or transistors in current limit mode (or resistance mode) A multivalued OR logic discriminator circuit based on the principle of the Fuge algebra can be constructed.

The effect of the third invention
As a result, between the inlet means (eg: input terminal etc.) and the outlet means (eg: output terminal etc.), without using resistance means such as resistors or transistors in current limit mode (or resistance mode) A multivalued AND logic discriminator circuit based on the principle of the Fuge algebra can be constructed.

FIG. 1 is a circuit diagram showing one embodiment (first embodiment) of a multivalued numerical value discrimination circuit according to the first invention. FIG. 7 is a circuit diagram showing an embodiment (Embodiment 2) of the multivalued numerical value discrimination circuit of the first invention. FIG. 7 is a circuit diagram showing a first example of a conventional multi-value numerical value discrimination circuit. FIG. 13 is a circuit diagram showing a second example of a conventional multi-value numeric value discrimination circuit. It is a circuit diagram showing the 1st example of the conventional "multi-value OR logic distinction circuit based on the principle of a Fourier algebra". It is a circuit diagram showing the 2nd example of the conventional "multi-value OR logic distinction circuit based on the principle of a Fourier algebra". FIG. 16 is a circuit diagram showing a first example of a conventional “multi-level AND logic discrimination circuit based on the principle of fugi algebra”. FIG. 13 is a circuit diagram showing a second example of the conventional “multi-level AND logic discrimination circuit based on the principle of fugi algebra”. FIG. 16 is a circuit diagram showing a third example of a conventional multi-value numeric value discrimination circuit. It is a circuit diagram which shows the 4th example of the conventional multi-value numerical value discrimination circuit. To Each drawing is a circuit diagram showing one to four examples of the conventional "multi-level NAND logic discrimination circuit based on the principle of the Fourier algebra". FIG. 16 is a circuit diagram showing a first example of a conventional “multi-level NOR logic discrimination circuit based on the principle of fuse algebra”.

FIG. 16 is a circuit diagram showing a second example of a conventional “multi-level NOR logic discrimination circuit based on the principle of fuse algebra”. FIG. 18 is a circuit diagram showing an embodiment (third embodiment) of the “multi-value OR logic discrimination circuit based on the principle of the Fourier algebra” of the second invention. It is a circuit diagram showing one example (Example 4) of "the multi-value OR logic discrimination | determination circuit based on the principle of Fuge algebra" of 2nd invention. To Each of the drawings is a circuit diagram showing four examples (Examples 5 to 8) of the "multi-level AND logic discrimination circuit based on the principle of the hoody algebra" of the third invention one by one. To Each figure shows 1st to 10th examples of the "multi-value EVEN circuit or multi-value NOT circuit based on the principle of the Fourier algebra" using the embodiment 1 or 2 of the multi-value numerical value discrimination circuit according to the first invention. It is a circuit diagram shown each. It is a circuit diagram explaining the equivalent circuit and duality of "multi-value logic, multi-value OR logic circuit based on Houji algebra". It is a circuit diagram explaining the equivalent circuit and duality of "multi-value logic, multi-value AND logic circuit based on Houji algebra".

FIG. 5 is a circuit diagram showing a synthesis / multi-level logic circuit (= first 10-level logic complete circuit) supporting “very flexible perfectness” of the FUJI algebra. → → Multi-valued logic complete circuit. FIG. 36 is a truth table / figure showing a truth table simplified for explanation of the synthetic / multilevel logic circuit of FIG. 35. FIG. 36 is a circuit diagram showing a combined / multi-level logic circuit (= second 10-level logic complete circuit) whose configuration is simplified by introducing a multi-level wired OR circuit into the combined / multi-level logic circuit of FIG. → → Multi-valued logic complete circuit. FIG. 17 is a circuit diagram showing a “three-valued logic complete circuit introducing a multi-value wired OR circuit”, which also supports “very flexible perfectity” of the Fuge algebra. → → Multi-valued logic complete circuit. FIG. 39 is a truth value table / figure showing a truth value table of the synthetic / multilevel logic circuit of FIG. 38. FIG. 36 is a circuit diagram showing a combination / multi-value logic circuit (= third 10-value logic complete circuit) obtained by improving the combination / multi-value logic circuit of FIG. 35. → → Multi-valued logic complete circuit. FIG. 41 is a circuit diagram showing a combined multilevel logic circuit (= fourth 10-level logic complete circuit) in which the configuration is simplified by introducing a multilevel wired OR circuit to the combined / multilevel logic circuit of FIG. 40. → → Multi-valued logic complete circuit. FIG. 42 is a circuit diagram showing a combination / multi-value logic circuit (= a fifth complete 10-value logic complete circuit) in which the combination / multi-value logic circuit of FIG. 41 is improved. → → Multi-valued logic complete circuit. FIG. 36 is a circuit diagram showing a combination / multi-value logic circuit (= sixth ten-value logic complete circuit) obtained by equivalently modifying the combination / multi-value logic circuit of FIG. 35. → → Multi-valued logic complete circuit. FIG. 45 is a circuit diagram showing a combined multi-valued logic circuit (= seventh ten-valued logic complete circuit) obtained by improving the combined multi-valued logic circuit of FIG. 43. → → Multi-valued logic complete circuit.

FIG. 42 is a circuit diagram showing a combination / multi-value logic circuit (= eighth ten-value logic complete circuit) obtained by equivalently modifying the combination / multi-value logic circuit of FIG. 41. → → Multi-valued logic complete circuit. FIG. 46 is a circuit diagram showing a combined multi-level logic circuit (= a ninth complete 10-level logic circuit) obtained by improving the combined multi-level logic circuit of FIG. 45. → → Multi-valued logic complete circuit. FIG. 17 is a circuit diagram showing one conventional example of an asynchronous multi-value EVEN circuit based on the principle of the Fourier algebra. FIG. 5 is a circuit diagram showing a first conventional example of an asynchronous multi-value NOT circuit based on the principle of the Fourier algebra. FIG. 18 is a circuit diagram showing a second conventional example of an asynchronous multi-value NOT circuit based on the principle of the Fourier algebra. FIG. 16 is a circuit diagram showing a first prior art example of an asynchronous multi-value AND circuit based on the principle of Fourier algebra. A second conventional example of an asynchronous multi-level AND circuit based on the principle of the Fourier algebra (when H = G) and one conventional example of the asynchronous "multi-level AND NOUT circuit or multi-level AND IN circuit" It is a circuit diagram which shows (when H> G). The first conventional example of an asynchronous multi-level NAND circuit based on the principle of the Fourier algebra (when H = G), and the first of the same non-synchronous "multi-level NAND NOUT circuit or multi-level NAND IN circuit" It is a circuit diagram which shows a prior art example (when H> G). A third conventional example of an asynchronous multi-level AND circuit based on the principle of the Fourier algebra (when H = G) and one conventional example of the asynchronous "multi-level AND NOUT circuit or multi-level AND IN circuit" It is a circuit diagram which shows (when H> G).

A second conventional example of an asynchronous multi-level NAND circuit based on the principle of the Fourier algebra (when H = G) and a second conventional example of the asynchronous “multi-level NAND NOUT circuit or multi-level NAND IN circuit” It is a circuit diagram which shows a prior art example (when H> G). One conventional example of an asynchronous multi-level OR circuit based on the principle of the Fourier algebra (when H = G) and one conventional example of an asynchronous "multi-level OR NOUT circuit or multi-level OR IN circuit" (H > G) is a circuit diagram showing One conventional example of asynchronous type / multi-level NOR circuit based on the principle of the Fourier algebra (when H = G) and one conventional example of asynchronous type "multi-level NOR / NOUT circuit or multi-level NOR / IN circuit" (H > G) is a circuit diagram showing One conventional example (when H = G) of "asynchronous type / multi-level OR circuit based on the principle of the Fourier algebra" which improves the circuit of FIG. 56 and an asynchronous type "multi-level OR / NOUT circuit or multi-level OR. FIG. 16 is a circuit diagram showing one conventional example (when H> G) of the “IN circuit”. One conventional example (when H = G) of “asynchronous type / multi-value NOR circuit based on the principle of the hood algebra” which is an improvement of the circuit of FIG. 56 and an asynchronous type “multi-value NOR · NOUT circuit or multi-value NOR ··· FIG. 16 is a circuit diagram showing one conventional example (when H> G) of the “IN circuit”. It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to the Q terminal: Synchronous, multi-value NOT means, ◆ When connected to the Q bar terminal: Synchronous, multi-value EVEN means. It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to Q terminal: Synchronous "multi-level NIN means or multi-level OUT means", ◆ When connected to Q-bar terminal: Synchronous type "multi-level IN means or multi-level NOUT means". It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to Q terminal: Synchronous "multi-level NIN means or multi-level OUT means", ◆ When connected to Q-bar terminal: Synchronous type "multi-level IN means or multi-level NOUT means".

It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to Q terminal: Synchronous "multi-level NUNDER means or multi-level OVER means" ◆ ◆ When connected to Q-bar terminal: Synchronous "multi-level UNDER means or multi-level NOVER means". It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to the Q terminal: Synchronous "Multi-Level UNDER Means or Multi-Level NOVER Means". ◆ When connected to the Q-bar terminal: Synchronous "multi-value NUNDER means or multi-value OVER means". It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to the Q terminal: pull-down output synchronous type · multi-value NOT means, ◆ when connected to the Q bar terminal: pull-down output synchronous type · multi-value EVEN means. It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to Q terminal: pull-up output synchronous type · multi-value NOT means, ◆ when connected to Q bar terminal: pull-up output synchronous type · multi-value EVEN means It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to the Q terminal, when H = G: synchronous, multi-value EVEN means, when H> G: synchronous “multi-value IN means or multi-value NOUT means”. ◆ When connected to the Q-bar terminal, when H = G: synchronous / multi-value NOT means, when H> G: synchronous “multi-value NIN means or multi-value OUT means”. FIG. 7 is a circuit diagram showing a first example of the “on / off driving means and bi-directional pull switching means” common to the disclosed prior application first and second inventions. It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to Q terminal: Synchronous type ・ Multi-value EVEN means, ◆ When connected to Q bar terminal: Synchronous type ・ Multi-value NOT means. FIG. 10 is a circuit diagram showing a second example of the “on / off driving means and bi-directional pull switching means” common to the disclosed prior application first and second inventions.

It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to the Q terminal: Synchronous, multi-value NOT means, ◆ When connected to the Q bar terminal: Synchronous, multi-value EVEN means. It is a circuit diagram showing the 3rd example of the "on-off drive means and bi-directional pull switching means" portion common to the disclosed prior application first and second inventions. It is a circuit diagram showing the 4th example of the "on-off drive means and two-way pull switching means" portion common to the disclosed prior application first and second inventions. It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to the Q terminal, when H = G + 2: synchronous type / multi-value NOT means, when H> G + 2: synchronous type “multi-value IN means or multi-value NOUT means”. ◆ When connected to the Q-bar terminal, when H = G + 2: synchronous multi-level EVEN means, when H> G + 2: synchronous “multi-level NIN means or multi-level OUT means”. It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to Q terminal: Synchronous type ・ Multi-value EVEN means, ◆ When connected to Q bar terminal: Synchronous type ・ Multi-value NOT means. In the case of “H = G: common with the first application / first and second invention disclosed: AND judgment means or NAND judgment means, with ◆ H> G: AND · IN judgment means, NAND · IN judgment means, AND -It is a circuit diagram which shows the 1st example of a NOUT discrimination | determination means or a NAND NOUT discrimination | determination means and a "binary synchronous flip flop means and a synchronous signal supply means." In the case of “H = G: common with the first application / first and second invention disclosed: AND judgment means or NAND judgment means, with ◆ H> G: AND · IN judgment means, NAND · IN judgment means, AND -It is a circuit diagram which shows the 2nd example of a NOUT discrimination | determination means or NAND NOUT discrimination | determination means and a "binary synchronous flip flop means and a synchronous signal supply means."

It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to the Q terminal, when H = G: synchronous type / multi-level NAND means, when H> G: synchronous type "multi-level NAND / IN means or multi-level NAND / NOUT means". ◆ When connected to the Q-bar terminal, when H = G: synchronous type / multi-level AND means, when H> G: synchronous type “multi-level AND · IN means or multi-value AND · NOUT means”. In the case of "H = G: NOR determination means or OR determination means common to the first application, first and second inventions disclosed: ◆ H> G: NOR-IN determination means, OR-IN determination means, NOR -It is a circuit diagram which shows one example of a NOUT discrimination | determination means or an OR NOUT discrimination | determination means, and a "binary synchronous flip flop means and a synchronous signal supply means." The circuit of FIG. 78 is improved “when H = G: NOR determination means or OR determination means, ◆ when H> G: NOR • IN determination means, OR • IN determination means, NOR • NOUT determination means or OR • FIG. 6 is a circuit diagram showing an example of NOUT determination means, binary synchronous flip flop means and synchronous signal supply means. Three-input “when H = G: NOR determination means or OR determination means, applying the circuit of FIG. 79: ◆ When H> G: NOR / IN determination means, OR / IN determination means, NOR / NOUT determination means Or, it is a circuit diagram showing an example of “OR · NOUT determination means”. It is a circuit diagram showing one embodiment common to the disclosed prior application first and second inventions. ◆ When connected to the Q terminal, when H = G: synchronous, multi-value NOR means, when H> G: synchronous “multi-value NOR, IN means or multi-value NOR, NOUT means”. ◆ When connected to the Q-bar terminal, when H = G: synchronous type / multi-value OR means, when H> G: synchronous type “multi-value OR · IN means or multi-value OR · NOUT means”.

In order to explain the first to third inventions in more detail, they will be described below according to the attached drawings. In addition, the following eight notes are described first.
1) The following explanation includes "explanation from the viewpoint of electronic circuit" and "explanation from the viewpoint of logic and mathematics", and there is also a description in which both are mixed.
{Circle around (2)} Each embodiment in the case where these constant potentials “go up” in numerical order from the first constant potential to the Nth constant potential will be mainly described. (→ → positive logic)
On the other hand, regarding each embodiment in the case where these constant potentials "go down", each power supply potential (corresponding to each of these constant potentials in "the embodiments to be described or their respective derivative embodiments"). With each controllable switching means being replaced by “controllable switching means complementary to it (eg P-channel MOS • FET for N-channel MOS • FET)”, and the voltage direction or An embodiment in which the components having a voltage polarity (eg, a diode, a zener diode, etc.) are reversed and that is an embodiment having a symmetrical relationship with respect to the voltage direction or the voltage polarity with respect to the original embodiment corresponds thereto. Do. (→ → negative logic)
However, in that case, the multi-level logic function may be the same as or different from the original circuit.
{Circle over (3)} n in each embodiment corresponds to the above N (predetermined plurality).
◆ 4) The integer m corresponds to “specific integer for input” or “specific integer common to input and output where the specific integer for input is the same as the specific integer for output”, “means for specific constant potential supply for input (example: power supply It is an integer corresponding to the input specific constant potential (example: specific power supply potential v _m ) of the line V _m ). There is a relationship of “0 ≦ m ≦ n−1” or “−n + 1 ≦ m ≦ n−1”.

◆ 5) The integer Cm (≠ m) is an integer other than the integer m among the integers “0 to (n−1)” or the integers “−n + 1 to 0 to (n−1)” used in multi-valued number N = n It is.
That is, each relationship of “0 ≦ m ≦ n−1”, “0 ≦ Cm ≦ n−1” and “m ≠ Cm” or “−n + 1 ≦ m ≦ n−1”, “−n + 1 ≦ Cm ≦ n− 1 and m 各 Cm.
◆ 6) Each of “V _G , V _H , V _m , V _Cm , V − _n , V − _{n + 1 to} V _{0 to} V _{n −1} , V _n ”, etc. expressed by capital letter V is a power supply line and small letters "v _G , v _H , v _m , v _Cm , v- _n , v- _{n + 1 to} v _{0 -} v _{n -1} , etc." _expressed by v etc. are the potentials of the power supply lines (= constant potential) the expressed sequentially, "from _{v -1} to _{v n"} power supply potential _v -1 to v _n and the power supply potential _v -n to v _n their power supply potential in this order and _"v from _{-n v} to _n And go high.
In addition, of course, the power supply line V ₀ or other power line is "the main body case of the circuit" or "body of the circuit device" or "the hull of the ship, or the like" or "automobile, motorcycle, car body, such as a bicycle," or "land and water Dual-purpose main body such as hovercraft, or "main body of flight means such as airplane or helicopter" or "main body of space navigation means such as spacecraft or space station / space floating means" or "stellar bodies such as earth, moon, Mars The potential of the main body, the vehicle body, the hull and the celestial body becomes the reference potential such as the ground potential.
However, although one DC power supply or one DC power supply means for DC voltage supply is connected between each of "two power supply lines adjacent to each other at the level of the power supply potential", they are not shown.

◆ 7) For example, the diodes 10, 12, 35, 36, “Zener diode pair in which two Zener diodes are connected in series in the reverse direction”, dotted line “connection of its circuit configuration means itself or its circuit configuration means In the case of indicating “,” it means that “there is the case with or without the connection or insertion / connection”.
◆ 8) “Each gate terminal is connected to the Q terminal (positive output terminal) of the D-type flip flop 27 or the gate terminals or common gate terminals of the transistors 41, 47, 48 are drawn two by two. , Q bar terminals (complementary output terminals) are shown by dotted lines.
As a matter of course, "change the connection from Q terminal to Q bar terminal" and "change the connection from Q terminal Q to Q terminal""do the circuit after the connection change to the circuit before the connection change" It means that "it becomes a negative circuit".
As a precaution, "Q bar" means a letter drawn above the letter Q.
◆ 9) The “inlet means” and “outlet means” described in the claims and the like generally refer to, for example, the input terminal and the output terminal, but in reality they do not exist as terminals, but are simply conductive wires or electrodes It is often the case. This is similar to, for example, a base terminal of a transistor, a base electrode, a base lead, or simply called a base.
◆ 10) “power supply potential v ₋₁ , v _n etc. and power supply line V ₋₁ , V _n etc” or “power supply potential v _−n , v ₋₁ , v _n etc. and power supply line V _−n , V ₋₁ , If there is V _n etc. (in the case of symbol symmetry expression), if each circuit using the power supply potential or power supply line operates properly, each of the power supply potential or power supply line etc. and “integer −1, n” Or each correspondence of "integer-n, n (in the case of code symmetrical expression)" does not need to be defined.

FIG. 1 shows one embodiment (.fwdarw. First embodiment) of the multivalue numerical value discrimination circuit according to the first invention. In the first embodiment of FIG. 1, the constituent means correspond one-to-one to the constituent means in claim 1 as follows.
◆ a) “integer m−1, m, m + 1” is a continuous three integer “m−1, m, m + 1” in the same paragraph.
B) "The power supply lines _Vm-1 , _Vm , _{Vm + 1} " are the constant potential supply means _Vm-1 , _Vm , _{Vm + 1} in the same item.
◆ c) “the power supply potentials v _m−1 , v _m , v _{m + 1} ” are the constant potentials v _m−1 , v _m , v _{m + 1} in the same paragraph.
◆ d) The “binary NOT circuit formed by the transistors 81 and 82” is the first binarized NOT circuit in the same paragraph.
◆ e) The transistor 81 is “the high potential side transistor (→ bi-directional switch)” in the same paragraph.
Incidentally, when the back gate is connected to the source, the transistor 81 is a reverse conduction type (bidirectional switch that can be controlled only in one direction), and the back gate When connected to the highest constant potential in the circuit, the transistor 81 is a bi-directional controllable switch (= bi-directional switch capable of bi-directional control).
"The Institute of Electrical Engineers of Japan Nomenclature No. 9 Power Electronics Authors: "Special Committee on Electrical Standards for Electrical Engineering", "Subcommittee for Semiconductor Power Converters for Electrical Engineering, Editors", Editor: Electrical Society, Inc., Corona Corp. February 28, 2000 Revised version 1st print issued. "Bidirectional switch, bi-directional controllable switch, reverse conducting switch, reverse blocking switch". Note that "valve" has almost the same meaning as "switch".

F) The "two-value NOT circuit formed by the transistors 83 and 84" is the second two-value NOT circuit in the same paragraph.
G) The transistor 84 is “the low potential side transistor (→ bi-directional switch)” in the same paragraph.
H) The input terminal Tin is the inlet means in the same paragraph.
◆ i) The gate-insulated transistor 96 is the normally-off control electrode-insulated transistor described in the same paragraph.
J) The gate terminal and the source terminal of the transistor 96 become the “control terminal and main terminal forming a pair for driving signal input” described in the same paragraph.
◆ k) The drain terminal of the transistor 96 is the remaining main terminal of the fifth transistor in the same paragraph.
L) The threshold voltage v _th 96 of the transistor 96 is equal to the threshold voltage described in the same paragraph.
Note that v _th 96 in FIG. 1 means the (on / off) threshold voltage of the transistor 96, and the relational expression in FIG. 1 holds. That is, the absolute value of threshold voltage v _th96 is smaller than the potential difference between both power supply potentials v _{m + 1} · v _{m -1,} and the potential difference between both power supply potentials v _{m + 1} · v _m , both power supply potentials v _m · v _{m -1} The potential difference between them is greater than either.
◆ m) The output terminal Tout is the outlet means in the same paragraph.
◆ n) “Connecting the gate-source portion of the transistor 96 in the gate forward bias direction” in the same paragraph “When the high potential side transistor and the low potential side transistor are on, the fifth transistor is It corresponds to "connecting to be driven on".

The circuit operation of the first embodiment of FIG. 1 is as follows. The input signal potential v _in input to the input terminal Tin is “the circuit threshold potential of the binary NOT circuit between both power supply potentials v _{m + 1} and v _m ” and “2 between both power supply potentials v _m and v _{m −1} If the value is between the circuit threshold potentials of the value NOT circuits, since the transistors 81 and 84 are turned on, the potential difference between the power supply potentials v.sub.m _{+ 1} and v.sub.m _-1 between the gate and source of the transistor 96 (= The transistor 96 is on because the voltage is applied in the forward direction.
At this time, the input numerical value N _in is determined to be the numerical value m, and the output potential v _out of the output terminal Tout is the power supply potential v _{m -1} .
However, the input signal potential v _in input to the input terminal Tin is “the circuit threshold potential of the binary NOT circuit between both power supply potentials v _{m + 1} and v _m ” and “between the two power supply potentials v _m and v _{m −1} of without between the circuit threshold potential of the binary NOT circuit "between the gate and source of the transistor 96" dual supply potential _{v m} + 1 · _{v m} between either the two power supply potential _{v m} · _{v m-1} between "the Although the potential difference is applied in the forward direction, the output terminal Tout is opened when the transistor 96 is turned off because the gate forward bias voltage is insufficient. At this time, it is determined that the input numerical value N _in is not the numerical value m.

More specifically, when the transistor 96 is off, the transistors 82 and 84 are turned on when the input signal potential v _in is higher than “the circuit threshold potential of the binary NOT circuit between the two power supply potentials v _{m + 1} and v _m ”. Therefore, part of the charging energy between the gate and source of the transistor 96 is regenerated between the power supply lines V _m and V _m-1 through the transistors 82 and 84, and both power supply potentials v _m between the gate and source The potential difference (= voltage) between v _{m −1} is applied in the forward direction. However, since the gate forward bias voltage is insufficient, the transistor 96 is off and the output terminal Tout is opened. (Open output or output open)
When the input signal potential v _in is lower than “the circuit threshold potential of the binary NOT circuit between both power supply potentials v _m · v _{m −1} ”, the transistors 81 and 83 are turned on. Part of the charging energy between the gate and the source is regenerated between the two power supply lines V _{m + 1} and V _m through the transistors 81 and 83, and the potential difference between the two power supply potentials v _{m + 1} and v _m between the gate and the source =) Voltage is applied in the forward direction. However, since the gate forward bias voltage is insufficient, the transistor 96 is off and the output terminal Tout is opened. (Open output or output open)
As a result, it is possible to configure a multi-value numerical value discrimination circuit between the input terminal Tin and the output terminal Tout without using resistance means such as a resistor or a transistor in the current limiting mode (or resistance mode). (Effect of the first invention)

FIG. 2 shows an embodiment (.fwdarw. Embodiment 2) of the multivalue numerical value discrimination circuit of the first invention. In the second embodiment shown in FIG. 2, each component means corresponds one-to-one to each component means described in claim 1 as follows.
◆ a) “integer m−1, m, m + 1” is a continuous three integer “m−1, m, m + 1” in the same paragraph.
B) "The power supply lines _Vm-1 , _Vm , _{Vm + 1} " are the constant potential supply means _Vm-1 , _Vm , _{Vm + 1} in the same item.
◆ c) “the power supply potentials v _m−1 , v _m , v _{m + 1} ” are the constant potentials v _m−1 , v _m , v _{m + 1} in the same paragraph.
◆ d) The “binary NOT circuit formed by the transistors 81 and 82” is the first binarized NOT circuit in the same paragraph.
◆ e) The transistor 81 is “the high potential side transistor (→ bi-directional switch)” in the same paragraph.
Incidentally, when the back gate is connected to the source, the transistor 81 is a reverse conduction type (bidirectional switch that can be controlled only in one direction), and the back gate When connected to the highest constant potential in the circuit, the transistor 81 is a bi-directional controllable switch (= bi-directional switch capable of bi-directional control).
"The Institute of Electrical Engineers of Japan Nomenclature No. 9 Power Electronics Authors: "Special Committee on Electrical Standards for Electrical Engineering", "Subcommittee for Semiconductor Power Converters for Electrical Engineering, Editors", Editor: Electrical Society, Inc., Corona Corp. February 28, 2000 Revised version 1st print issued. "Bidirectional switch, bi-directional controllable switch, reverse conducting switch, reverse blocking switch". Note that "valve" has almost the same meaning as "switch".

F) The "two-value NOT circuit formed by the transistors 83 and 84" is the second two-value NOT circuit in the same paragraph.
G) The transistor 84 is “the low potential side transistor (→ bi-directional switch)” in the same paragraph.
H) The input terminal Tin is the inlet means in the same paragraph.
◆ i) The gate-insulated transistor 95 is a normally-off control electrode-insulated transistor described in the same paragraph.
J) The gate terminal and the source terminal of the transistor 95 become the “control terminal and main terminal forming a pair for driving signal input” described in the same paragraph.
◆ k) The drain terminal of the transistor 95 is the remaining main terminal of the fifth transistor in the same paragraph.
L) The threshold voltage v _th95 of the transistor 95 is equal to the threshold voltage described in the same paragraph.
Note that v _th95 in FIG. 2 means the (on / off) threshold voltage of the transistor 95, and the relational expression in FIG. 2 holds. That is, the absolute value of both the power supply potential _v of the threshold voltage _{v th95 m} + 1 · _v less than the potential difference between the _m-1, the potential difference between the power supply potential _{v m} + 1 · _{v m,} both the power supply potential _v m · _{v m-1} The potential difference between them is greater than either.
◆ m) The output terminal Tout is the outlet means in the same paragraph.
◆ n) “Connecting the source-gate portion of the transistor 95 in the gate forward bias direction” in the same paragraph “When the high potential side transistor and the low potential side transistor are on, the fifth transistor is It corresponds to "connecting to be driven on".

The circuit operation of the second embodiment of FIG. 2 is as follows. The input signal potential v _in input to the input terminal Tin is “the circuit threshold potential of the binary NOT circuit between both power supply potentials v _{m + 1} and v _m ” and “2 between both power supply potentials v _m and v _{m −1} If the value is between the circuit threshold potentials of the value NOT circuits, the transistors 81 and 84 are turned on. Therefore, the potential difference between the power supply potentials vm _{+ 1} and vm _-1 between the source and gate of the transistor 95 (= The transistor 95 is on because the voltage is applied in the forward direction.
At this time, the input numerical value N _in is determined to be the numerical value m, and the output potential v _out of the output terminal Tout is the power supply potential v _{m + 1} .
On the other hand, the input signal potential v _in input to the input terminal Tin is “the circuit threshold potential of the binary NOT circuit between both power supply potentials v _{m +1} and v _m ” and “between the two power supply potentials v _m and v _{m −1} of without between the circuit threshold potential of the binary NOT circuit ", between the source and gate of the transistor 95" dual supply potential _{v m} + 1 · _{v m} between either the two power supply potential _{v m} · _{v m-1} between "the Although a potential difference is applied in the forward direction, the transistor 95 is off because the gate forward bias voltage is insufficient, and the output terminal Tout is opened. At this time, it is determined that the input numerical value N _in is not the numerical value m.

More specifically, when the transistor 95 is off, the transistors 82 and 84 are turned on when the input signal potential v _in is higher than “the circuit threshold potential of the binary NOT circuit between both power supply potentials v _{m + 1} and v _m ”. made for a part of the charge energy between the source and gate of the transistor 95 is regenerated through the transistor 82 and 84 between both the power supply line V _m · V _m-1, both the power supply potential v _m between the source and gate The potential difference (= voltage) between v _{m −1} is applied in the forward direction. However, since the gate forward bias voltage is insufficient, the transistor 95 is off and the output terminal Tout is opened. (Open output or output open)
When the input signal potential v _in is lower than “the circuit threshold potential of the binary NOT circuit between both power supply potentials v _m · v _{m −1} ”, the transistors 81 and 83 are turned on. some charge energy between the source and gate is regenerated through the transistor 81 and 83 between both the power supply line V _{m + 1 ·} V _m, the potential difference between the power supply potential v _{m + 1 ·} v _m between the source and gate ( =) Voltage is applied in the forward direction. However, since the gate forward bias voltage is insufficient, the transistor 96 is off and the output terminal Tout is opened. (Open output or output open)
As a result, it is possible to configure a multi-value numerical value discrimination circuit between the input terminal Tin and the output terminal Tout without using resistance means such as a resistor or a transistor in the current limiting mode (or resistance mode). (Effect of the first invention)

In each embodiment, one P-channel type “IGBT (= gate insulated bipolar transistor) or normally-off control electrode insulated transistor” is used instead of each PMOS, and an N-channel type is used instead of each NMOS. Embodiments are also possible in which one "IGBT or normally-off control electrode isolated transistor" is used.
However, with regard to a transistor which is limited to being bidirectional switching means such as the transistors 81 and 84, it is a matter of course that the alternative transistor is bidirectional (eg reverse conduction type, bidirectional control type). There must be.
These matters also apply to each embodiment of the first invention and each embodiment of the second to sixth inventions using the first invention.

(1) A multi-value logic circuit based on the principle of the FUJI ALGE using the multi-value numerical discrimination circuit according to the first invention
In each of FIGS. 23 to 32, ten examples of multi-value EVEN (logic) circuits or multi-value NOT (logic) circuits based on the principle of Fourier algebra are shown, using Embodiment 1 or 2 (first invention).

FIG. 17 shows an embodiment of the "multi-value OR logic discrimination circuit based on the principle of the Fourier algebra" of the second invention (claim 2). The multi-value OR logic determination circuit of FIG. 17 is a “multi-value OR logic determination circuit based on the principle of hood algebra” in which three multi-value numerical value determination circuits (Example 1) of FIG. 1 and three diodes are combined. The three diodes form a diode OR circuit.
段落 段落 Paragraph numbers [0061 to 0062].

FIG. 18 shows an embodiment of the "multi-value OR logic discrimination circuit based on the principle of the Fourier algebra" of the second invention (claim 2). The multi-value OR logic determination circuit of FIG. 18 is a “multi-value OR logic determination circuit based on the principle of the hood algebra” combining three of the multi-value numerical value determination circuit (Embodiment 2) of FIG. 2 and three diodes. The three diodes form a diode OR circuit.
The circuit configurations of both the embodiments of FIGS. 17 and 18 are in a complementary relationship with each other.

FIG. 19 shows an embodiment of the "two-input multi-value AND logic discrimination circuit based on the principle of the Fourier algebra" of the third invention (claim 3).
In the fifth embodiment of FIG. 19, “the binary NOT circuit on the side of the transistors 81 and 82 in the multivalued numerical value discrimination circuit (first embodiment) of FIG. 1 is replaced by a binary CMOS NOR circuit of two inputs. The multi-value AND logic based on the principle of the hood algebra in which the binary NOT circuit on the 84 side is replaced by a 2-input binary CMOS NAND circuit and the NOR circuit and the two input terminals of the NAND circuit are connected one by one. Discrimination circuit ".

FIG. 20 shows an embodiment of the "two-input multi-value AND logic discrimination circuit based on the principle of the Fourier algebra" of the third invention (claim 3).
In the sixth embodiment of FIG. 20, “the binary NOT circuit on the side of the transistors 81 and 82 in the multivalued numerical value discrimination circuit (second embodiment) of FIG. 2 is replaced by a binary CMOS NOR circuit of two inputs. The multi-value AND logic based on the principle of the hood algebra in which the binary NOT circuit on the 84 side is replaced by a 2-input binary CMOS NAND circuit and the NOR circuit and the two input terminals of the NAND circuit are connected one by one. Discrimination circuit ".
The circuit configurations of both the embodiments of FIGS. 19 and 20 are in a complementary relationship with each other.

FIG. 21 shows an embodiment of the "three-input multivalued AND logic discrimination circuit based on the principle of the Fourier algebra" of the third invention (claim 3). The seventh embodiment of FIG. 21 is a 3-input version of the 2-input embodiment 5 of FIG.
In the seventh embodiment of FIG. 21, “the binary NOT circuit on the side of the transistors 81 and 82 in the multivalue numerical value discrimination circuit (first embodiment) of FIG. 1 is replaced with a 3-input binary CMOS NOR circuit; The multi-value AND logic based on the principle of the hood algebra that the 84-side binary NOT circuit is replaced with a 3-input binary CMOS NAND circuit and the NOR circuit and the two input terminals of the NAND circuit are connected one by one. Discrimination circuit ".

FIG. 22 shows an embodiment of the "three-input multivalued AND logic discrimination circuit based on the principle of the Fourier algebra" of the third invention (claim 3). The eighth embodiment of FIG. 22 is a three-input version of the six-input embodiment of FIG.
In the eighth embodiment of FIG. 22, “the binary NOT circuit on the side of the transistors 81 and 82 in the multivalued numerical value discrimination circuit (second embodiment) of FIG. 2 is replaced with a 3-input binary CMOS NOR circuit; The multi-value AND logic based on the principle of the hood algebra that the 84-side binary NOT circuit is replaced with a 3-input binary CMOS NAND circuit and the NOR circuit and the two input terminals of the NAND circuit are connected one by one Discrimination circuit ".
The circuit configurations of both the embodiments of FIGS. 21 and 22 are in a complementary relationship with each other.

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◆ ◆ ◆ ********** Finally, I will supplement the following. ********** ◆ ◆ ◆
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●● 1) For convenience of explanation, it is called the input terminal, the output terminal (equivalent to the inlet means and the outlet means in each of claims 1 to 10), but actually it does not exist as a terminal, but a simple conductor or electrode It is often the case. This is similar to, for example, a base terminal of a transistor, a base electrode, a base lead, or simply called a base.
●● 2) In each embodiment or each of its derivative embodiments, with respect to “each NMOS connected with its back gate and source”, its back gate is not “its source” but “means for supplying the lowest constant potential of its circuit {eg: It may be connected to the power supply line V ₀ or V ₋₁ }. Alternatively, it may be connected to other constant potential supply means whose potential is lower than the source potential. (Derivative example)
Further, in each embodiment or each of the derivative embodiments, with respect to “each PMOS connecting its back gate and source”, the back gate is not “the source” but “means for supplying the constant potential of the circuit {example: power supply line It may be connected to V _n-1 or V _n }. Alternatively, it may be connected to other constant potential supply means whose potential is higher than the source potential. (Derivative example)
●● 3) Instead of resistors 15, 20, 21, 26, 28, 62 to 64, 67 etc. in each embodiment or each of its derivatives, “junction FET or normally-on with its gate and source connected directly One type of MOSFET can be used as the resistance means, or a normally-off type MOSFET with its drain and gate connected. (Derivative example)
Furthermore, as long as there is no problem in the operation of the circuit, a constant current diode, “two constant current diodes connected in series in the reverse direction” instead of the resistors in each embodiment or each of the derivatives thereof, current mirror A circuit or constant current means with two terminals can be used one by one as resistance means. However, when using a constant current diode, constant current means, etc., pay attention to the voltage division ratio.
(Derivative example)

●● 4) In each embodiment or each of its derivatives, instead of each diode, “bipolar transistor with its collector and base directly connected”, “junction FET with its drain and source directly connected”, “the drain and Conduction between SIT or GTBT in bipolar mode with directly connected gates, "normally off type MOS FET with its gate, back gate and source connected" or "between its drain and back gate, between its source and back gate" It is possible to use one normally-off type MOS • FET ”in which the back gate potential is maintained and the drain and gate are connected so as not to be (Derivative example)
5) In each embodiment or each derivative embodiment, the levels of the respective power supply potentials are made to be opposite to each other, and each controllable switching means is "complementary with the controllable control means (example: for N channel type MOS.FET) “P-channel type MOS • FET” ”one by one, and“ symmetrical with respect to the voltage direction or voltage polarity ”with respect to the original example in which the direction of each component (eg, diode) having voltage direction or voltage polarity is reversed. Of course, an embodiment having a similar relationship is also possible. The respective embodiments having this symmetrical relationship correspond to the "case where the constant potentials are lowered in numerical order from the first constant potential to the N-th constant potential" in the first claim. However, in that case, since it corresponds to negative logic with respect to positive logic, the multi-valued logic function may be the same as or different from the original circuit. (Derivative example)
●● 6) In each embodiment or each derivative embodiment, the power supply line V ₀ or another power supply line is “the main body case of the circuit” or “the main body of the circuit device” or “the vehicle body such as automobile, motorcycle, bicycle etc. Or "a body of a ship or the like" or "a main body such as an amphibious hoover craft" or "a main body of a flight means such as an airplane or a helicopter" or "a main body of space navigation means such as a spacecraft or space station / space stray means Or, it is often connected to the Earth, Moon, Mars and other celestial bodies, etc., and the potential of the main body, body, hull and celestial body is often the reference potential of the ground potential such as earth potential. However, although one DC power supply or one DC power supply means for DC voltage supply is connected between each of "two power supply lines adjacent to each other at the level of the power supply potential", they are not shown.

●● 7) With the idea of “Beyond the CMOS”, various new elements such as quantum elements have been proposed, but ☆☆☆ CMOS also evolves! ! ! ☆☆☆ CMOS evolves towards 3D IC, multi-value, multi-augment, new concept computer (→ → paragraph number [0287-0292] described later)! ! !
Whenever you use multi-valued circuits, you will need to use the Fuge algebra. The reason is that the Fuge algebra has the ability to firmly support their practical application from the foundation. And, although CMOS compatible technology is already used for the light source of the optical circuit, if the optical circuit is going to be multi-valued, it will always be necessary to use the fuse algebra in this case as well. → → Paragraph numbers [0297 to 0301] described later.
One specific example of the CMOS evolution is the "bidirectional switch combining transistors 3 and 5" or "bidirectional switching means combining transistors 3, 5 and 22 to 25 (with diode 36)" in FIG. is there. → → Following Patent Document 6 (Japanese Patent Application Laid-Open No. 2006-252742).
Another example is the multilevel memory of FIG. 15 of Patent Document 8 (Japanese Patent Application Laid-Open No. 2007-035233) described below.
Moreover, even if a circuit is not a complete CMOS structure, there is no problem if the power consumption of the entire circuit is fundamentally low. For example, even when using a pull-up or pull-down resistor, in the circuit “a MOSFET that is in the on state during its operation and pulls the pull-up (or pull-down) resistor In the case of the circuit, the total number is always small, and "the total number of MOS-FETs etc. which are switched on / off during the operation is always small". It is predicted that this will be the case with an input / output pattern storage type decimal computer described later. → → Paragraph number [0287-0292].
On the other hand, despite the fact that current CPUs etc. are lumps (lumps) of CMOS circuits, the total number of "MOS · FET etc. switched on / off at high switching frequency" is extremely large. CPUs and so on are now like heaters because of the total switching loss including the power loss due to and the total power loss due to charging and discharging of their gate-source capacitances etc. .
JP 2006-252742 A (bidirectional switching means, multi-value buffer means, multi-value storage means) JP 2007-035233 A (multi-level decoding means, multi-level information processing means, etc.)

●● 8) With regard to the normally-off type MOS • FET used in the present invention, its withstand voltage between the drain and source and its withstand voltage between the gate and the source are maintained at a certain level (if possible), while their off time If the magnitude of the (on / off) threshold voltage can be reduced gradually while keeping the leakage drain current small, the 100-value (or 100-ary) computer and the 1000-value (or 1000-ary) computer (! ?) Also comes into view.
●● 9) Data input part of binary synchronous flip flop means (example: D terminal input part) which is one constituent means of the first and second inventions described later (paragraph numbers [0164 to 0284]) If the input integer meets the requirements of the numerical value determination means that determines whether the input integer is greater than or not greater than or less than the specified input integer, then the binary synchronous type It goes without saying that the flip flop means doubles as the numerical value judging means.

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In the explanation of the present invention, paragraph numbers about “Fuji Algebra” etc. just in case, so as to be able to treat the unfamiliar “Fuji Algebra” etc. in the same way as technical common sense. Will be described in detail.
After that, in the paragraph numbers [0214 to 0334], "multi-level logic means having synchronous latching function and multi-level hazard removal means" and the like will be described in detail so that they can be handled in the same manner as technical common sense.

◆ ◆ ◆ ◆ ***** Explanation of the new multi-valued logic "Hooji algebra" **** ◆ ◆ ◆
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◆ ◆ ◆ ***** Explanation of the new-multi-
value-logic, “Hooji algebra” **** ◆ ◆ ◆
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● ● 10) Each potential circuit (or voltage mode) multi-valued logic circuit that has been presented so far in the explanation "a totally new world's first multi-valued logic that the present inventor independently conceived at the time of 2002" Is an embodiment of the invention. However, it is inconvenient if there is no name for the new multi-valued logic, so I decided to name it "Hooji algebra" in 2010.
The multivalue-logics of circuits of which the 1st to 4th present inventions are on the basis, are circuits' embodied and realized 'from a'world's first '-&-' completely new'-multivalue-logic.
The new multivalue-logic, the present inventor thought out by him himself in the year 2002. And he called the logic “Hooji algebra” in the year 2010, because it was inconvenient in various ways if the logic has no name.
Reference: JP2010-149141 (application number in Japan).
In addition, in the multivalue-logic-circuits it is defined that each 'electric-potential or voltage' is one by one responsible to each numerical value used in the logic.
Generally, the definition is called 'electric-potential mode' or 'voltage mode'.

The reason why it was so named is that "I am a Japanese, so it belongs to Mt. Fuji, a symbol of Japan," and "Boolean" of "Boolean algebra" Whether it is (matching) or "ability, practicability, expansion extensibility, future potential, etc. including its ambiguity", it is huge {= out of step no matter what It is said that the word is aligned with the English huge (huge), since the present inventors strongly judge that it is large, tremendously large, huge. (Reference: following · Patent documents 1 to 3)
When the English name is decided, “H” in the “Huge” space, “oo” in the “Boole” space, and “ji” in the “Fuji” space are combined into “Hooji”. did.
The three reasons why the present inventor called the logic so, are the following.
(1) named from Mt. Fuji which is a symbol of Japan, because present inventor is a Japanese.
→ → the spelling of 'ji' picked out from the spelling of 'Fuji'.
(2) named a little from 'Bole' of Boolean Algebra.
→ → the spelling of 'oo' picked from the spelling of 'Boole'.
(3) named from the word of 'huge'.
Because the present inventor strongly judges that “Hooji algebra” has many huge strong points.
For example, 'the huge abilities to include an ability to express ambiguity', the huge probability, the huge practicability, the huge expansibility, the huge great future, etc. .
→ → the spelling of 'H' picked from the spelling of 'Huge'.
● To unite 'H', 'oo' and 'ji', the spelling becomes “Hooji”.
→ → ◆ ● '' H '+' oo '+' ji '⇒ Ho “Hooji”

Japanese Patent Application Laid-Open No. 2004-020322 (Multi-Valued Logic Circuit Based on 'Fuji Algebra') [filing date: March 10, 2003, priority date: March 11, 2002, May 7, 2002], (considered under). ◆ Reference patent no. 1: JP 2004-02032 A. Application date: March 10, 2003. First priority date: March 11, 2002. Second priority date: May 7, 2002. JP-A-2005-198226 (Expansion re-application of patent of patent document 1. Patent registration.) ◆ Reference patent no. 2: JP 2005-198226 A JP-A-2005-236985 (improvement of patent of patent document 2. patent registration) ◆ Reference patent no. 3: JP 2005-236985A

The reason for this judgment is that the multi-valued logic circuit based on the new multi-valued logic "Fuji Algebra" is as follows: "◎ whatever number of multi-valued number N is," a conventional multi-valued logic circuit There are a number of advantageous unique effects (⇒ in 2002, the world's first.) However, there is also an effect that did not notice its existence in 2002.
Speaking of the reasons for the present invention to cause there because of 'many advantageous-&-special effects not existing in any multivalue logic circuits of up to now now' in the new multivalue logic circuits on the basis of the new multivalue logic, “Hooji Algebra”, even if its multivalue number 'N' is any number.
Explaining the multivalue number 'N', that means the following number.
* That means '2' in case of 2 value.
* That means '3' in case of 3 value.
* That means '4' in case of 4 value.
* That means '10' in case of 10 value.
* That means 'N' in case of 'N' value.
The advantageous-&-special effects are as noted below.

A) When connecting a binary circuit to the previous stage, its connectivity is extremely good, and no special interface (eg, binary multi-value code conversion means) is required between them. Reference: Paragraph Number [0155]
To have extremely good connectivity, when connecting a 2 value circuit at the prestage of the new multi value logic circuit, and to need no special interface between both the circuits.
For example, a circuit for converting 2value-code to multivalue-code.
→ → minutely explained at 'paragraph number 0155 '.

B) Even when a binary circuit is connected to the subsequent stage, its connectivity is extremely good, and no special interface (eg, multi-value / binary code conversion means) is required in the meantime. Reference: Paragraph Number [0156]
☆ To have extremely good connectivity, when connecting a 2 value-circuit at the next stage of the new multi-value-logic-circuit too, and to need no special interface between both the circuits.
For example, a circuit for converting multivalue-code to 2value-code.
→ → minutely explained at 'paragraph number 0156 '.

C) As described in the prior application invention in the later paragraph (paragraph numbers [ 0164 to 0284 ]), the connectivity with the binary circuit is extremely good even during signal transmission in the multilevel logic circuit, and a special interface is in between It is not necessary. Reference: Paragraph Number [0195-0196 ]
To have extremely good connectivity, when insert-connecting a 2 value-circuit into one of fixed places on the process of signal communication in the new multivalue-logic-circuit.
☆ So, to need no special interface between both the circuits then.
→ → minutely explained at 'paragraph number 0195-0196 '.

D) For this reason, unlike the conventional multi-level circuit, multi-level hazards can be eliminated as in the present invention without conversion to binary. Reference: Paragraph Number [0199 ]
For this reason, ☆ to be able to eliminate directly multivalue-hazards like the preceding invention 'JP 2014-135709 A' of the present invention without converting the multivalue hazards into the 2value-hazards like multivalue-circuits of until now, by using the above .
→ → minutely explained at 'paragraph number 0199 '.

◆ e) Binary logic (non-inverting logic) AND (non-inverting logic) AND logic, OR logic, NOT logic, NAND logic, NOR logic, including basic logic circuits and having compatibility. Reference: Paragraph Number [0131 to 0132 ]
☆ To have compatibility with the 2 value-basic-logic-circuits on the basis of Boolean algebra.
That is, the logic-circuits on the basis of "Hooji Algebra" include some logic circuits on the basis of Boolean algebra.
For example, each circuit of (NON-REVERSE-logic), AND-logic, OR-logic, NOT-logic, NAND-logic, and NOR-logic on the basis of Boolean algebra.
→ → minutely explained at 'paragraph number 0131 to 0132 '.

F) In some cases, a plurality of “same basic and multilevel logic circuits different from each other in specific integer” may be used according to the multilevel number N, but a plurality of the same type basic and multilevel logic circuits The basic configurations of the power supply lines to be connected are just the same as each other, and they are completely the same and compatible. Reference: Paragraph Number [0129 to 0130 ]
☆ To have both 'compatibility' and 'completely the same basic structure', speaking about all of the same kind of plural basic-multivalue-logic-circuits' whose specific integers are different from each other.
The differences of the specific integers are due to differences of the power-lines which connect all the logic circuits to their power-sources.
And there are cases of using “the same kind of the plural basic-multivalue-logic-circuits” according to the multivalue number 'N' of a multivalue-circuit constructed by the logic-circuits and so on.
→ → minutely explained at 'paragraph number 0129 to 0130 '.

G) For this reason, it is possible to construct a large combined / multi-valued logic circuit with a large multi-valued number N on the basis of a combined / multi-valued logic circuit with a small multi-valued number N as it is. Reference: Paragraph Number [0133 ]
For this reason, ☆ to be able to construct 'the synthetic-multivalue-logic-circuits with the large multivalue-number' N '' on the base of those with the small multivalue-number 'N', by using the above compatibility etc . .
Of course, in these cases, the large are satisfied with the truth table of the small.
→ → minutely explained at 'paragraph number 0133 '.

H) The change of the multi-value number N is extremely easy. Reference: Paragraph Number [0133 ]
☆ To be extremely easy to change the multivalue number 'N'.
→ → minutely explained at 'paragraph number 0133 '.

◆ i) There is duality that "the duality always holds" regardless of the number N of multi-values. Reference: Paragraph Number [0126 to 0128 ]
☆ To have duality in the multivalue-logic even if the multivalue number 'N' is any number.
→ → minutely explained at 'paragraph number 0126 to 0128 '.

J) Able to represent all multilevel logic functions with one basic multilevel logic circuit (complete system) regardless of the multilevel number N.完全 性 完全 性 Completeness, that is also 'perfect'. Reference: Paragraph number [0134 to 0147 ]
To be able to express all the multivalue logic functions by using a kind of the basic-multivalue logic circuit (→ complete system) without relation to the largeness of the multivalue number 'N'.
Complete ''completeness', and that 'completeness of completeness'.
***
→ → minutely explained at 'paragraph number 0134 to 0147 '.

◆ k) It is very easy to “unitize or modularize” the basic multi-level logic circuit and the synthesis multi-level logic circuit. Reference: Paragraph numbers [0129 to 0130, 0133 ]
☆ To be so easy to make 'each circuit-unite or each circuit-module' of 'each basic-multivalue-logic-circuit and each synthetic-multivalue-logic-circuit'.
→ → minutely explained at 'paragraph number 0129 to 0130, 0133 '.

L) A plurality of logical variables “..., x, y, z, ...” and their respective multivalued numbers N (≧ 2) of their logical functions f (..., x, y, z, ...) are completely different from each other Also, there is the flexibility to cope flexibly without any problems. Reference: Paragraph Number [0154 ]
☆ x, y, z, ... 'and their logic-function' f (..., x, y, z, ... ) 'With no problem at all, even if each multivalue number' N (≧ 2, includes 2) 'of' ..., x, y, z, ..., f (..., x, y, z, ...) 'is completely different from each other.
→ → minutely explained at 'paragraph number 0154 '.

◆ m) Since a multi-level wired OR circuit is realized like a binary wired OR circuit, it is extremely advantageous in simplifying the overall circuit configuration and reducing the total number of parts. Reference: Paragraph Number [0148-0149 ]
☆ To be very advantageous both 'when simplifying the whole circuit structure' and 'when deciding total articles of the parts', as it is possible to construct multivalue-wired-OR-circuits as well 2 value-wired-OR-circuits.
→ → minutely explained at 'paragraph number 0148 to 0149 '.

◆ n) A (three-dimensional) programmable logic array or a semi-order (three-dimensional) IC / LSI can be realized in the “multi-level logic complete circuit”. Reference: Paragraph Number [0150 to 0153 ]
☆ To be possible to construct '(3 dimensional) programmable-logic-arraies', '(3 dimensional) semi-ordered-ICs &LSIs', etc. which 'embody and realize' multivalue-logic- "completeness of completeness" -circuits.
→ → minutely explained at 'paragraph number 0150-0153 '.

◆ o Eight new multi-valued logics that the inventor has further created, “OVER logic, NOVER logic, UNDER logic, NUNDER logic, IN logic, NIN logic, OUT logic, By using each multi-valued logic circuit such as NOUT (Nauto) logic, “fuzziness” can be defined and expressed freely and flexibly easily. Reference: Paragraph Number [0285-0286 ]
☆ To be 'freely, flexibly and easily' able to 'define and express' “ambiguity” by using each of 8 new-multivalue-logic-circuits etc. which the present inventor further created out.
The logics of their circuits are OVER-logic, NOVER-logic, UNDER-logic, NUNDER-logic, IN-logic, NIN-logic, OUT-logic, NOUT-logic, & c. .
These names are from golf terms in order to make it easy for everyone to memorize them.
→ → minutely explained at 'paragraph number 0285 to 0286 '.

In these multi-valued logic systems and circuits prior to the emergence of "Fuji Algebra", there were no unique advantageous effects / features that stood up in these cases.
So, "new / multivalued logic" Fuji algebra "is" the most faithful and orthodotically expanded / expanded Boolean algebra to now "and" includes its ambiguity expression ability "The ability, the possibility, the practicality, the expansion extensibility, the future, etc. are huge regardless of their nature," the inventor believes.
There were neither multivalue-logic-systems nor their circuits to have 'the above conspiciously advantage-&-special effects-and-characteristics' till “Hooji algebra” appeared.
For this reason, the present inventor is thinking that the new-multivalue-logic, "Hooji Algebra" is the logic to have applied-&-expanded Boolean algebra into the direction of multivalue 'most faithfully and most ortoxly until now'.
Further the present inventor is thinking that all of the following characteristics are huge.
'The abilities to include an ability to express ambiguity', the possibility, the practicability, the applicability-&-expansibility, the great future, etc. .

Until now, multi-value computers have not been widely and deeply put into practical use like binary computers, and the first major reason has not been developed: “In the case of binary, it becomes a foundation to firmly support binary circuits, and for practical use While "Boolean Algebra," which can be tolerated, has been used, in the case of multi-value, it has become a basis to firmly support multi-valued circuits, and there has been no multi-valued logic system that can withstand practical application. " The inventor thinks that it is a body.
The present inventor thinks of the reasons why multivalue-computers have been 'neither put into practical use nor developed'widely-&-deeply until now like 2value-computers as the following.
● The main big reason:
As against that there was the 2value-logic-system'Boolean algebra 'to be able both to foundation which firmly supports all 2value-logic-circuits' and 'to end their practical application' in case of the 2value-computers,
There was no multivalue-logic-system to be able to both the foundation which was firmly supported all multivalue-logic-circuits' and 'to end their practical application' in a case of the multivalue computers.
Other than that, three-dimensional IC technology and "low voltage drive (= small absolute value of on / off threshold voltage) and high withstand voltage compatible technology" is particularly important, energy saving and cooling technology, Also important are multi-level hazard removal techniques and techniques for suppressing the damped oscillations of the input signal such as overshooting and undershooting.
Besides, the following technologies are especially important for the multivalue computers.
(1) 3 dimension IC (includes LSI) technologies.
(2) Compatibleness technologies of transistors' low-voltage-driving (= the small absolute value of its on-off threshold voltage) and its high-voltage-proof.
(3) Technologies to save energy for the multivalue computers to consume.
(4) Technologies to cool the multivalue computers, and so on.
(5) Technologies to prevent appearance of multivalue-hazards.
(6) Technologies to suppress damped-oscillations of input-sygnals such as overshooting and undershooting.

As such, to be the basis of multi-valued computers, "compatible with binary logic," Boolean algebra "and completely including it", and yet, "same basics different in multi-valued number N from each other・ Multi-level logic circuit ・ There is compatibility among each other, and the larger one of the multi-level number N completely includes the smaller one. ”Furthermore,“ the logic function and [1 Regardless of the number N (≧ 2) of multiple values of one or more logical variables], even if they are completely different from each other, they are not affected at all, and their functions can be exhibited freely and flexibly. The inventor believes that it is necessary.
In order that the multivalue-logic-system becomes the foundation of the multivalue-computers like so, the present inventor thinks that the system moreover needs the following workings.
● The 1st working:
The multivalue-logic-system is compatible with the 2value-logic-system'Boolean algebra 'and the former logically-&-perfectly includes the latter.
● The 2nd working:
As regards all the same kind of the basic-multivalue-logic-circuits to have the different multivalue-number "N" each other ', they are compatible each other, and the large of' N 'perfectly includes the smaller of' N '.
Of course, the large is satisfied with the truth table of the small.
● The 3rd working:
The multivalue-logic-system can freely-and-flexibly fulfills each working of their multivalue-logic-circuits, with no relation to the largeness of the multivalue-number 'N (≧ 2, includes 2)', and with no influence at all even if it is any number each number 'N (≧ 2)' of 'the logic-function and its' one or plural logic-variables ''.
And no problem at all even if the each number 'N (≧ 2)' is completely different from each other.
However, in the case of a synthetic multilevel logic circuit of multilevel number N based on the Fourier algebra, there are cases where all the same basic multilevel logic circuits whose specific integer values are 0 to (N-1) may be used, but As described in the section f), the same kind of basic multilevel logic circuits are compatible with each other.
But in a case of synthetic-multivalue-logic-circuits both 'with the multivalue-number' N 'and' on the basis of Hooji algebra ', though there is more over a case too when used all the same kind of basic-multivalue- logic-circuits whose special-integer-values are 0 to (N-1), as explained at Item f), the same kind of basic-multivalue-logic-circuits are compatible with each oth r.

By the way, "the number of types of multi-level logic functions that can be represented", that is, "the number of types of information processing that can be represented" increases ultra-explosively as follows, as the multi-level number N increases. Furthermore, if the number of each digit is also used, it can be super -..... super-explosively increased, and it can easily surpass "the number of types of information processing by programming of program storage type (= built-in type) computer type" (!!! Therefore, for example, a computer system of a new concept without using a program becomes possible with a 10-value decimal computer.
Changing the speaking, the larger the multivalue-number 'N' is, the more 'the number of the kinds of the multivalue-logic-function to be able to express' increases ultra-explosively.
That is, the more 'the number of the kinds of information-processing to be able to express' increases ultra-explosively as the following numbers of the kinds.
In addition to the increasing value of the multivalue-number 'N', the more 'the number of the figures (= digits) of the numerical-values utilized in the multivalue-logic-function' increases, the more 'the number of the kinds of the information-processing 'increases ★ ultra-ultra ... ultra-explosively as the following number of the kinds.
As the result, 'A New-Concept-Computing-Method not to use programs concerning 10 values-Decimal-Computers for example' becoming possible, because 'the number of the kinds of information-processing' can easily exceeded 'the number of the Kinds of the information-processing which "the Computing-Method of Program-Memorizing-Type" can express by their programing '.

◆ ◆ Example of the number of types such as 10-valued logic function ◆ ◆
However, the number of each (multi-level) logic variable is two.
◆ ◆ for examples, the number of the kinds of 10 values-logic-function etc. ◆ ◆
But two variables per each multivalue-logic.
And each Chinese character means in Japan as follows.
◆ 'value' means 'a value' or 'values'.
◆ 'Digits' means 'a figure', 'figures', 'a digit' or 'digits'.
◆ 'Logical variables' means 'a logic -variable' or 'logic-variables'.
◆ 'kinds' means 'a kind' or 'kinds'.
***
* Binary 1 digit 2 logic variable → → 2 4th power · type = 16 types 2 value-1 figure-2 logic-variables → →
2 ⁴ kinds = 16kinds
* 3 values 1 digit 2 logical variables → → 3 to the 9th power · type = 19, 683 types (= kinds)
= 3 ⁹ kinds
* 4 values 1 digit 2 logical variables → → 4 to the 16th power · type 4 4, 294, 968,000 types = 4 ¹⁶ kinds
* 5 values 1 digit 2 logical variables → → 5 to the 25th · kind = 5 ²⁵ kinds
* 6 values 1 digit 2 logical variables → → 6 to the power of 36, types = 6 ³⁶ kinds
* 7 values 1 digit 2 logical variables → → 49 to the power of 7 · types = 7 ⁴⁹ kinds
* 8 values 1 digit 2 logical variables → → 8 to the power of 8 = 8 ⁶⁴ kinds
* 9 value single-digit second logical variable →→ 9 of 81 square-type ⁼ 9 81 kinds
* 10 values one digit 2 logical variables → → 10 to the power of 100 · kind = 10 ¹⁰⁰ kinds
* 10 values 2 digits 2 logical variables → → 10 to the ^10,000th power · type = 10 ^10,000 kinds
* 10 values 3 digits 2 logical variables → → 1 to 10 million power · type
= 10 ^1,000,000 kinds
* 10 values 4 digits 2 logical variables → → 10 to 100 million power · type
= 10 ^100,000,000 kinds
* 10 values 5 digits 2 logical variables → → 10 billions of power · type
= 10 ^{10,000,000,000} kinds
* 10 values 6 digits 2 logical variables → → 1 to 10 power of 10 types
= 10 ^{1,000,000,000,000} kinds
* 10 values 7 digits 2 logical variables → → 10 to the power of 100 trillion · type
= 10 ^{100,000,000,000,000} kinds
* 10 values 8 figures 2 logic variables → → 10 1 kyo (= 1,000,000 trillion) · type 10 value-8 figures-2 logic-variables → →
→ → 10 ^{10,000,000,000,000,000} kinds
■ Patent Document (Patent-document) 8 ■
Paragraph number [0029-0033] of Unexamined-Japanese-Patent No. 2007-035233 (JP2007-035233A).

Correctly speaking, “the number of types of information processing by programming”, whatever the multi-value number N (≧ 2), rather than the above “lightly surpassable (!!!)”. Can never exceed “the number of types of logic functions that can be expressed using its number of digits”.
Exactly speaking, 'the number of the kinds of information-processing by the programing' can ★ absolutely-not excluded 'the number of the kinds of the logic-function to be able to express both' by increasing its multivalue-number 'N (≧ 2) “'and' by utilizing its number of the figures', even if the multivalue number 'N (≧ 2)' is any number. ★ ★ Absolutely-not! ! !

The reason is as follows. Also in the "information processing by program", the function contents as the information processing means can be determined only from the in / out of the "data or information" regardless of the process of the information processing.
The reason is as the following. It is possible to discriminate what kind of work information-processing-means-through-only input-&-output of its data-or-information with no relation to information-processing has been done.
And both "each individual input" data or information "and" each individual information processing result to this "must be all combinations of numbers, so! That is, since the information can be represented by a truth table, the information processing content can not absolutely exceed "the number of types of logic functions that can be represented by the truth table".
And it's possible to express certainly both 'all the input-data-or-input-information' and 'all the information-processing-results gotten from their data-or-information' by combinations of numerical values.
So! ! ! That is, because the combinations too can be expressed by a truth table, 'the number of the kinds of information-processing by the programing' can ★ absolutely-not exceeded 'the number of the kinds of the logic-function to be able to express by the truth table '. Absolutely-not! ! !
Moreover, the number of types of "information processing that is created by programming, useful for people, and used actually" does not seem to be any number and 10 to the power of 100.
In addition, the present inventor does not think there are the 10 ¹⁰⁰ kinds of information-processing which are made by the programing, useful to human and used in practice '.
■■ Patent document 8 (◇)
Paragraph No. of Unexamined-Japanese-Patent No. 2007-035233 (JP2007-035233A).
→ → minutely explained at 'its paragraph number 0029 to 0033'.

◆ ◆ ◆ ***** Duality of "Hooji Algebra" ****** ◆ ◆ ◆
***
● ● 11) The property of “newness (that is true) regardless of the multivalue number N”, “duality”, etc. of the new / multivalue logic “fuge algebra” will be described below.
“Fuji Algebra” is “a binary Boolean Algebra expanded and expanded into multiple values faithful to the present inventors * by the present inventors”, so naturally the multiple value (specific value) NOT logic, multiple value (specific value) The "dual" holds for AND logic and multi-value (specific value) OR logic.
“Duality in Boolean algebra” means “in the identity of any logical function composed of NOT logic, AND logic or OR logic, transpose“ 1 ”and“ 0 ”on both sides, and at the same time AND logic and OR logic Even if they are interchanged, the identity holds.
Figure 33-34 shows that holds true even in "Fuji Algebra", "double negation theorem Boolean algebra, De Morgan theorem, the theorem that likewise correspond to the respective duality". Below, I will explain one by one.
***
“Introductory Lecture on Transistor Circuit 5: Concept of Digital Circuit”, p. 27 to p. 31 "3 · 3 Boolean algebras (1) axioms (2) theorem (3) duality", supervision: Yoshifumi Amamiya, Norii Kojima (author), author: Kensuke Shimizu (Konsuke), Masakazu Susumu (Masahiro), published by Ohm Co., Ltd. May 20, 1959.

First, an equivalent circuit of each of the OR circuit and the AND circuit already known in Boolean algebra will be described.
★ ★ Equivalent circuit of OR circuit:
* From the theorem of double negation "OR logic of A and B" = A + B
= "(A + B) double denial"
* From the de Morgan's theorem "(A + B) double denial" = "(a denial of A) · (a denial of B) denial"
= "Negation of AND logic of (Negation of A) and (Negation of B)"
* Therefore,
"OR logic of A and B" = "Negation of AND logic of (Negation of A) and (Negation of B)" ......
... ... ... ... ... ... ... ... ... ... ... ... ... ... Expression (1)
★ ★ Equivalent circuit of AND circuit:
* From the double negation theorem "AND logic of A and B" = A · B
= "Double denial of A and B"
* From De Morgan's Theorem "A-B's double denial" = "{(A's denial) + (B's denial)} 's denial"
= "Negation of the OR logic of (the denial of A) and (the denial of B)"
* Therefore,
"AND logic of A and B" = "Negation of OR logic of (Negation of A) and (Negation of B)" ......
... ... ... ... ... ... ... ... ... ... ... ... ... ... Expression (2)
★ ◆ ★ Duality in Boolean algebra;
Equations (1) and (2) exchange “1” and “0” on their both sides, and at the same time exchange the AND logic and the OR logic.

Duality in New and Multivalued Logic [Hooji Algebra:
Then, "regardless of the number of levels N in Shin multivalued logic [Fuji (Hooji) algebra, dual it (so marked) property holds" on the basis of each-multi-valued logic circuit of FIG. 33 to 34, etc. Will be explained.
However, m = specific integer for input = specific integer for output, v _m is "potential corresponding to specific integer m", v _Cm (≠ v _m ) is "potential corresponding to integer other than specific integer m" or "which Independent additional potentials that do not correspond to integers, that is, “potentials that can be any potential that each multi-valued AND, OR, and NOT circuit does not determine that the input numerical value is a specific integer m”. Note that represents the power line of the power supply potential _{v m} in _{V m,} represents the power line of the power supply potential _{v Cm} at _{V Cm.}
Also, "NOT (m) = m" is abbreviated, and the input specific integer = output specific integer = m multi-value NOT circuit, "AND (m) = m" is abbreviated input specific integer = output specific “OR (m) = m” is abbreviated to mean a multi-value AND circuit of integer = m, and a multi-value OR circuit of a specific integer for input = a specific integer for output = m.
It is noted that each definition of multilevel {specific value (= specific integer)} NOT logic, multilevel (specific value) AND logic, multilevel (specific value) OR logic is as follows.
◆ Multi-value NOT logic: “release its output” when its input number is equal to a specific integer m, otherwise it outputs a specific integer m.
◆ Multi-value AND logic; output a specific integer m when all its input numbers are equal to a specific integer m, otherwise "open its output".
◆ Multi-value OR logic: output a specific integer m when at least one input numerical value is equal to a specific integer m, otherwise "open its output".
In the equivalent circuit of the multi-value OR (m) circuit of FIG. 33 , “when at least one of the input logical variables x and y is an integer m, the logic function f (x, y) outputs a specific integer m, otherwise It is understood that the output is "opened". Moreover, the value of m is a free value from minus integer to plus integer.
On the other hand, in the equivalent circuit of the multi-level AND (m) circuit of FIG. 34 , “when all of the input logical variables x and y are integers m, the logic function f (x, y) outputs a specific integer m, For example, it is understood that the output is "opened". Again, the value of m is a free value from minus integer to plus integer.
Moreover, since it is extremely easy to change the multi-value number N as described in (14) below (paragraph number 0133 ), “new / multi-value logic [fuge algebra] regardless of the multi-value number N, at least double negation It is understood that theorem, de Morgan theorem, duality theorem hold.

◆ ◆ ◆ ***** The changeability of a specific integer not affected by the multi-value number N ***** ◆ ◆ ◆
***
●● 12) The multi-valued logic circuit based on “Fuji Algebra” has no effect on the multi-valued number N [[Modability of specific integer value m] and [very easy circuit unitization or modularization ( Unique effects)]] will be described below.
◆ Following ・ EQUAL (or judgment) circuits, AND circuits, OR circuits, OR circuits, NOT circuits, NAND circuits, NOR circuits disclosed in the patent documents of Patent Literatures 1, 2 and 3 and their derivatives In the case where the output switch unit is bi-directional, the specific integer m is (n-2) m m 1 1, but the circuit may be separate even if "m = n-1" or "m = 0" separately There is no problem at all in operation and logic, and the value of the specific integer m can be freely set in the range of (n-1) ≧ m ≧ 0. However, only the potential supply means (eg, power supply line etc.) to be connected is changed.
However, in the case of m = n-1, electric potential v (n-1) [In this invention, it describes with v _n-1 . In the present invention, it is denoted by v _{n above} . Power supply line Vn for supplying [in the present invention, denoted by V _n . Or the like, or there is an extra function or component such as “determine based on the threshold voltage on the positive side” or the like.
In the case of m = 0, denoted by _{v 0} is the potential v0 [present invention. Under the electric potential v (-1) [in the present invention, denoted by v _-1 . Power supply line V (-1) [in the present invention, denoted as V _-1 . ], Or there is an extra function or component such as “determine based on the threshold potential on the negative side” or the like.
Moreover, the specific integer m may take any free value from integer 0 to plus integer. In any case, the value of the specific integer m can be freely changed simply by changing the "potential supply means (for example, power supply line etc.) to be connected".
For this reason, it is not necessary to consider the difference in the specific integer m if they are the same multilevel logic, and it is sufficient to keep the same circuit configuration, so "unitization or modularization" of the circuit is possible for each type of multilevel logic. Become. (Unique effect)
☆ ☆ Example of circuit:
· Each-asynchronous-multilevel NOT {or Neven (Niven or Nebun)} asynchronous-multilevel EVEN circuit-FIGS. 48 to 49 of Figure 47 circuit.
- FIGS. 50 to 51, each-asynchronous-multilevel AND circuit-52 of Figure 53, each, asynchronous, multi-level NAND circuit-FIG. 55 in FIG. 54, each, asynchronous, multi-value OR in FIG. 57 Circuits · Fig. 56 , each of Fig. 58 · Asynchronous · Multi-value NOR circuit
Japanese Patent Application Laid-Open No. 2004-020322 (Multi-valued logic circuit based on new and multi-valued logic "Fuge algebra") JP 2005-198226 (ibid) JP 2005-236985 (ibid)

◆ Also, "IN circuit, OUT circuit, NIN (Nin) circuit, NOUT (Nout)," also "OVER circuit, UNDER circuit, NOVER (Nounbar) circuit, NUNDER (Nander) circuit", described later (Paragraphs 0179 to 0185 ) Even in the case of "circuit", the integer can be freely set within the limited "specific integer for one or two inputs" setting range. However, only the potential supply means (eg, power supply line etc.) to be connected is simply changed.
Here as well, it is not necessary to consider the difference between each specific integer m if they are the same multilevel logic, and it is sufficient to keep the same circuit configuration, so "unitization or modularization" of the circuit is possible for each type of multilevel logic become. (Unique effect)
◆ In addition, in each case, as described later (paragraph number 0133 ), there is a feature that "the change of the multi-value number N is extremely easy", so "the changeability of a specific integer" is also "a very easy circuit Unitization or modularization] is not affected at all by the multi-value number N.

◆ ◆ ◆ ********** "Fuji Algebra" including Boolean Algebra ******** ◆ ◆ ◆
***
● 13) New and multi-valued logic "Hooji algebra" includes Boolean algebra of binary logic, and it is explained below that there is compatibility.
The new multi-valued logic "Fuji Algebra" is a faithfully expanded / extended binary logic Boolean algebra to multi-valued in the manner of the present inventor, completely including Boolean algebra and compatible with Boolean algebra .
For example, each output of a multi-level specified value EQUAL {or EVEN (even) or non-inverted} circuit, an AND circuit, an OR circuit, a NOT {or NEVEN (even) circuit, a NAND circuit, a NOR circuit whose specific integer value is 1 If the terminals are pulled down to the potential v ₀ of the power supply line V ₀ by resistors and each input numerical value is limited to “1” and “0”, these multilevel logic circuits are buffers of binary / positive logic (or Non-inverting circuit, AND circuit, AND circuit, OR circuit, NOT circuit, NAND circuit, and NOR circuit operate in exactly the same logic and are compatible.
Then, each output of a multi-level specified value EQUAL {or EVEN (even) or non-inverted} circuit, an AND circuit, an OR circuit, a NOT {or NEVEN (even) circuit, a NAND circuit, a NOR circuit whose specific integer value is 0 terminal pulled up to the potential v ₁ of the power source line V ₁ in the resistor, if only each input number in the "1" and "0", these multi-valued logic circuit is binary and negative logic buffer ( Or, it has the same logic operation as the non-inverting circuit, the AND circuit, the OR circuit, the NOT circuit, the NAND circuit, and the NOR circuit, and is compatible.
On the other hand, Boolean algebra composed of “AND circuit (= Min circuit), OR circuit (= Max circuit), inversion circuit (complement) circuit, literal circuit (literal circuit) and cycling circuit” is developed into multi-values In the case of the extended conventional multilevel logic circuit (Ukashevich type), all multilevel circuits are Boolean algebras with respect to "inverted circuit, literal circuit and cycling circuit" in which the binary NOT circuit is expanded and expanded to multiple values. Does not include the binary NOT circuit of and is not completely compatible.
Therefore, it goes without saying that the conventional multi-level NAND circuit and multi-level NOR circuit also do not include Boolean binary NAND circuits and binary NOR circuits, and there is no compatibility at all.
★ Reference: p. 18 to p. 20.
"Multi-value information processing-post-binary electronics-" Authors: Tatsuo Higuchi, Michitaka Kameyama (Michitaka), Shokodo (Shikokodo) published in June 1989. "Mathematical science February issue (1980, No. 200) Feature: Multivalued Logic", published by Science Co., Ltd. on February 1, 1959.

Here, consider, for example, the case where there are “a plurality of multi-level AND circuits having different specific integer values” in a 10-value logic circuit based on “Fuji algebra”. However, in each multi-value AND circuit, the input specific integer value and the output specific integer value are the same value.
"The AND circuit of the specific integer value 8 corresponding to the power supply potential v ₈ is defined as" the electric potential v ₀ of the power supply line V ₀ corresponds to the integer 0, etc. " if it potential v ₇ of the power supply line V ₇ is redefined as such and the corresponding integer 0 ", the particular integer value becomes 1. In this case, “binary AND compatible circuit based on Boolean algebra” is formed between the power supply lines V ₇ and V ₈ , and the AND circuit based on “Fuji Algebra” is “binary AND circuit based on Boolean algebra ( In particular, it is completely compatible with the open drain type and the open collector type.
Similarly, if the power supply potential to turn from the power supply line V ₆ to the power supply line V ₁ is redefined as such and the corresponding integer 0, integer value corresponding to the potential v ₈ of the power supply line V ₈ below It becomes like.
And potential of the power supply line _{V 6 v 6} →→ integer 2
And potential _{v 5} →→ integer value 3 of the power supply line _{V 5}
And potential _{v 4} →→ integer value 4 of the power supply line _{V 4}
And potential of the power supply line _{V 3 v 3} →→ integer 5
And potential of the power supply line _{V 2 v 2} →→ integer value 6
Of - the power line _{V 1} voltage _{v 1} →→ integer value 7
During these redefinitions, the electronic circuit does not change or change the circuit configuration at all, and is completely identical.
As described above (paragraphs 0129 to 0130 ), in the case of various multi-valued logic circuits based on "Fuji Algebra", the change of the specific integer m is "one or more connected to the multi-valued logic circuit". This is because it is sufficient to simply change the plurality of power supply lines.
As a result, for example, in the case of a 10-value logic circuit, the “multi-value AND circuits having different specific integer values” used therein will be described as follows.
* Number of used multi-value AND circuits of specific integer value 0 → → 0 to multiple.
* Number of used multi-value AND circuits of specific integer value 1 → → 0 to multiple.
* Number of used multi-value AND circuits of specific integer value 2 → → 0 to multiple.
* ......................................................................................
* ......................................................................................
* Number of used multi-value AND circuits of specific integer value 8 → → 0 to multiple.
* Number of used multi-value AND circuits of specific integer value 9 → → 0 to multiple.
In the 10-value logic circuit, the multi-value AND circuits are completely compatible with each other, regardless of the number of used values of each multi-value AND circuit. Since there is complete compatibility with the binary AND circuit, the all-multilevel AND circuit of this 10-valued logic circuit can be expressed or configured by the binary AND circuit of Boolean algebra.
The same applies to multi-value OR circuits, multi-value NOT circuits, multi-value NAND circuits, and multi-value NOR circuits, and to multi-value logic circuits other than 10 values.

◆ ◆ ◆ *************** Mutability of N is easy to change.
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●● 14) On the unique effects and features of “The change of multi-value N is extremely easy” of the new multi-value logic “Hooji algebra”:
As described above (paragraph numbers 0129 to 0130 and 0132 ), since the change of the specific integer m is very easy, the change of the multi-value number N is also very easy.
For example, in each basic and multilevel logic circuit such as the AND circuit, OR circuit and NOT circuit, the same kind of basic and multilevel logic circuit groups having different multilevel numbers N are compatible with each other. The larger one contains the smaller one. The reason is that the "multi-value number N" can be added simply by adding "basic / multi-value logic circuits whose basic configurations are exactly the same even if specific integers differ from each other (= only different power supply lines are connected)". Can be easily changed.
Further, for example, if it is desired to change to five values when combining and multilevel logic circuits are formed with four values using basic and multilevel logic circuits such as AND circuits, OR circuits, NOT circuits, potential supply means (example: Power supply and power supply line.) Added, and “specific integer for input or specific integer for output is set to“ 5 ”etc. (that is, determined the power supply line etc. to be connected), various necessary“ basic The multi-level number N can be extremely easily changed only by adding the multi-level logic circuit or the multi-level logic circuit unit or making the necessary connection.
As a result, it is possible to construct a "large multi-value N combined / multi-valued logic circuit" based on the "small multi-valued number N small combining / multi-valued logic circuit" as it is. In this case, as a matter of course, the five-value synthesis / multi-value logic circuit satisfies the truth table of the four-value synthesis / multi-value logic circuit.
***
On the other hand, in the case of a multi-valued logic circuit based on "the multi-valued logic such as Ukashevich, which has been developed / expanded into multi-valued Boolean algebra" as the prior art, the binary NOT is as described above (the second paragraph). With regard to “invert circuits, literal circuits and cycling circuits” in which circuits are expanded and expanded into multiple values, no multilevel logic circuit includes a binary NOT circuit and is not only incompatible at all, but also its number N The same kind of basic and multivalued logic circuits different from each other can not be included, and there is no compatibility at all.
For example, "three-valued inverting circuit and four-valued inverting circuit", "three-valued literal circuit and four-valued literal circuit", and "three-valued cycling circuit and four-valued cycling circuit". The same applies to other multivalued numbers.
Therefore, with respect to these basic and multilevel logic circuits, it is not possible to construct a "basic and multilevel logic circuit having a large number of multilevels" on the basis of "a basic and multilevel logic circuit having a small number of multilevels" as it is. Naturally, the same can be said of multi-value NAND circuits and multi-value NOR circuits to which these basic and multi-value logic circuits are applied.
As a result, it is possible to construct a "combination / multi-value logic circuit with a larger number of multi-values" based on the "synthesis / multi-value logic circuit using even one of these basic / multi-value logic circuits" as it is. Because it is impossible, it is extremely difficult to change the multi-value number N. It is necessary to reassemble from 1.

◆ ◆ ◆ ********** "Fuji's Algebra" perfection ***** ***** ◆ ◆ ◆
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●● 15) Unique effect / characteristic of "completeness by one type of multi-valued logic circuit which is not influenced by multi-valued number N at all, it is" complete "" in new multi-valued logic "Hooji algebra" Will be described below. → → Realize multi-valued logic complete circuit.
According to the above-mentioned (paragraph numbers [ 0126 to 0129 ]) "duality that duality ( stiff ) holds regardless of multivalued number N" or the like, "multivalued NAND logic or multivalued NOR logic, either one type of multivalued Completeness that can realize all multi-valued logic functions regardless of their multi-value number N [by itself] or [by combining multiples], the effect / characteristic of it is also “complete” "Algebra".
“Introduction to logic circuits”, p. 31 (8) Complete System. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd., September 28, 2001. “A well understood digital electronic circuit”, p. Line 14 of 9 ~ p. "Complete system" of the first line of ten. Author: Sekine Keitaro, Inc. Ohm company published on July 25, 1997. "Multi-value information processing-post binary electronics-", p. 16 to p. 17 contents of "completeness, complete system, complete". Author: Takao Higuchi, Michitaka Kameyama (Michitaka), Shokodo (Shokodo) published in June 1989.

Based on the synthetic / multilevel logic circuit of FIG. 35 , "It is easy to understand in electronic circuit engineering" and the "perfectness" will be described below.
◆ However, multi-valued number N = 10 (decimal system), each specific integer m (= specific integer for input = specific integer for output) and each power line potential (example: v _{0 to} v ₉ , v _C0 As to v _C9 , v _C0 ≠ v ₀ , v _C1 ≠ v ₁ , ........., v _C8 ≠ v ₈ , v _C9 ≠ v ₉ ), each integer m (= 0, 1, 2, 3, .., 8 and 9) are written, but the definition of each basic / multilevel logic circuit is as described above (the first half of paragraph number 0132). Note that represent each power line of the power supply potential _v 0 to v ₉ at _V 0 ~V _9, represent the respective power line of the power supply potential _v C0 _{to v C9} in _V C0 _{~V C9.}
◆ Also, as in the case of the binary logic circuit, “connect all the input terminals of the multi-value NAND circuit and combine them into one input terminal” or “leave one input terminal of the multi-value NAND circuit but do not If all input terminals are connected to a power supply line or the like of the input specific potential v _m (= power supply potential corresponding to the specific integer m for the input) of the NAND circuit, the multilevel NAND circuit It becomes a circuit.
★ Each of FIGS. 52 and 54・ Asynchronous type ・ Multi-value NAND circuit ★ Reference: Japanese Patent Application Laid-Open No. 2005-236985 ・ FIG. 11 multi-value (specific value) NAND circuit (3 inputs).
◆ Furthermore, the output terminal of the multilevel NAND circuit is pulled up or down with a resistor etc. to the power supply potential v _Cm (≠ v _m ) other than the input specific potential (= output specific potential) v _m of the NAND circuit. If the above "multi-level NOT circuit" is connected to the subsequent stage of its output terminal, the multi-level NAND circuit becomes a multi-level AND circuit.

◆ Alternatively, as in the case of the binary logic circuit, “connect all the input terminals of the multi-value NOR circuit and combine them into one input terminal” or “leave the other input terminal of the multi-value NOR circuit If all the input terminals of the NOR circuit are connected to the power supply line of the power supply potential v _Cm (≠ v _m ) other than the input specific potential v _{m of the} NOR circuit, the multilevel NOR circuit become.
★ Each of FIGS. 56 and 58・ Asynchronous type ・ Multi-value NOR circuit ★ Reference: Japanese Patent Application Laid-Open No. 2005-236985 ・ FIG. 13 multi-value (specific value) NOR circuit.
◆ Then, pull up or pull down the output terminal of the multi-value NOR circuit to the power supply potential v _Cm (≠ v _m ) other than the input specific potential (= specific potential for output) v _m of the NOR circuit. If the "multi-value NOT circuit" is connected to the subsequent stage of the output terminal, the multi-value NOR circuit becomes a multi-value OR circuit.
◆ Moreover, as described above (Figures 33 to 34 and paragraph numbers [ 0126 to 0128 ]), the characteristic of "the duality of the new / multilevel logic" Fuji algebra "" allows the multilevel AND circuit to be used Conversely, it is possible to construct a multi-value OR circuit or the like from the multi-value AND circuit.
For this reason, one type of multi-value NOR circuit constitutes a multi-value OR circuit, a multi-value AND circuit, a multi-value NOT circuit, a multi-value NAND circuit, or one kind of multi-value NAND circuit The multi-value NOT circuit and the multi-value NOR circuit can be configured.
As a result, there is also the feature of "the easiness of changing the specific integer m which is not influenced by the multi-value N at all" as described above (paragraph numbers [ 0129 to 0130 ]). It can be understood that the combination / multi-level logic circuit of FIG. 15 can be configured with only one type of basic / multi-level logic circuit of either “multi-level NAND circuit or multi-level NOR circuit” based on

Then, the composite / multi-level logic circuit of FIG. 35 can realize or actualize "all multi-level logic functions represented by the truth table of the multi-level logic function f (x, y) shown in FIG. 36 ". It is a logic perfect circuit. However, FIG. 36 is considerably omitted and simplified for easy understanding and explanation.
The truth table of f (x, y) shown in FIG. 36 is all of the decimal 2 logical variables x and y by rewriting the numerical pattern, that is, rewriting the numerical value of each. A multi-valued logic function (total of 10 to the power of 100) can be expressed.
The reason is that there are ten integer numbers “0 to 9” that can be taken by one eyelid, and the total number of squares is 100 in total, so the numerical patterns that can be taken by 100 squares are all in all. (10 ways) × (10 ways) × ...... <<<< product of 100 (10 ways) of each other >>>> ...... × (10 ways) × (10 ways) = 10 to the power of 100 × It is from.
Moreover, in the truth table of f (x, y) shown in FIG. 36 , the N-ary system and 2 logical variables can be obtained by changing the “multi-valued number N” and “each logical variable range of logical variables x It can represent all and multi-valued logic functions. For example, 67xN0, 6 ≧ y ≧ 0 in the base 7 system of N = 7. In this case, there are seven in all in the x horizontal direction in FIG. 36 and seven in all in the y vertical direction, so the total number of squares is 49, and the numerical pattern is a total of 7 to the 49th power.・ It becomes kind.
Description of the number of types of multi-valued logic functions in paragraph numbers [0030 to 0031] of JP-A-2007-035233.

By the way, the item {circle over (d)} in the paragraph {paragraph number [ 0144 ] described later. } As you can “combination of each value of input logic variable x, y can be expressed by 2-input multi-value AND circuit etc.” “combination of each value of input logic variable x, y, z is 3 inputs Can be expressed by a multi-value AND circuit or the like, and “combinations of values of the input logical variables w, x, y, z can be expressed by a four-input multi-value AND circuit or the like”, The combination of the values of the input logic variables u, w, x, y, z can be expressed by a 5-input multi-value AND circuit etc. " By increasing or decreasing the number of inputs of the circuit, it is possible to cope with the increase or decrease of the number.
However, as the number of input logical variables increases or decreases (how the writing of the truth table changes), the “total number of cells in the corresponding truth table” also increases or decreases. Corresponding to the total number of squares in the truth table, corresponding to increase / decrease.
For example, in the case of six inputs of 10-valued one-digit input logical variables u, w, x, y, z, a, replace x in the truth table of FIG. 36 with uwx and replace y with yza. . Therefore, the uwx horizontal direction is the 1,000 cells of "number 000 to 999", and the yza vertical direction is also the 1,000 squares of "number 000 to 999". Therefore, the total number of the cells is 100. The number becomes ten thousand, and the numerical pattern becomes a total of ten one-millionths and kinds = 10 ^1,000,000 kinds. Of course, at this time, each of the input logical variables u, w, x, y, z, a represents each 10-value one-digit integer, but by expressing in this way, the number of input logical variables is 6 The case of individual can be expressed in a truth table (with the total number of cells, which is quite difficult), in a vertical, horizontal, or simple manner.

Here, furthermore, the u wx can be replaced with x ₂ x ₁ x ₀ , and this x ₂ x ₁ x ₀ can also be used to represent three digits of x. At this time, it can be interpreted that the input logical variable x is expressed by 10 values of 3 digits, or can be interpreted as expressed by a 1000 value of 1 digit.
In addition, it may sound strange to say that "represented by 1000 one digit," but we already have 16 values "0, 1, 2, ..., 8, 9, A, B, C, D, E" , "F" is represented by one digit of 16 characters. “The numerical value 10 corresponds to A, the numerical value 11 to B,..., The numerical value 14 to E, and the numerical value 15 to F”. Similarly, if each numerical value of 10 to 999 is replaced with one character, it can be expressed by 1000 value one digit. On the other hand, in the case of 10 values 3 digits and _expressions, since 3 characters x ₂ x 1 _{x 0} are representing numbers independent of each _other, if you express x ₂ x 1 _{x 0} on one character, 10 values 3 digits・ The meaning of expression is lost. In addition, although the number of power supply potentials required for 1000 values is at least 1000, it is at least 10 for 10 values.
Now, the remaining yza side can also replace the yza with y ₂ y ₁ y ₀ , and the y ₂ y ₁ y ₀ can also represent the three digits of y. At this time, it can also be interpreted that the input logical variable y is represented by 10 values of 3 digits, or it can be interpreted as represented by a 1000 value of 1 digit.
And the above mentioned things are similarly ......, u, w, x, y, z, a, ...... variables “......”, “... u ₄ u ₃ u ₂ u ₁ u ₀ "... w ₄ w ₃ w ₂ w ₁ w ₀ ", "... x ₄ x ₃ x ₂ x ₁ x ₀ ", "... y ₄ y ₃ y ₂ y ₁ y ₀ ", "... z ₄ z ₃ z ₂ z ₁ z ₀ "," ... a ₄ a ₃ a ₂ a ₁ a ₀ "," ... "and so on can be expanded and expanded to any extent.
This is why, if synthesis and multi-valued logic circuit of Figure 35 is a truth table representing a "logical function f shown in FIG. 36 (x, y), N-ary-2 logical variables x, total-y-multi If we can prove that we can realize value logic functions, regardless of the number and the number of digits of the logic variables, the completeness and completeness of the multi-valued logic Hooji algebra are given. It will be proved.

The synthetic / multi-level logic circuit of FIG. 35 is one configuration example of "a circuit capable of realizing multi-level logic functions of all two logic variables", and most of the configuration means are shown by dotted lines. Although not shown, it is as follows.
However, "NOT (m) = m" is a multi-value NOT circuit of input specific integer = output specific integer = m, "AND (m) = m" is input specific integer = output specific integer = m multilevel aND circuit, the "OR (m) = m" is multivalued OR circuit specific integer = m for the specific input integer = output means respectively, specific numerical values for each specific integer m in FIG. 35 Writing m (= 0, 1, 2,..., 8, 9).
In FIG. 35 , a multi-value "OR (1) = 1" circuit to a multi-value "OR (8)" is usually between the multi-value "OR (0) = 0" circuit and the multi-value "OR (9) = 9" circuit. 8) There are 8 circuits in the circuit, and the multi-level "AND (0) = 0" circuit group (the circuit represented by "AND (0) = 0"-all) and the multi-level "AND (9) = 9) Circuit group (= circuit expressed by “AND (9) = 9” and all.) Usually, multi-level “AND (1) = 1” circuit group to multi-level “AND (8) = 8” There are eight circuit groups of circuit groups. To each multi-value "AND (...) = ..." circuit group, the necessary number of multi-value "NOT (...) = ..." circuits corresponding to the group are connected.
In addition, it is confirmed again that each operation of the multi-value “OR (m) = m” circuit, the multi-value “AND (m) = m” circuit and the multi-value “NOT (m) = m” circuit It is street.
◆ Multi-value “OR (m) = m” circuit: While a specific integer m is output when at least one of a plurality of input numerical values is a specific integer m, the output is released otherwise.
→ → Figure 55 , Figure 57 · each asynchronous · multi-valued OR circuit.
◆ Multi-value "AND (m) = m" circuit: While a plurality of input numerical values are all a specific integer m, a specific integer m is output, while the output is released otherwise.
→ → FIGS. 50 to 51 and each of FIG. 53・ Asynchronous type ・ Multi-value AND circuit ◆ Multi-value “NOT (m) = m” circuit: While one input numerical value is a specific integer m, its output is released, Otherwise, output a specific integer m.
Each-asynchronous-multilevel NOT of →→ Figure 48 to 49 {or Neven (Niven or Nebun)} circuit.

■■ Rough description of circuits and functions ■■
Although specific integer values m (= 0, 1, 2,..., 8, 9) are written in each specific integer m in FIG. 35 , the function of each circuit is as follows.
◆ multi-level "OR (m) = m" circuit group (Group spread drawings, a longitudinal direction. A total of 10 circuit.) Each integer m which is described in the truth table of f (x, y) shown in FIG. 36 = 0, 1, ..., 8 and 9 are output.
Therefore, the number of multi-level “OR (m) = m” circuits and “the number of types of integers described in the truth table of f (x, y) shown in FIG. 36 ” are the same. For this reason, if only nine types of integers are listed, there are only nine circuits corresponding to the remaining nine integers except for the unlisted integers. If there are eight types, there are only eight circuits. The same is true for the following, but for the sake of clarity, it will be described as m = 0-9.
◆ Multi-level "OR (m) = m" circuit and multi-level "AND (m) = m" belonging to the same multi-level OR-AND-NOT circuit group (drawings-group extending horizontally, 10 groups in total) Each value (= 0 to 9) of both m of the circuit is identical. Naturally, the number of groups and the total number of multi-value "OR (m) = m" circuits are the same.
◆ Each multi-value "AND (m) = m" circuit group (drawings-a group extending in the vertical direction, m = 0 to 9) is "as each relationship shown in the truth table in Fig. 36 " f (x , Y) and x, y are connected.
For this reason, the number of logic variables and the number of input terminals of each multi-level “AND (m) = m” circuit are the same.
The number of "AND (m) = m" circuits belonging to each-multi-level OR-AND-NOT circuit group, "that circuit group-specific integer in the truth table of f (x, y) shown in FIG. 36 This is the same as the total number of squares in which the value m is written.
◆ Each multi-value "NOT (m) = m" circuit group (drawing-group extending in the vertical direction; m = 0 to 9) determines each value of x and y.
The reason for this is that the m value of each multi-level “AND (m) = m” circuit may be different from “the specific integer value m to be compared originally when it is determined”. Therefore, the m value of each AND circuit and the m value of “the NOT circuit connected to it” are necessarily different.
If both m values match, the multi-level "NOT (m) = m" circuit is unnecessary, and the multi-level "AND (m) = m" circuit directly determines the value of x or y, The input terminal Tx or the input terminal Ty is directly connected to the input part of the multi-value "AND (m) = m" circuit.
That is, when the value of f (x, y) and the value of x are the same m value, the multi-value "AND (m) = m" circuit directly determines the value of x, and the value of f (x, y) If the values of y and y are the same m value, the multi-valued "AND (m) = m" circuit directly determines the value of y.
◆ Pull-up resistance or pull-down resistance connected one by one between each multi-level “AND (m) = m” circuit and each multi-level “OR (m) = m” circuit Both signals are matched in order to make each output signal the latter input signal. It should be _{noted that although} there is a relationship of v _C0 ≠ v ₀ , v _C1 ≠ v ₁ , v _C2 ≠ v ₂ , ..., v _C9 ≠ v ₉ with respect to each power supply potential, each power supply line of power supply potentials v _{0 to} v ₉ the expressed as _V 0 ~V _9, it represents the respective power line of the power supply potential _v C0 _{to v C9} in _V C0 _{~V C9.}
◆ Pull-up resistance or pull-down resistance connected one by one between each multi-level “NOT (m) = m” circuit and each multi-level “AND (m) = m” circuit Both signals are matched in order to make each output signal the latter input signal.

The functions of the details are as follows. ■■
◆ 1) In the multi-level OR-the AND-NOT circuit group configured to identify an integer m = 0 multilevel OR circuit, multi-level "OR (0) = 0" input of the circuit shown in FIG. 36 f (x, In the truth table of y), all cases are satisfied if f (x, y) = 0 is satisfied. Therefore, "the total number of cells in which m = 0 is written" = the total number of input terminals of the multi-level "OR (0) = 0" circuit (= the total number of multi-level "AND (0) = 0" circuits) .
Although both m values of “OR (m) = m” and “AND (m) = m” belonging to the same multi-value OR-AND-NOT circuit group are the same, each “NOT (m It is always different from the m value of) = m ".
Also, if there are only two cells in which “m = 0 is written” in the truth table, the number of input terminals of the multi-valued “OR (0) = 0” circuit is also two. If there are a total of 70 "cells with m = 0 written", then the number of input terminals is 70.
◆ 2) Each multi-value "AND (0) = 0" circuit set to specific integer m = 0 "each combination of values of logical variables x and y satisfying f (x, y) = 0" I will cover. That is, each multi-value "AND (0) = 0" circuit corresponds one-to-one with "a combination of x value and y value of the grid to which m = 0 is written".
In the truth table of FIG. 36 , each combination of (5, 0) and (8, 3) is illustrated, and f (5, 0) = 0 and f (8, 3) = 0.
In this way, each multi-value "AND (m) = m" circuit covers (or does not) each "combination of the values of the logic variables x and y satisfying f (x, y) = m".
◆ 3) Each "NOT (m) = m" circuit connected to the input terminal Tx determines the logical variable x = m (= 0, 1, 2, ..., 8, 9) and connects to the input terminal Ty Each "NOT (m) = m" circuit determines the logic variable y = m (= 0, 1, 2,..., 8, 9).
However, if the value of the logic variable x to be determined is the same as the m value of the multi-level “AND (m) = m” circuit, the multi-level “AND (m) =” is not used without the “NOT (m) = m” circuit. m "directly determine whether the circuit is the logic variable x = m.
For example, if the value of the logical variable x satisfying f (x, y) = 0 is 0 (ie, when f value = x value), the “NOT (0) = 0” circuit is not necessary. The potential signal is input as it is to the multi-value "AND (0) = 0" circuit.
Then, if the value of the logical variable y satisfying f (x, y) = 0 is 0 (that is, if f value = y value), the “NOT (0) = 0” circuit is not necessary. for potential signal to be input directly to the multi-level "aND (0) = 0" circuit, both of which are directly connected with the conductor as in Figure 35.
When f (5, 0) = 0, the input terminal Ty is directly connected to the second input terminal of the lowermost multi-valued "AND (0) = 0" circuit.
Similarly, when f (7, 9) = 9, the input terminal Ty is directly connected to the second input terminal of the lowermost multi-valued "AND (9) = 9" circuit.
◆ 4) Pull “up” or “up” connected one by one between the multi-level “OR (0) = 0” circuit and each multi-level “AND (0) = 0” circuit set to specific integer m = 0 A "down" resistor matches the input and output signals. Therefore, the potential v _C0 ≠ v ₀ .
◆ 5) Each combination of “multi-level“ NOT (...) = ... ”circuit and pull and“ up or down ”resistance” in the same circuit group is each multi-level “AND” with each potential signal of input terminals Tx and Ty (0) = 0 "Match the input of the circuit.
◆ 6) In the same way, each of the multi-value circuit groups (= each value of multi-value OR, AND and NOT circuit groups) set to “specific integer m = 1 to 9” has the same function. Play.

The above is the case of the decimal system, but in the case of the N system, the value of the grid is 0 as described above, and the above-mentioned "specific integer m = 1 to 9" respectively is “Similarly, it changes to“ specific integer m = 1 to (N−1) ”respectively” and the like.
***
As described above, the synthetic / multi-level logic circuit of FIG. 35 can realize / implement "all multi-level logic functions represented by the truth table of f (x, y) shown in FIG. 36 ". The completeness of the multi-valued logic "Fuji algebra" is proved. Moreover, since all of the multi-valued logic functions can be realized and embodied by only one kind of basic / multi-valued logic circuit as described above (paragraph numbers 0135 to 0136 ) without using the “logic constant input circuit”・ The "completeness" of the multi-valued logic "Fuji algebra" is proved.
★ ★ "Complete" of "Fuji Algebra" by only one type of basic / multi-level logic circuit ★ ★
“Introduction to logic circuits”, p. 31 (8) Complete System. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd., September 28, 2001. “A well understood digital electronic circuit”, p. Line 14 of 9 ~ p. "Complete system" of the first line of ten. Author: Sekine Keitaro, Inc. Ohm company published on July 25, 1997. "Multi-value information processing-post binary electronics-", p. 16 to p. 17 contents of "completeness, complete system, complete". Author: Takao Higuchi, Michitaka Kameyama (Michitaka), Shokodo (Shokodo) published in June 1989.

■■ Configuration of the multilevel logic circuit shown in Fig. 35 · Individual description ■■
Just in case here it will be specifically described with reference to "truth table of simplified the f (x, y)" shown in FIG. 36 structure and individually for the synthesis and multivalued logic circuit shown in FIG. 35. However, the issues of maximum fan-in, maximum fan-out, current capacity, and multilevel hazards are ignored.
◆ b) Each specific integer value of f (x, y) = 0 to 9 is usually described in each 升 in the truth table of f (x, y) shown in Fig. 36 However, each multi-valued “OR (m) = m” circuit is prepared in which each specific integer value described therein is a specific integer m.
If there is a specific integer not described there, the multilevel "OR (m) = m" circuit of the specific integer not described, each multivalue "AND (m) = m" The circuits and each multi-level "NOT (...) =..." Circuit connected to the front stage of "this each multi-level" AND (m) = m "circuit can be omitted because it is unnecessary.
◆ b) In the truth table of f (x, y) shown in FIG. 36 , when viewing an integer value of one certain cell, for example, f (x, y) = 0 set to integer m = 0, in all Since there are two (there may be more cases in practice because the illustration is simplified), the multi-level “OR (0) is set to the specific integer m = 0 in the multi-level“ OR (m) = m ”circuit. ) Set the number of input terminals of the circuit to two of the same number.
Iii) The same number as the number of input terminals of the multi-level "OR (0) = 0" circuit set to the specific integer m = 0, set to the specific integer m = 0 in the multi-level "AND (m) = m" circuit Prepare a multilevel "AND (0) = 0" circuit. Then, the multi-value "AND (0) = 0" circuit is connected one by one to the previous stage of the multi-value "OR (0) = 0" circuit.
◆ d) At this time, the number of input terminals of each multi-level "AND (m) = m" circuit is 2 the same as the number 2 of the logic variables x and y, but there are 3 logic variables x, y and z Then, the number of input terminals is three, and if there are four logic variables w, x, y, z, the number of input terminals is four, and five logical variables u, w, x, y, z If there are one, the number of input terminals is five. After that, it is only necessary to connect one multi-valued "NOT (m) = m" circuit to each input terminal.
As described in the item d), the number of input terminals of each multi-value "AND (m) = m" circuit is two.

◆ E) Each potential of the multi-valued “AND (0) = 0” circuit set to the specific integer m = 0 is the potential v ₀ (in this case, m = 0 because v _m = v ₀ ) other than the potential v _C0 ( At this time, since m = 0, pull up or pull down to v _Cm = v _C0 . v _C0 ≠ v ₀ (v _Cm ≠ v _m ).
Note that the potential v _Cm is “potential corresponding to an integer other than the specific integer m” or “independent additional potential not corresponding to any integer,” the multi-value “OR (m) = m” circuit is a specific integer m Any potential is acceptable as long as the potential can not be determined.
◆ f) f (x set to an integer m = 0 in FIG. 36, y) = 0 a satisfactory logical variables x, each combination of values of y (5, 0), confirms (8,3).
In general, each combination of values of the logic variables x and y satisfying f (x, y) = m is confirmed.
G) For the first set (5, 0), between the input terminal Tx and the first input terminal of the first multi-level "AND (0) = 0" circuit (specific integer m of AND = 0) certain integer m = 5 multilevel "NOT (5) = 5" to (= logical variable value _{m x} of x) to connect the circuit, the multi-value "NOT (5) = 5" potential output terminal of the circuit to Pull "up or down" to v0 (v _m = v _{0 because} the specific integer m of AND is ₀ ).
On the other hand, between the input terminal Ty and the second input terminal of the first multi-level "AND (0) = 0" circuit (in this case m = 0), the logic variable y has the value m _y = 0 and the AND Since the value is 0, which is the same as the specific value m of the circuit, the input terminal Ty is directly coupled directly to the second input terminal of the first multi-value "AND (0) = 0" circuit.
Of course, if the value m _y変 数 0 of the logic variable y, as in the case of the input terminal Tx, a multi-value “where the integer“ ... ”different from 0 is a specific integer between the input terminal Ty and its second input terminal NOT (...) = ... "connect the circuit etc.
Also, if there is a case of the value m _x = 0 of the logic variable x, the input terminal Tx is directly subjected to the first multi-value “AND (0) = 0” as in the case of the value m _y = 0 of the above logic variable y. Directly to the first input terminal of the circuit.

◆ For the second set (8, 3), specify between the input terminal Tx and the first input terminal of the second multi-level "AND (0) = 0" circuit (in this case m = 0) integer m = 8 (= logical variable values of x _{m x)} to connect the multi-value "NOT (8) = 8" circuits, the multi-value "NOT (8) = 8" output terminal potential of the circuit _{v 0} (At this time, m = 0, so v _m = v _0. ) Pull "up or down".
On the other hand, a specific integer m = 3 (= value m _{y of} logical variable _y ) between the input terminal Ty and the second input terminal of the second multilevel “AND (0) = 0” circuit (in this case m = 0) The multi-level "NOT (3) = 3" circuit is connected, and the output terminal of the multi-level "NOT (3) = 3" circuit is connected to the potential v ₀ (in this case, m = 0 because v _m = v ₀ ) Pull up or down.
Of course, if there is a case where the value m _x = 0 of the logic variable x or the value m _y = 0 of the logic variable y, the connection work of the direct connection is performed in the same manner as the connection work in the above item ( _g ).
◆) In the truth table of f (x, y) shown in FIG. 36, there are other combinations of the values m _x and m _y of logical variables x and y satisfying f (x, y) = 0. Then, the connection work of the above item (v) or (v) is repeated by the number of combinations.
◆ j) Similarly, f (x shown in FIG. 36, ★ "f (x, y) = 1 to 9" in the truth table, the y) for integers even the integer values for each the integer Instead of m = 0, it sets to each specific integer m = 1-9, and repeats the connection work of "the above-mentioned ◆ b)-the above-mentioned b) item".
◆ The above is the case of the decimal system, but in the case of the N system, only the above “f (x, y) = 1 to 9” is “f (x, y) = 1 to (N − 1) only.
Connection work and completion by the above.

Then, in the combined / multi-level logic circuit of FIG. 35 , each multi-level “OR (m) = m” circuit and each multi-level “AND (m) = m” circuit are simultaneously multi-level “NAND (m) = A multi-valued equivalent circuit is possible in which one circuit is replaced by one circuit of “m” circuit. Of course, each integer value of m is set to the integer value shown in FIG. 35, set to the number of the - input terminal shown in Figure 35 is also the number of the - input terminal.
Reason to be equivalent circuit replaces one in the equivalent circuit of the multi-valued "OR (m) = m" circuit of Figure 33 each-multi-level "OR (m) = m" circuit in FIG. 35, the Each series circuit of "multi-level" AND (m) = m "circuit and multi-level" NOT (m) = m "circuit connected to the subsequent stage after replacement" is multi-level "NAND (m) = m" This is because if one circuit is replaced one by one, the above-mentioned multiple value equivalent circuit is obtained.
Furthermore, as described above (paragraph numbers [ 0135 to 0136 ]), each multi-valued "NOT (m) = m" circuit in FIG. 35 is "combined with all its input terminals and put together into one input terminal. When replacing one by one with the multilevel “NAND (m) = m” circuit etc., the above multilevel equivalent circuit, that is, the combined / multilevel logic circuit of FIG. 35 can be realized by only the multilevel “NAND (m) = m” circuit. It can be seen that it can be configured. At that time, the "logic constant input circuit" is not necessary.
In addition, as described above (in paragraph number [ 0137 ]), it is possible to express all-multivalued logic function of N base 2 logical variables by changing each logic variable range of logic variables x and y, and {paragraph number [0138] and [0144] of ◆ to be able to change the number of street logic variables binomial)}, or it can be changed each logical variable x, each digit of y like 3 digits.
That's why, in the new multi-valued logic "Hooji algebra," unique effects and features such as "completeness by one type of multi-valued logic which is not influenced by the multi-valued number N at all, it is perfect" There is.
◆ ↑ Only one type of basic / multilevel logic circuit is not affected by the multilevel number N at all ↑ ◆
◆ 完全 完全 ◆ ◆ 完全 新 完全 新 新 ◆ 新 新 新 新 新 新 新
“Introduction to logic circuits”, p. 31 (8) Complete System. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd., September 28, 2001. “A well understood digital electronic circuit”, p. Line 14 of 9 ~ p. "Complete system" of the first line of ten. Author: Sekine Keitaro, Inc. Ohm company published on July 25, 1997. "Multi-value information processing-post binary electronics-", p. 16 to p. 17 contents of "completeness, complete system, complete". Author: Takao Higuchi, Michitaka Kameyama (Michitaka), Shokodo (Shokodo) published in June 1989.

◆ ◆ ◆ ***** The multivalued wired OR circuit in "Fuji Algebra" ***** ◆ ◆ ◆
***
●● 16) Describe the fact that the multi-value wired OR circuit holds in a multi-value logic circuit based on the new multi-value logic "Hooji algebra".
First, it is shown in Figure 37 a multi-level wired OR circuit introduced synthetic-multivalued logic circuit (= completely circuits) in synthesis and multi-valued logic circuit of FIG. 35 (= complete circuit). As a matter of course, the latter circuit configuration is considerably simpler than the former circuit configuration, and the number of parts is correspondingly reduced.
It should be noted that in the combined / multi-level logic circuit of FIG. 37 , the pull-up or pull-down resistor is not connected to the output terminal Tf because the output switch portion of one of the AND circuits is always on, Because the potential of the terminal Tf is pulled up or down, the pull up resistance and the pull down resistance can be omitted.
→ → Save power consumed by each pull resistor.
Also, if there is at least one cell in which no numerical value is entered in the truth table in FIG. 36 , the output terminal Tf is opened at the time of the x value and y value of the cell, so pull-up resistance or It is necessary to connect one end of the pull-down resistor to the output terminal Tf and connect the other end to a predetermined power supply line V _Cm .
The fact that the composite / multivalued logic circuit of FIG. 37 satisfies the truth value table of FIG. 36 similarly to the composite / multivalued logic circuit of FIG. 35 is specifically the x value, y value, f (x, it is that immediately turn out if Atehamere each-integer values of y) values on synthesis and multi-valued logic circuit of Figure 37. But, given simply, whereas "the AND circuit synthesis and multivalued logic circuit of FIG. 35 and outputs the output number to the output terminal Tf via a respective OR circuit", the synthesis of "Figure 37 - Each AND circuit of the multi-level logic circuit directly outputs its output numerical value to the output terminal Tf.

Then, in addition to the problem of the circuit configuration and the number of parts, the synthetic / multivalued logic circuit in FIG. 35 has a “problem to be solved” of “very inconvenient and not practical” The synthetic / multilevel logic circuit of FIG. 37 using the circuit can solve the problem.
◆ Example 1: In the truth table of FIG. 36 , there are a total of 80 square cells whose integer values are, for example, 6 and 2 or 3 squares of integer values 0 to 5 and 7 to 9 other than 6 respectively A total of 80 input terminals of the multi-valued "OR (6) = 6" circuit are required. Others are two or three each.
◆ Example 2: When the number of squares which are integers of m = 0 to 9 in the truth table of FIG. 36 is uniformly approximately 10 each, each multi-valued “OR (m) = m” circuit The total number of input terminals is also approximately 10 in a uniform manner.
***
In short, the numerical pattern of the truth table of FIG. 36, i.e., depending on whether the squares of the same integer values there by a number, total-number of input terminals of each-multi-level "OR (m) = m" circuit fluctuates Furthermore, if the integer value m to be written is deviated, the total number of input terminals of the specific multi-value “OR (m) = m” circuit is particularly increased.
As a result, it is extremely inconvenient and not practical when the multilevel logic function shown in the truth table of FIG. 36 is embodied and realized as a combination / multilevel logic circuit.
Meanwhile, due to the use of multi-level wired OR circuit in synthesis and multi-valued logic circuit of FIG. 37, each-multi-level varying number its input terminal by a numerical pattern of the truth table of "Figure 36" OR (m) Since there is no "m" circuit itself ", the synthetic / multilevel logic circuit of FIG. 37 can solve the" problem to be solved "described above. In addition, as described above, the combined / multi-level logic circuit of FIG. 37 is simpler than the combined / multi-level logic circuit of FIG. 35 , and the number of parts is reduced. It is convenient.
These things, the relationship of "synthesis and multi-valued logic circuit of Figure 38 a truth table of (multi-level number N = 3) and 39" to be described later, and its development and derivation circuit (multi-level number N = 4 , 5, 6 ... 10).

◆ ◆ ◆ ◆ ***** (3D) IC · LSI implementation of "perfect" circuit ***** ◆ ◆ ◆
***
●● 17) Explain that (three-dimensional) programmable logic array of “perfect” circuit, semi-order (three-dimensional) IC, LSI can be realized.
Synthesis and multivalued logic circuit of Figure 38 in synthesis and multi-valued logic circuit of "Figure 35, to change both logical variable x, the number of levels y from 3 to 10, 3 pieces of multivalued" OR (m) The circuit configuration is simplified and standardized by using a multi-level wired OR circuit instead of the “m” circuit (m = 0, 1, 2).
Note that since any one of the plurality of AND circuits is always on, connections such as pull-up resistors or pull-down resistors can be omitted. That is, there is no need to connect them. → → Save power consumption.
This makes it easy to realize (three-dimensional) programmable logic array and semi-order (three-dimensional) IC / LSI, etc., which is convenient.
◆ ◆ Utility that multi-level wired OR circuit holds ◆ ◆
Then, FIG. 39, the function f (x, y) in FIG. 38 = In the truth table, diagram _{m z,} are as follows rewritten.
◆ x = 0, 1, 2
◆ y = 0, 1 and 2
_{◆ f (x, y) =} m z, (m z = m0, m1, ......, m7, m8)
f (0, 0) = m0, f (0, 1) = m1, f (0, 2) = m2
f (1, 0) = m3, f (1, 1) = m4, f (1, 2) = m5
f (2, 0) = m6, f (2, 1) = m7, f (2, 2) = m8
However, 2 m m0, m1, m2, m3, m4, m5, m6, m7, m8 0 0

Since each integer value of m0 to m8 is either 0, 1 or 2, m0 has 3 values, m1 has 3 values, ..., m8 has 3 values, so in the end, "Type of multi-valued logic function f (x, y) that can be expressed in all of them" = (3 ways) x (3 ways) x (3 ways) x (3 ways) x (3 ways) x (3 ways) x (3 ways) x (3 ways) x (3 ways) = 3 to the 9th power · 19 = 683 types.
Then, in FIG. 38 , one “simple conductor” is drawn next to each multi-level “NOT (m) = m” circuit, and each multi-level “AND (m _z ) =” with each of the input terminals Tx and Ty. Indicated by “each connection terminal and each dotted line” that there are cases where the “m _z ” circuit and the input part are connected via each multi-value “NOT (m) = m” circuit and that there is a direct connection. It is done.
In FIG. 39 , when the value m _x (one of 0, 1 and 2) of the logic variable x and the value m _{z of the} multi-value logic function f (x, y) are the same (m _x = m _z ), The input terminal Tx is directly connected to “a multi-valued“ AND (m _z ) = m _z ”circuit first input terminal” where m _z is a specific integer. ”
On the other hand, when the value _{m z} of logical variables x values _{m x} and the multi-level logic function f (x, y) is different from _{(m x} ≠ _{m z),} the multi-level "NOT (m as the input terminal Tx 38 It is connected to “a multi-valued“ AND (m _z ) = m _z ”circuit first input terminal” in which m _z is a specific integer via a circuit _x ) = m _x ”.
Similarly, the connection between the input terminal Ty and the second input terminal of each multi-level “AND (m _z ) = m _z ” circuit is also connected via the multi-level “NOT (m _y ) = m _y ” circuit. Or directly connected. However, _{m y} is the value of a logical variable y, of 0,1,2 is any one.

When the integers m0 to m8 are sequentially set to the integers 0 to 8, respectively, the combined / multilevel logic circuit of FIG. 38 becomes a three-value / nine-value code conversion circuit. Of course, y is the first digit of its ternary representation and x is the second digit of its ternary representation. In this case, the specific potential supply means of the “AND (0) = 0” circuit is, for example, the power supply line V ₀ , and the specific potential supply means of the “AND (1) = 1” circuit is, for example, the power supply line V ₁ . ... specific potential supplying means "AND (9) = 9" circuit is a power supply line _{V 9,} for example.
In addition, it is possible to freely set the multivalued number of each of the logical variables x and y and the three multivalued logical functions f (x, y). All or multi-value numbers may be set to be the same, or each or multi-value number may be set to different values.
Furthermore, when the three multivalued numbers N are the same and four, "the kind of multivalued logic function f (x, y) that can be expressed" is also fourteen sixteenth kinds of kinds 4 4, 294, 968,000 kinds . Moreover, "multi-value [AND (...) = ...] In the synthesis, the multi-level logic of the duster large variety of multi-valued logic function" Figure 38 circuit, two multi-value [NOT (...) = ...] circuit And the combination of two wires can be realized by increasing the number of combinations of 9 and 16 from one set to nine and increasing the power supply and power supply lines one by one with an increase in the number of levels.
Similarly, when the same multilevel number is 5, "the type of multilevel logic function f (x, y) that can be expressed" is the 5th power of 5 · type 2.9 2.980233 × (10 to the 17th power) type, In the combined / multilevel logic circuit of FIG. 38 , it is only necessary to further increase the number of combinations from 16 to 25.
Similarly, the "type of multivalued logic function f (x, y) can be expressed" when the same multi-level number is 10 is 100 square-type 10, the Combination In the synthetic-multivalued logic circuit of FIG. 38 It is sufficient to further increase the number of 25 pairs from 100 to 100.
So, in proportion to the small number of parts, "the kind of multi-level logic function f (x, y) that can be expressed" will increase extremely and explosively with the increase of the same multi-level number N.
★ Reference: Paragraph No. [0031-0033] of JP-A-2007-035233.
Moreover, as will be described later (paragraph number 0154 ), each multi-value number of the logic variable x, the logic variable y, and the multi-value logic function f (x, y) may be different. It does not have to be identical. → Correspondence flexibility.
Such ultra-explosion and its corresponding flexibility, FIG. 37, the synthesis and multi-valued logic circuit programmable three-dimensional logic array and in Figure 38, semi-order three-dimensional IC, LSI When it is put to practical use, etc., it becomes an extremely powerful weapon and effect.

For example, there are the following as specific multilevel logic circuits.
Example 1: FIG. 48 and FIG. 49 show two examples of asynchronous and multi-value “NOT (m) = m” circuits, and FIGS. 50 to 51 and 53 show asynchronous and multi-value “AND (m) = m "indicates the three examples of the circuit, FIG. 55 shows two examples of asynchronous-multilevel" OR (m) = m "circuit in Figure 57.
The diode 225 in asynchronous-multivalued NOT circuit of Figure 49 is a "transistor 201 is turned off, the resistance transistors 202,228 from the power supply line _{V m} when on 223, through transistor 228, resistor 220 and transistor 202 Power "For preventing current from flowing to the line _Vm-1 ." When the series circuit of the transistors 201 and 228 can not drive the transistor 224 off due to the forward voltage of the diode 225, the diode 226 and the resistor 227 are required. However, if the transistor 228 is off when the transistor 201 is off and the transistor 202 is on, there is no need to insert the diodes 225 and 226 and no resistor 227 is needed.
Reference: Each circuit of FIG. 10 and FIG. 9 of patent document 3 (Unexamined-Japanese-Patent No. 2005-236985).
The asynchronous type / multilevel NOT circuit of FIG. 48 removes the D-type flip flop 127 etc. in the twelfth embodiment common to the prior art / first and second inventions (= synchronous type / multilevel NOT circuit) shown in FIG. 70 . , Etc. and changed to an asynchronous type / multilevel NOT circuit.
Example 2: Nine "Same type AND circuits according to the fourteenth embodiment common to the first and second inventions shown in FIG. 75 " and 18 "first and second prior applications shown in FIG. 59 " invention common synchronous NOT circuit of the first embodiment "or" prior application, first shown in FIG. 69, synchronous NOT circuit "in FIG. 37 of the second invention common of example 17, the synthesis and the multi-level shown in FIG. 38 It is possible to change the logic circuit to synchronous type, and to perform synchronous combination / multilevel logic circuit in which both the latching timing of the all-synchronous NOT circuit and the all-synchronous AND circuit are shifted.
As a matter of course, this synchronous combining / multilevel logic circuit can remove multilevel hazards. Moreover, if the gate terminal of the transistor 41 is changed from the Q terminal to the Q bar terminal in the first embodiment common to the prior art / first and second inventions shown in FIG. 59 , the first embodiment is a synchronous NOT circuit to a synchronous type. Since it changes to an EVEN circuit (= synchronous EQUAL circuit), the conductors shown next to each NOT circuit in each of FIGS. 37 and 38 are not necessary.
Also in this case, “increase of all multi-level number N” can be performed as described above (paragraph number [ 0152 ]), and “change to each different multi-level number N” can be performed as in the next term .

◆ ◆ ◆ ***** Flexible for logical variables etc. with different multi-values
***
●● 18) New and multi-valued logic “Hooji algebra” “Flexible correspondence that can cope with multiple logical variables and their respective logical functions N (関 数 2) even if they are different” These features will be described below.
★ See: For multi-value N = 2 → Paragraph numbers [ 0131 to 0132 ].
Some multilevel logic circuit systems may handle complex information or the like in which a plurality of "data or information" having different multilevel numbers N (≧ 2) are mixed. For example, the three primary colors of light (blue-red-green) multi-value number "3", the positive and negative multi-value numbers "2", and also "multi-level of brightness" multi-value number "blue-red-green" It is a multi-value number such as "blending ratio".
In such a case, multi-valued logic circuits having different multi-valued numbers N () 2) are mixed and formed, but “the multi-valued logic of the larger number of multi-valued numbers” It is better for the former to have compatibility with the latter completely including the smaller multilevel logic.
In the case of the new multi-valued logic "Hooji algebra", the former is built on the basis of the latter (multi-valued number N 通 り 2) as described above (paragraph number [ 0133 ]. While the former includes the latter, it is compatible with the latter.
In the synthetic / multi-level logic circuit of FIG. 35 described above, the multi-level number N2 (≧ 2) of the logic variable x is always for the multi-level number N1 (≧ 2) of the multi-level AND circuit and the multi-level OR circuit. It is not necessary to be the same, and the multi-value number N3 (≧ 2) of the logic variable y does not have to be always the same. There may be cases where N1 ≠ N2 or N1 ≠ N3. Furthermore, N2 and N3 need not always be the same. There may be cases where N1 ≠ N2 or N1 ≠ N3 or N2 ≠ N3.
◆ Example 1: A ternary / nine-valued code conversion circuit in paragraph number [ 0152 ].
◆ Example 2: When the variable range only logical variable x, for example 0-7 in the truth table of Figure 36, which is connected to the input terminal Tx in FIG. 35 multilevel "NOT (m) = m" circuit Among them, the multi-value “m” is the multi-value “NOT (8) = 8” circuit where m is 8 or 9, and the multi-value “NOT (9) = 9” circuit is removed. By removing the AND (m) = m circuit, it is possible to cope with the change of the multi-level number.
In this case, if there is a multi-value AND circuit whose input is directly connected to the input terminal Tx among each multi-value "AND (8) = 8" circuit and each multi-value "AND (9) = 9" circuit. Because the multi-value AND circuit and the "multi-value NOT circuit connected to it" are unnecessary, they can be removed.
Of course, the same applies to the logic variable y.
As a result, “[Multiple logical variables and their functions] flexible correspondence that can be coped with each other even if their multi-valued numbers N (≧ 2) are different” is the new multi-valued logic “Hooji algebra” There is.
On the other hand, in the case of the multi-valued logic circuit constituted of the conventional "AND circuit, OR circuit, inverting circuit, literal circuit and cycling circuit" described above (paragraph number [ 0131 ] second half and paragraph number [ 0133 ] second half). Inclusion does not hold in "inverted circuits, literal circuits and cycling circuits" different in multi-value number, and there is no compatibility at all, so there is no flexible correspondence like new and multi-valued logic "Fuji algebra".
★ Reference: p. 19 to p. 20.
"Multi-value information processing-post-binary electronics-" Authors: Tatsuo Higuchi, Michitaka Kameyama (Michitaka), Shokodo (Shikokodo) published in June 1989. "Mathematical science February issue (1980, No. 200) Feature: Multivalued Logic", published by Science Co., Ltd. on February 1, 1959.

◆ ◆ ◆ ◆ ***** ***** Good connectivity with pre-stage binary circuits ********* ◆ ◆ ◆
***
●● 19) When connecting a binary circuit to the front stage of the new multi-valued logic "Hooji algebra", its connectivity is extremely good, and a special interface between them (eg: binary / multi-valued code conversion) The following is an explanation of the unique effects / features of the means) not required.
In the case of each multi-valued logic circuit based on the new multi-valued logic "Fuji Algebra", the decision means fundamentally decides that "the signal indicating whether each decision content is positive or negative, affirmed A negative signal (a two-or-one signal), that is, a signal indicating whether each or the determination content is Yes or No, a yes / no signal (a two-or-one signal), a binary signal, etc. The compatibility with the output signal of the previous stage binary circuit is very good.
Therefore, as described below, the output of the former binary circuit and the input of the multilevel logic circuit are simply matched.
◆ a) When the preceding binary circuit outputs two levels, H level and L level:
The output level range of one of H level and L level of the binary circuit is completely inserted (Yes) within the input discrimination range in which the multilevel logic circuit discriminates "Yes", and the multilevel logic circuit The other output level range may be matched (matched) so that the other output level range completely falls within the input determination range determined as “.”
B) When the output part of the former binary circuit is open collector or open drain:
33 to 35, FIG. 37, the pull-up resistor means or a pull-down the output terminal thereof multivalued logic circuit as each-multi-level "NOT (...) = ..." circuits in the circuits of FIG. 38 Resistance means may be connected, and matching (matching) may be performed within the H level and L level output level ranges output from the binary circuit in the same manner as the above item a).
Note that in both cases ◆ a) and ◆ b), both power levels to which both H and L levels correspond are “any two power potentials among the lowest potential and the highest potential of the multilevel circuit” anything is fine. For example, in decimal system, both power supply potentials are “v ₀ and v ₁ ”, “v ₄ and v ₅ ”, “v ₈ and v ₉ ”, “v ₅ and v ₇ ”, “v ₃ and v _8” “V ₀ and v ₉ ”, “potentials less than v ₀ and greater than v ₉ (both potentials do not correspond to numerical values)” and the like.
That is why new and multi-valued logic "Fuji Algebra" has unique effects and features that "when connecting a binary circuit to the previous stage, its connectivity is extremely good and no special interface is necessary in between". I understand.

◆ ◆ ◆ ◆ ***** ***** Good connectivity with the post-stage binary circuit ********* ◆ ◆ ◆
***
●● 20) When connecting a binary circuit to the post-stage of the new multi-valued logic “Hooji algebra”, its connectivity is extremely good, and a special interface between them (eg: multi-valued / binary code conversion) The following is an explanation of the unique effects / features of the means) not required.
There are the following two actual examples.
◆ Example 1: Japanese Patent Application Laid-Open No. 2006-190239 ・ “Each AND multi-valued circuit” and “each subsequent binary circuit” in the circuit of FIG.
Example 2: "Each multi-value NOT circuit shown in FIG. 11" in the circuit shown in Japanese Patent Application Laid-Open No. 2007-035233 and Figs.
***
On the other hand, in the case of the conventional Ukashevitch type multilevel logic circuit well-known in the multilevel logic field, the connectivity with the binary circuit is bad at the former stage and the latter stage, and the special interface (binary and Value code conversion means and multi-value / binary code conversion means are required.
★ Reference: p. 13 Figure 1.2.
"Multi-value information processing-post-binary electronics-" Authors: Tatsuo Higuchi, Michitaka Kameyama (Michitaka), Shokodo (Shikokodo) published in June 1989.

◆ ◆ ◆ ** Possibilities of using one-way switch in each circuit in Figure 35 , Figure 37 and Figure 38 * ◆ ◆ ◆
***
● ● 21) In conclusion, the use of a unidirectional output switch is possible. In each of the combined / multi-valued logic circuits (= multi-valued logic complete circuits) in FIGS. 35 , 37 , and 38 described above (paragraph numbers [★ 0184 to 0199]), the bi-directional switching in the output switch portion is mainly performed. A "multi-level logic complete circuit" has been described which can realize all multi-level logic functions using various basic and multi-level logic circuits using means.
However, in each of the synthesized and multivalued logic circuits of FIGS. 35 , 37 and 38 , the outputs of “the basic and multivalued logic circuits each having a pull-up resistor or a pull-down resistor connected to the output portion thereof” The switch part need not be bi-directional switching means. Each of the basic and multi-level logic circuits whose pull-up resistors are connected to its output section is of the reverse blocking type or reverse blocking type (for example, reverse conducting type, reverse conducting type, etc.) The basic / multilevel logic circuit which is the pull-down switching means of “.)” May be separately used. The reverse conductivity type includes, for example, a MOS.FET having a built-in diode, and the reverse conductivity type includes, for example, a bipolar transistor or the like.
On the other hand, each of the "basic and multi-valued logic circuits whose pull-down resistors are connected to its output section" is a pull-up switching means whose "output switch section is reverse blocking type or" type without reverse blocking capability ". Even a basic and multilevel logic circuit may be used separately. Of course, “a basic / multi-level logic circuit may be connected to either the pull-up resistor or the pull-down resistor at its output part” according to the pull direction of its resistance. It is to use a basic / multilevel logic circuit which is a "pull-up switching means or a pull-down switching means" of the type having no mold or reverse blocking ability.
In these cases, in the combined / multi-level logic circuit of FIG. 35 , "[multi-level NOT circuit and multi-level AND circuit using one-way pull output switch]" and "multi-level OR circuit using bi-directional output switch" At least three of the circuits form a complete system, and in each of the synthesized / multivalued logic circuits in FIG. 37 and FIG. 38 , “multivalued NOT circuit using one-way pull output switch”, “multiple using bi-directional output switch” At least three circuits of the "value AND circuit" and the multi-value wired OR circuit form a complete system.

In addition, for each-multi-level AND circuit in synthesis and multi-valued logic circuit of each-multi-level OR circuit and Figure 37 in the synthesis and multi-valued logic circuit of FIG. 35, the pull output of the output terminal Tf of each circuit is If there is no need to be bi-directional and it is sufficient for the pull output to be either pull-up or pull-down, all its basic and multi-valued logic circuits The basic circuit or multi-level logic circuit which is an up switching means or a pull down switching means may be used separately. In this case, the synthesis and multi-valued logic circuit of FIG. 35, the if the total-multilevel OR circuit uses a reverse blocking type pull-up switching unit to its output switch section, and the output terminal Tf is for example 35 low power supply potential {example than the power supply potential v ₀ of synthesis and multivalued logic circuits: a power supply potential v ₀ than one potential lower supply potential v _-1. Output signal based on} is output. On the other hand, if the the whole-multilevel OR circuit uses a reverse blocking type pull-down switching means to the output switch unit, the power supply potential of the synthesis and multivalued logic circuit of the output terminals Tf, for example FIG. 35 v ₉ higher supply potential {e.g. power supply potential _{v 9} than the potential one high power supply potential _{v 10.} Output signal based on} is output. The same applies to each multi-level AND circuit in each of the combined multi-level logic circuits of FIGS. 37 and 38 .
In these cases, in the combined / multi-level logic circuit of FIG. 35 , at least three circuits of “multi-level NOT circuit, multi-level AND circuit and multi-level OR circuit using one-way pull output switch” form a complete system. In each of the synthesized / multivalued logic circuits of FIGS. 37 and 38 , at least three circuits of “multivalued NOT circuit and multivalued AND circuit using one-way pull output switch” and multivalued wired OR circuits are complete systems. I will.

Then, the basics using “pull-up switching means or pull-down switching means” of “type without reverse blocking ability (eg reverse conducting type, reverse conducting type, etc.)” in the output switch section regard multivalued logic circuit can be used in the final stage of the circuit of Figure 37 when a twist. For example, in the circuit of FIG. 37 , the output terminal / all of them are once connected every (multiple) AND circuit of “multi-value AND circuit whose output specific integer is the same value”, and that connection / common terminal / every (every) A diode may be connected between the common terminal and the output terminal Tf. In this way, it is possible to prevent a power supply short circuit between multi-value AND circuits and between each other.
Also in this case, the output switch section of the all / multi-level AND circuit performs either pull-up or pull-down during on-drive, and there is no mix of pull-up and pull-down operations. output signal to be output in the circuit of Figure 37, "high supply potential than the power supply potential v _{9 {eg.} power supply potential v ₉ than the potential one high supply potential v _10}" or "low power supply potential than the power supply potential v ₀ { Example: A power supply potential v _{−1 which is} lower by one than the power supply potential v ₀ }} ”is used as a reference.
Therefore, a diode connection is made to the multi-level AND circuit group whose output specific integer value is either 0 (when the reference power supply potential is v ₁₀ ) or 9 (when the reference power supply potential is v _-1 ) Is not necessary, so the total number of output diodes required is only nine.
In this case, in the combined / multi-level logic circuit of FIG. 37 , in addition to at least three circuits of “multi-level NOT circuit and multi-level AND circuit using one-way pull output switch” and multi-level wired OR circuit, the output thereof Nine diodes form a complete system.
At first glance, it seems that the number of parts has increased, but in the case of the synthetic multi-valued logic circuit of FIG. 37 using the reverse blocking type pull switching means described above (the previous paragraph), this is normally necessary. The total number of reverse blocking and output diodes is 100, and 91 extra output diodes are required.

Alternatively, in the combined / multi-level logic circuit of FIG. 35 , for example, when the power supply potential increases in the order of v ₀ to v ₄ , v B and v _{5 to} v ₉ and there is an extra power supply potential v B, You can also do the following.
Each multi-level OR circuit in the combined / multi-level logic circuit of FIG. 35 outputs an output signal based on the power supply potential vB. Therefore, for each of the "multi-value OR circuits whose specific integer value for output is any one of 0 to 4", the output switch section is a reverse blocking pull down switching means. On the other hand, the output switch part is a reverse blocking type pull-up switching means with respect to each “multi-value OR circuit whose specific integer value for output is any of 5 to 9”.
The power supply potential vB serving as a reference potential of the output signal is not necessarily there in between both the power supply potential v4 · v5, among the power supply potential v ₀ to v _9, the two power supply potential adjacent any two It does not matter if there is an interval. Of course, in this case, it pulls up higher than the power supply potential vB or pulls down lower than the power supply potential vB.
The same applies to the combined / multilevel logic circuit of FIG. 37 , and each multilevel AND circuit outputs an output signal based on the power supply potential vB. In synthesis and multi-valued logic circuit it is 35 described above in synthesis and multi-valued logic circuit of FIG. 37 that the was for that each multi-value OR circuit fit for the respective multi-level AND circuits.
In these cases, there are cases where there are two pull directions, so in the combined / multi-level logic circuit of FIG. 35 , “a multi-level NOT circuit, a multi-level AND circuit and a multi-level OR circuit using a one-way pull output switch At least four circuits form a complete system, and in the combined / multi-level logic circuit of FIG. 113, “[Multi-level NOT circuit and multi-level AND circuit using one-way pull output switch” ”and multi-level wired OR circuit Of at least four circuits form a complete system.

Alternatively, each multi-level AND circuit in the combined / multi-level logic circuit of FIG. 37 outputs an output signal based on the power supply potential vB as described above (contents of the preceding paragraph). This is the case where a pull switching device of reverse conduction type or reverse conductivity type is used for the output switch portion.
The output switch unit is a pull-down switching means such as a reverse conduction type or a reverse conduction type for each “multi-level AND circuit whose specific integer value for output is any of 0 to 4”. The same is done with the paragraph number [ 0159 ].). The output terminal and all of the multi-value AND circuits whose output specific integers have the same value are connected once (every), and between the common terminal and the output terminal Tf every connection (common terminal). Connect the diode in the pull down direction.
On the other hand, for each of the "multi-level AND circuits whose specific integer value for output is any of 5 to 9", the output switch section is a pull-up switching means such as reverse conducting type or reverse conducting type, As in the case described above (paragraph number [ 0159 ]). "All AND circuits with the same value specific integer for output" are connected once (every) to its output terminal, and the diode between the common terminal and the output terminal Tf every connection (common terminal) In the pull-up direction.
In this case, there are cases where there are two pull directions. Therefore, in the combined / multi-level logic circuit of FIG. 37 , “[Multi-level NOT circuit and multi-level AND circuit using one-way pull output switch”] and multi-level wired In addition to at least four of the OR circuits, nine of its output diodes form a complete system.

◆ ◆ ◆ ◆ ********** Fourth 10-Valued Logic Complete Circuit ********** ◆ ◆ ◆ ◆
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●● 22) shown in FIG. 40 the fourth 10-valued logic complete circuits (= synthetic-multi-valued logic circuit). The multi-level logic complete circuit of FIG. 40 is an improvement of the multi-level logic complete circuit of FIG. 35 , and “multi-level EVEN circuit and“ multi-level EVEN circuit "Pull-up resistance or pull-down resistance" is inserted and connected one by one.
By this, when various multilevel synchronous logic means are used for the multilevel logic complete circuit of FIG. 40 , it is possible to make each synchronous timing and each signal propagation time uniform. For example, the synchronization timings of "all-synchronous NOT means and all-synchronous EVEN means" may be matched, the synchronization timings of all-synchronous AND means may be matched, and the synchronous timings of all-synchronous OR means may be matched. it can.
In this case, for example, the three synchronization timings may be different from each other, or the synchronization timings of the “all-synchronous NOT means and the all-synchronous EVEN means” and the synchronization timings of the all-synchronous OR means are the same. There are also cases where only the synchronization timing of the all-synchronous AND means differs.
Also in the multivalued logic complete circuit of FIG. 40, also in the multi-valued logic complete circuit of FIG. 35, using OR equivalent circuit of FIG. 33, the multi-level AND means and the multi-level OR means multilevel NAND means Can be replaced one by one. This is because "the multi-value NOT means connected to the subsequent stage of the multi-value AND means, etc." is equivalent to the multi-value NAND means.
Of course, the specific integer value of each multi-level NAND means is set to "a specific integer value of each multi-level logic means to be replaced".
The configuration of the multivalued logic complete circuit of FIG. 40 will be described. The multivalued logic complete circuit of FIG. 40 satisfies the 10-value truth table (FIG. 36 ) representing the multivalued logic function f (x, y). When "multi-value NOT circuit or multi-value EVEN circuit" determines input logic variable y, if y value and f value in the truth table are the same, the multi-value EVEN circuit is used, otherwise the multi-value NOT circuit Is used. The specific value common to the input and output of each circuit is the y value to be determined. These things are the same also in x value discrimination.
Each multi-value AND circuit expresses each of the correlations of the x value, y value and f value one by one "by connecting their three numerical signals in their own circuit", and the specific value common to their own input and output The f value is output to the output terminal Tf via “a post-stage multi-value OR circuit having the same specific value as the input / output same as oneself”.
Each multi-level OR circuit plays a role of putting together all "pre-stage multi-level AND circuits having the same specific value as the input and output".
For each pull ・ “up or down” resistance between one stage and two stages ・ Each pull ・ “Up or down” resistance for matching the previous stage output signal • for the latter stage input signal Match the previous stage output potential, its y value and f value If identical, pull up / down to "power supply potential corresponding to values other than the same value", and if different, pull up / down to "power supply potential corresponding to the f value". The same applies to the side of the x value and the f value.
For each pull between “1 stage and 2 stages” ・ “Up or down” resistance: The pull-up for “pre-stage output signal” • “pull up / down” for “post-stage input signal matching” “power supply potential corresponding to values other than its f value Pull to "up or down".

◆ ◆ ◆ ◆ ********** The fifth 10-valued logic complete circuit ********** ◆ ◆ ◆ ◆
***
●● 23) showing the fifth 10-valued logic complete circuits (= synthetic-multivalued logic circuit) in FIG. 41. The multi-level logic complete circuit of FIG. 41 is an improvement of the multi-level logic complete circuit of FIG. 37 , in which “multi-level EVEN circuit and“ multi-level EVEN circuit "Pull-up resistance or pull-down resistance" is inserted and connected one by one.
Alternatively, in the case of multi-valued logic circuit based on the principle of Fuji algebra, since the multi-level wired OR is satisfied, the multi-level logic complete circuit of Figure 41 is a full-multi-value OR circuit in multivalued logic complete circuit of "Figure 40 The circuit configuration is simplified by replacing it with a multi-value wired OR circuit.
This makes it possible to align the multi-value logic when using various multivalue synchronous logic means complete circuits, each-signal propagation time and the Synchronous timing of Figure 41. For example, the synchronization timings of "all-synchronous NOT means and all-synchronous EVEN means" can be matched, and the synchronization timings of all-synchronous AND means can be made equal. However, it goes without saying that both synchronization timings are completely different and usually shifted.
The configuration of the multivalued logic complete circuit of FIG. 41 will be described. The multivalued logic complete circuit of FIG. 41 satisfies the 10-value truth table (FIG. 36 ) representing the multivalued logic function f (x, y). When "multi-value NOT circuit or multi-value EVEN circuit" determines input logic variable y, if y value and f value in the truth table are the same, the multi-value EVEN circuit is used, otherwise the multi-value NOT circuit Is used. The specific value common to the input and output of each circuit is the y value to be determined. These things are the same also in x value discrimination.
Each multi-value AND circuit expresses each of the correlations of the x value, y value and f value one by one "by connecting their three numerical signals in their own circuit", and the specific value common to their own input and output Is output to the output terminal Tf as the f value. Pre-stage output signal / Pull-stage input signal matching Pull-up / down resistance pulls up the pre-stage output potential to “power supply potential corresponding to values other than the same value” when the y value and f value are the same "Up or down", otherwise "pull up or down" to "power supply potential corresponding to the f value". The same applies to the side of the x value and the f value.
■ multivalued logic complete circuit diagram with improved multi-valued logic complete circuit of FIG. 41 42 ■
The multivalued logic complete circuit with an improved multi-valued logic complete circuit of FIG. 41 is shown in FIG. 42. In the multilevel logic complete circuit of FIG. 42 , unnecessary potential oscillations (or voltage oscillations), such as overshooting and undershooting, generated at each input portion of each multilevel AND circuit are suppressed.
In the multi-level logic complete circuit of FIG. 41 , each “multi-level NOT circuit or multi-level EVEN circuit” is connected with a pull resistor that pulls up or down its output potential to a predetermined constant potential of its circuit when the output is open. In the multi-level logic complete circuit of FIG. 42 , in order to suppress the unnecessary vibration, each input potential of each multi-level AND circuit is referred to as Among the predetermined constant potentials, one lower clamper is connected to clamp each constant potential, with the lower one being the low potential side and the higher one being the high potential side.
By this, the multi-valued logic complete circuit of FIG. 42 can suppress each input potential oscillation (or input voltage oscillation) of each multi-valued AND circuit. This suppression function is also useful for preventing the occurrence of multi-level hazards and the transmission delay of the transmission signal.

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◆ ◆ ◆ ◆ ***** Disclosed contents such as JP 2012-075084 gazette ***** ◆ ◆ ◆
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● ● 24) “Various multi-level logic circuits based on the principle of Fourier algebra” and “Multi-level logic means with synchronous latching function and multi-level hazard removal means” (Japanese Patent Application Laid-Open No. 2012-075084) As a precaution, the inventor will now describe these techniques in the paragraph numbers [ 0165-0284 ] so that they can be treated in the same way as the technical common sense in the description of the present invention.

分 技 分 Technology ◇ ◇ ◇
The first application of the prior application is a multilevel logic means having a synchronous latching function in which a multilevel logic circuit in a potential mode (or a voltage mode) based on the following "Fuji algebra (= multilevel logic)" is provided with a synchronous latching function. "
The above-mentioned "synchronous latching function" does not have such an all value latching function, instead of latching using a "multivalued synchronous latching means having an" all value latching function capable of latching any value used in multivalued logic ". There are the following effects and features when latching in units of “multi-level logic means having
1) Since the binary synchronous flip flop means is built in, each trigger method (example: edge trigger, level trigger, pulse trigger) can be used as it is.
★ Reference materials on “each trigger method”: pages 79 to 88 of the following non-patent document 4.
2) It is possible to latch "signal status corresponding to open output or open output".
Note: The following "Fuji Algebra" has a unique output method of "releasing output".
● 3) There is no latching function for "a signal state corresponding to each integer other than a specific integer for output among all multi-valued values". That is, there is no extra and unnecessary latching function.
→ → There is no wasted parts and no wasted configuration, so parts and circuits can be used efficiently and power consumption can be saved.
→ → Multilevel circuit to be used {Example: Multilevel logic circuit, multilevel operation circuit (or multilevel arithmetic circuit), multilevel storage means, multilevel memory means, multilevel digital circuit, etc. According to the configuration of}, there are more options for multi-level synchronous latching means connected to the subsequent stage, which is convenient.
Conventionally, for example, it has been considered to provide a multi-level synchronous latching means between a multi-level circuit and a multi-level circuit.
P. 79-88 (binary pulse trigger system). Japan Riko Publishing Co., Ltd. published 4th edition on April 25, 2008. Author: Nakamura Tsugio.

● In addition, since there are only two states in the flip flop originally, the term “multi-level flip flop” is not consistent, so the term “multi-level latching means” is unified.
● In addition, although the multilevel logic circuit which is the configuration means of each invention is an embodiment of "multilevel logic created by the present inventor", it can be used as the new / multilevel logic. Since it is inconvenient if there is no name, I decided to name it "Hooji Algebra" (details in paragraph numbers [ 0100 to 0163 ]).
The reason why it was so named is, "Because the inventor is Japanese, that it is attributed to Mt. Fuji, which is a symbol of Japan,""Boolean" of "Boolean Algebra" (Ground) and "The ability, possibility, practicality, expansion extensibility, future potential, etc." Because the present inventors strongly judge that it is a huge, it is that the word path is adjusted to an English huge (huge). (Reference: following · Patent documents 1-3.)
When the English name is decided, “H” in the “Huge” space, “oo” in the “Boole” space, and “ji” in the “Fuji” space are combined into “Hooji”. did.
Japanese Patent Application Laid-Open No. 2004-020322 (Multi-valued logic circuit based on the principle of the Fourier algebra) JP 2005-198226 (ibid) JP 2005-236985 (ibid)

● Furthermore, in the field of logic mathematics, the concept of "open the output" or "open output (example: open collector, open drain.)" Which is well known as a basic technology in electronic circuits, is itself described above. "Fuji's algebra" was not before. However, with the advent of this "Fuji Algebra", I had to adopt the concept. This is because "Fuji's algebra" has a number of "advantage unique effects" that are not found in conventional multi-valued logic. → → Paragraph numbers [ 0100 to 0119 ].
On the other hand, even in the field of electronic circuits, "All in one type or several types of basic / multilevel logic circuits alone" or "combination thereof or combinations thereof" regardless of the multilevel number N (N value of N). Function that can realize and embody the multi-valued logic function of "", that is, "completeness", it is "complete"", and additionally, it does not rely on multi-valued logic system published in the field of logic mathematics, and is built independently There is no multilevel logic system and circuit before the above patent documents 1 to 3. The "fullness" of the above "Fuji Algebra" was proved in paragraph numbers [ 0134 to 0147 ].
★ Reference materials on “complete system, completeness, complete”: the following non-patent documents 1 to 3.
Then, in the present invention, each integer of N value and each constant electric potential supply means (eg, power supply line, power supply plate, etc.) correspond one by one to each other in order, but as the integers become larger, The case where these constant potentials go "high" corresponds to the positive logic and the "when it goes low" corresponds to the negative logic in numerical order from the first constant potential to the N-th constant potential.
“Introduction to logic circuits”, author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd., September 28, 2001. “Chapter 2 Logic Functions” → “2.1 Basic Logic Operations” → “2.1.4 Basic Logic Operations and Logic Symbols” → “(8) Complete System” (p. 31 to p. 32). “A well understood digital electronic circuit”, p. Line 14 of 9 ~ p. "Complete system" of the first line of ten. Author: Sekine Keitaro, Inc. Ohm company published on July 25, 1997. "Multi-value information processing-post-binary electronics-" Authors: Tatsuo Higuchi, Michitaka Kameyama (Michitaka), Shokodo (Shikokodo) published in June 1989. p. 16 to p. 17.

The prior art second invention relates to a multilevel hazard removing means utilizing the "multilevel logic means having a synchronous latching function" of the prior art first invention, wherein the multilevel number N (= N of N value). Regardless of the value, it is possible to remove the multi-value hazard generated before or at the time of the input of the multi-value hazard removal means.
In the multi-level circuit (eg, multi-level logic circuit, multi-level arithmetic circuit (or multi-base arithmetic circuit), multi-level memory, multi-level memory, multi-level digital circuit, etc.) In addition to the multi-level hazards generated by the following mechanism, there are three or more “logical values, logic levels and potentials (or voltages) corresponding to each other one by one” together, “multi-level unique multi-level hazards” Occur.

背 背 Background technology 技 ◇
■ ■ ■ ■ Prior art of the first invention Background art ■ ■ ■
As a conventional multi-level synchronous latching means, multi-level synchronous latch (level) means of level trigger system is disclosed in Example 10 (paragraph number 0035) of JP-A-2006-345468, and JP-A-2007-35233. 18 and FIG. 15 of the patent publication disclose multi-level synchronous latching means of the pulse trigger system (= master slave system).
However, “each multi-level synchronous latching means of the method corresponding to each binary flip flop means of the positive edge trigger method and the negative edge trigger method” has not been embodied or put into practice yet. Naturally, positive and negative edge trigger schemes can not be used.
If the synchronous multi-level circuit can be triggered at the rising or falling of the synchronization signal, the options of trigger timing and trigger method increase and it becomes very convenient. For example, if each edge trigger method can be used, the step-like multilevel synchronization signal (reference: Patent Document 7 below) considered by the present inventor can be used more effectively. The choice of trigger timing increases in one cycle, which is very convenient.
Therefore, in the prior art, there is a problem that "the positive and negative edge trigger methods can not be used". (First Problem to be Solved by First Application First Invention)
JP-A-2006-345468 (multi-level synchronization signal generating means etc.). In the stepped multilevel synchronization signal waveform of FIG. 4, there are a plurality of rising portions or falling portions in one cycle. For example, it is possible to select one of the "plurality of rising portions or falling portions" depending on which two power supply lines of the multi-value overall circuit one synchronous binary flip flop means is provided. it can. It is also possible to provide synchronous binary flip flop means at each of the plurality of places.

  Also, in the case of the potential mode (or voltage mode) multilevel logic circuit based on the above-mentioned "Fuji Algebra", there is an important output method of "output open or open output". There is also a problem that the mold latching means can not latch the signal state corresponding to [output open or open output]. (The second problem to be solved by the first application first invention)

Furthermore, there is a problem that "the latching function corresponding to [the output numerical value] is not provided and a waste occurs." (The third problem to be solved by the first application first invention)
For example, either of the multi-level synchronous latching means has "an all-value latching function that can be used to latch any number used in multi-level logic". If the (input) value to be output is all over the value, the use efficiency of the latching function is good, but “when only a part of the value is output (input) (= number to latch) In the case of limitation, the use efficiency of the latching function deteriorates in terms of the effective use of components and circuits as well as the power use efficiency.
That is, since "the latching function part corresponding to the numerical value not output" is not used, the circuit of the functional part is wasted, and "when all transistors etc. are switched on / off due to the rewriting of the latching content" The total switching loss of the above becomes extra due to the “switching loss of the unnecessary useless latching function part”.
In other words, the number of parts is extra for "the latching function part for the numerical value not output", and the circuit configuration becomes complicated, so that the effective utilization rate of the part / circuit becomes worse and the extra latching function It consumes extra power for the part's on / off switching loss.
Moreover, if all the transistors etc. are voltage driven type such as MOS.FET or insulated gate type transistors, there is also charge / discharge energy loss due to electrostatic capacity between the gate and source etc. Therefore, charge / discharge of the extra latching function part The energy loss consumes extra power.
As a result, the latching function and the use efficiency deteriorate in terms of the effective use of the component and the circuit as well as the power use efficiency. If the effective utilization rate of the parts and circuits is poor, the area occupied by the multi-level synchronous latching means in the two-dimensional IC or in the two-dimensional LSI naturally becomes large in the case of the three-dimensional IC and LSI. Become a factor of cost up.
As described above, the reason why the latching function and the use efficiency are poor is that "there is an extra latching function for each value other than the output value".
Therefore, there is a problem that "the latching function corresponding to [[numerical value to be output] is not provided and a waste occurs"]. (The third problem to be solved by the first application first invention)

Then, if you want to use multi-level circuit {example: multi-level digital circuit etc. It is convenient if it is possible to select multi-level synchronous latching means connected to the subsequent stage according to the configuration of}.
Specifically, if the multi-level logic means has the synchronous latching function, it can perform synchronous latching per multi-level logic means / unit, so that flexibility is created in the whole circuit configuration, and the whole circuit configuration There are more options to be useful.
→ → In the case of each multi-level logic circuit based on “Fuji Algebra”, you can easily change the “numerical value” to be latched by changing the connection of the constant potential supply means (eg power supply line, power supply plate etc.) to which this circuit is connected. Above, the circuit used can be selected from among the various multilevel logic circuits. That is, since there are many options for the multilevel logic circuit from the beginning, if it is possible to give each multilevel logic circuit a synchronous latching function, the "selectable multilevel synchronous latching means" increases and becomes convenient.
Therefore, multilevel circuits to be used {example: multilevel logic circuit, multilevel arithmetic circuit (or multilevel arithmetic circuit), multilevel memory, multilevel storage means, multilevel digital circuit, etc. It is desirable that there are many options of multi-level synchronous latching means connected to the subsequent stage according to the configuration of}. If there are many such options, flexibility is created in the configuration of the entire multilevel circuit. (The fourth problem to be solved by the first application first invention)
→ → For the various multi-level logic circuits, for example, the inventors of the present invention have implemented “(multi-level) AND circuit, (multi-level) OR circuit, (multi-level) NOT circuit, (multi-level) NAND circuit, (multi-level) NOR Circuit, OVER circuit, NOVER (Nounbar) circuit, EVEN (even) circuit, UNDER circuit, NUNDER (Nander) circuit, IN circuit, NIN (Nin) circuit, OUT circuit, NOUT (Nout) circuit There are logic circuits and their combination multi-level logic circuits (eg, multi-level ANDANDOVER circuits, multi-value OROROUT circuits, etc.).

In the prior art, multi-level synchronous latching means must be provided between multi-level circuits and multi-level circuits, and the latching locations are fixed. If there are many options for the latching point, flexibility is created in the configuration of the entire circuit.
Therefore, it is desirable that there are many options for the latching point “where to latch in the entire circuit”. (The fifth problem to be solved by the first application first invention)

■ ■ ■ ■ Prior art of the second invention Background art ■ ■ ■
Here, the explanation will be made on the premise of the above-mentioned preliminary knowledge (paragraph numbers [0007 to 0020]). In general, "hazard" corresponds to false "ghost signal, ghost data or ghost information" as "signal noise" in both conventional binary circuits and multilevel circuits, and transmits real "signals, data or information" It makes it difficult to understand "where" and "where", or where "from" to "where" is the real "signal, data or information". Then, the "hazard" adversely affects other circuit operations (such as malfunction or unnecessary circuit operation).
In addition, the five problems of the conventional multilevel logic circuit are summarized as follows. Detailed descriptions of these will be described later.
◆ 1) In addition to the problem of hazard that occurs with the same mechanism as the conventional binary hazard, because there are three or more of both the logical value and the logic level, “when the logic level of a certain multilevel signal changes, In particular, there are many problems inherent in multi-level circuit problems and multi-level hazards, in which transient hazards are generated by passing through the logic levels of
(First Problem to be Solved by Prior Invention Second Invention)
★ Reference: Lines 13 to 10 from the bottom of the bottom of Non-Patent Document 8 below. Multi-value inherent hazard.
◆ 2) “Similarly, when the logic level of a certain multilevel signal changes, overshooting or undershooting may cause the logic level area to go beyond the original logic level area to reach the next logic level area and then go to that logic In particular, there are many problems inherent in multi-level circuits, such as multi-level hazards, in which transient hazards are generated by returning to or convergence with the level area. (The second problem to be solved by the second application of the prior application)
◆ 3) In the multi-level circuit, there is a problem that "multi-level hazards lead to amplification / increase of power loss". (The third problem to be solved by the second application of the prior application)
◆ 4) The larger the multi-level number, the larger the adverse effect of each of the above first to third problems. Therefore, "the larger the number of multi-level logic circuits, the larger the adverse effect of multi-level hazards".
(The fourth problem to be solved by the second application of the prior application)
◆ 5) Even when using the conceivable conventional multi-level hazard elimination circuit, the influence of the multi-level hazard can not be avoided in the circuit part of the previous stage before removing the multi-level hazard, but the circuit subrange I want to make it as small as possible.
Therefore, there is a problem that "If possible, the range in the circuit affected by the generated multilevel hazards should be narrowed as little as possible". (The fifth problem to be solved by the second application of the prior application)
"High-tech classroom multi-level logic circuit IC integration degree increase binary numbers and three values also go", Nikkei Sangyo Shimbun (Tokyo version) published November 22, 1985. Writing: Ishizuka Kohiko.

Detailed description of the first and third problems to be solved by the second invention
From here, "the occurrence of multi-value-specific hazard due to the first factor" will be described using an easy-to-understand example. For example, when the input numerical value of the first multi-level circuit changes from the minimum value "0" to the maximum value "3" with the multi-value number N = 4, the numerical values "1 and 2" in the middle always pass through The output side of the circuit goes from "the output numerical value corresponding to the input numerical value 0" to "the output numerical value corresponding to the input numerical value 1", "the output numerical value corresponding to the input numerical value 2" to "the output numerical value corresponding to the input numerical value 3" Become. At this time, depending on the value of each output numerical value, a multi-value hazard occurs as follows.
Temporarily, if "the output numerical value corresponding to the input numerical values 1 and 3" is "3" and that "the output numerical value corresponding to the input numerical values 0 and 2" is "0", the input numerical value is from "0" Since the output numerical value changes needlessly three times as “0” → “3” → “0” → “3” while changing to “3” once, the number of changes on the input side is amplified three times, and , A first extra pulse appears at its output.
(The occurrence of the first multi-level hazard → → ● First issue to be solved by the second invention of the prior application)
And if the same thing happens in the second multi-level circuit of the latter stage where the output numerical value is input, and so on, not only "while the input numerical value changes once from" 0 "to" 3 "" The same thing happens when the input numerical value changes once from "3" to "0".
That is, even while the input numerical value changes once from "3" to "0" in the second multilevel circuit, the output numerical value is "3" → "0" → "3" → "0" and so on. Because of the change, the number of changes on the input side is amplified three times, and a second extra pulse appears at the output.
(The occurrence of the second multi-level hazard → → ● The first problem to be solved by the second invention of the prior application)
As a result, for each change of the input numerical value of the second multi-level circuit, that is, three changes of "0 → 3", "3 → 0" and "0 → 3", the one input value change Since (at each) the output side has 3 times of value change and 1 extra pulse appearance, after all, 1 time change of the input numerical value of the first multilevel circuit is the second multilevel circuit On the output side of this, nine numerical changes and three extra pulses appear. No, the appearance of the extra pulse is a total of four. In fact, it can be understood by drawing the nine numerical changes on paper.
In this way, if the same thing occurs in the second multi-level circuit after the second stage and so on, the "number of times the wasteful change" and "the number of extra pulses generated" are the number of connected stages of the multi-level circuit. It takes more and more to take as it piles up. As a result, the circuit operation becomes extremely complicated and abnormal as it becomes the subsequent circuit, and further adversely affects other circuit operations. It will become useless to get rid of it.
As an example of the adverse effect, "appearance of signal noise", that is, "to make it difficult to understand where and where, or where to which is the true" signal, data or information "", "malfunction due to hazard noise", “Ineffective circuit operation” or the like.
(Amplification and increase action of multi-level hazard occurrence frequency and expansion of adverse effect due to it)
→ ● (● First issue to be solved by the second invention of the prior application)
Moreover, even if one hazard pulse is "one dust or pile, it will be a mountain" and it can not be ignored naturally if the hazard pulses in the multi-level circuit are summed up. “Amplification and increase”, ie, “amplification and increase of the number of multi-level hazard occurrences within a substantially fixed period (= multi-level hazard, high frequency of pulse generation frequency)”, “switching (power) loss at on / off switching, MOS In the case of FET, it means that the power loss associated with charge and discharge such as gate-source capacitance is further amplified and increased.
(More wasteful increase in power loss → → ● Third issue to be solved by the second invention of the prior application)

Detailed description of the second and third problems to be solved by the second invention
Next, “the occurrence of multi-value-specific hazard due to the second factor” will be described using an example that is easy to understand. If it is assumed that the output numerical value of the first multi-level circuit changes from the minimum value "0" to the numerical value "2" at multi-level number N = 4, the input section of the second multi-level circuit in the subsequent stage Overshooting, undershooting occurs if it is negative logic. On the other hand, when the output numerical value changes from the maximum value “3” to the numerical value “1”, “undershooting in positive logic, overshooting in negative logic” occurs oppositely.
Although these damped oscillations become the second cause of multi-level hazards, the output resistance of the first multi-level circuit is usually small, and the input impedance of the second multi-level circuit is capacitive (example: MOS · FET) Capacitance between the gate and the source.) If there is a floating impedance on the signal line between the two circuits, the internal resistance is small, and thus overshooting or undershooting is likely to occur. That is, when it is intended to transmit a signal from the former stage to the latter stage quickly with energy efficiency, those damping oscillations are likely to occur.
If overshooting or undershooting of the input signal swings too much, the input signal passes the “intending logic level area” and reaches the adjacent logic level area, and then the “intending logic level area” If it returns or converges, the hazard pulse will be generated transiently. Such hazard pulses often occur in ternary circuits.
(Occurrence of multi-level hazard due to overshooting etc.)
→ ● (● The second problem to be solved by the second application of the prior application)

Here, we will simplify and briefly explain how overshooting and undershooting occur. Now, consider the operation of a circuit in which a series resonant circuit is connected to both ends of a DC power supply via a bidirectional switch. Stored energy in the series resonant circuit as an initial condition is zero, turning on its bidirectional switch as energy loss zero at the resonant operation, the voltage of the resonance capacitor voltage zero around the power source voltage V _E Oscillates between 2 and 2V _E endlessly. If the power supply voltage directions are exactly opposite, the voltage of the resonant capacitor oscillates endlessly between the voltage zero and the negative 2V _E around the power supply voltage minus V _E.
In short, if there is no energy loss in the resonant operation, the voltage of the resonant capacitor will easily reach twice the power supply voltage (= twice the power supply potential difference).
In a general digital circuit, for example, the resonance capacitor is the gate-source capacitance of the MOS-FET, the resonance coil is the floating inductance of the signal line or wiring between the front circuit and the rear circuit, and the front circuit Output resistance is relatively small.
Similarly, when the input signal potential changes from the lowest power supply potential to the intermediate power supply potential in a ternary circuit, the input signal potential lightly reaches the highest power supply potential if there is no power loss in the resonance operation. (Overshooting). Then, even when the input signal potential changes from the highest power supply potential to the intermediate power supply potential, if there is no power loss in the resonance operation, the input signal potential lightly reaches the lowest power supply potential (undershooting).
However, since there is a power loss in the resonance operation in practice, the resonance operation is damped oscillation, so the input signal potential reaches only "before the maximum power supply potential" or "before the minimum power supply potential" There are many cases where you can not do it. However, for example, in the case of positive logic in a three-value circuit of numbers 0, 1, 2, the threshold potential of logic level 2 is “minus threshold potential with reference to its highest power supply potential”. On the other hand, since the threshold potential of the logic level of numerical value 0 is "the positive side threshold potential with reference to the lowest power supply potential", the input signal potential is the logic level area of numerical value 2 by the overshooting. And undershooting often reach the logic level area of the numerical value 0 even in a ternary circuit.
(Occurrence of multi-level hazard due to overshooting etc.)
→ ● (● The second problem to be solved by the second application of the prior application)
If this is a 4-value circuit of numbers 0 to 3, for example, the "potential difference corresponding to number 0 · number 2" will usually be twice the "potential difference corresponding to number 2 · number 3". -Since the corresponding potential difference between the numerical values 3 is usually three times as large as the "potential difference between the numerical values 3 and 4", the input signal potential of the numerical value changes extremely easily by the overshooting. It is possible to pass the logic level area of the numerical value to which the next logic level area can be reached. And, as the number of oscillations of the overshooting or the undershooting increases, the number of times to reach the adjacent logic level area increases, and the number of generated hazard pulses increases.
(Occurrence of multi-level hazard due to overshooting etc.)
→ ● (● The second problem to be solved by the second application of the prior application)
Moreover, even if one hazard pulse is "one dust or pile, it will be a mountain" and it can not be ignored as long as the hazard pulses in the multi-level circuit are summed up, but in addition the increase in the number of hazard pulses is "on・ Increasing switching (power) loss at the time of off-switching or “in the case of a MOS-FET, an increase in power loss due to charging and discharging of capacitance between gate and source”.
(More wasteful increase in power loss)
→ ● (● Third issue to be solved by the second invention of the prior application)

In the case of a binary circuit, since there are only 0 and 1 in the numerical value, that is, there are only two types, the highest power supply potential and the lowest power supply potential, the input signal potential is "the highest power supply potential side and the lowest power supply potential side" There is no overshooting or undershooting problem as described above, as it is possible to absorb overshooting or undershooting of its input by diode clamping each in one direction.
However, in the case of a multilevel circuit, since there is at least one intermediate power supply potential, it is not possible to use the method of “diode clamping the input signal potential to the intermediate power supply potential”. Because, if the input signal potential of the subsequent circuit is diode-clamped to one of the intermediate power supply potentials in one direction, the output of the preceding circuit is not the intermediate power supply potential so that the forward voltage of the diode is obtained. This is because when the power supply potential is output, the output section and its clamp diode cause a power supply short circuit.

Detailed description of the fourth problem to be solved by the second invention
First, the larger the number of multi-levels, the more "the number of logic levels in the process of passing when the logic level of the multi-level signal changes", and multi-level hazards are more likely to occur. As the number of stages of multi-level circuits is increased, the amplification and increase action of the number of occurrences becomes stronger, so the degree of adverse effect of the first and third problems also becomes larger.
***
Second, the larger the multi-value number, the larger the change from a smaller value to a larger value, or from a larger value to a smaller value, and the larger the change in potential difference corresponding to the value change. And the amplitude of the overshooting and the undershooting is increased, so that the excessive swinging causes the logic level area to reach the adjacent logic level area rather than the adjacent logic level area and the logic level to be originally intended Returning to the area causes "more transient hazards".
In addition, since there are many cases where the logic level area next to that is on both the high potential side and the low potential side of the logic level area to which it should go, there may be cases where "more transient hazards" occur. As the number increases, the degree of adverse effect of the second and third tasks also increases.
Of course, the more “the number of oscillations to convergence or overshooting of the overshooting or undershooting”, the more the number of times to reach the logic level area next to that etc., and the number of generated hazard pulses increases. And the adverse effect is spread by the number of connection stages of the multi-level circuit.
***
Therefore, from the aspect of both "the magnitude of the amplitude and the number of oscillations", "the larger the number of multi-values, the larger the problem of multi-level hazards and the adverse effect". (The fourth problem to be solved by the second application of the prior application)

Detailed description of the fifth problem to be solved by the second invention
Then, as another multi-level hazard removal method, it is disclosed in the above-mentioned "Example 10 (paragraph number 0035) of JP-A-2006-345468 or Figs. 18 and 15 in JP-A-2007-35233". The same conventional multi-level synchronous latching means is provided between each of "a multi-level logic circuit based on a new multi-level logic [Fuji algebra] connected in a plurality of stages before and after""and removed similarly In addition to “Problems to be solved by the first invention of the prior application,” which will be described later (paragraph number [ 0182 ]), it is possible to There is a problem that I want to narrow.
First, since the generation source for generating multi-value-specific multi-value hazards (described in paragraph numbers [ 0175-0178 ]) is the numerical value determination means of the multi-value logic circuit, the multi-value hazards generated by the numerical value determination means The value hazard is transmitted to the output switch section through the on / off driving means in the circuit and the subsequent stage, and the propagation is shut off by the multilevel synchronous latching means on the outside and the subsequent stage.
Also, if the numerical value determination means starts to generate the multi-level hazard, it is when the output of the multi-level synchronous latching means outside the circuit / preceding stage changes.
Therefore, between the two multi-level synchronous latching means in the former stage and the latter stage of the multi-level logic circuit, that is, in the multi-level logic circuit, the effect of the multi-level hazard can be "minorized" However, it will be received as described above (the previous paragraph). This applies to all "multi-level logic circuits sandwiched by two multi-level synchronous latching means connected to the front and rear stages".
Therefore, there is a problem that "If possible, the range in the circuit affected by the generated multilevel hazards should be narrowed as little as possible." (The fifth problem to be solved by the second application of the prior application)

概 概 概 Outline of prior application invention ◇ ◇
◇ ◆ Problems to be solved by the prior application invention ◆ ◇ ◇

■ ■ ■ ■ Prior application first problem to be solved invention ■ ■ ■
For that reason (paragraph numbers 0169 to 0173 ), the conventional multilevel synchronous latching means has the following five problems.
1) The positive and negative edge trigger methods can not be used.
→ → For example, if each edge trigger method can be used, the step-like multilevel synchronization signal considered by the present inventor (the waveform of FIG. 4 of Patent Document 7 below. Its rising portion or falling portion or horizontal portion is Since it becomes possible to utilize the plurality more effectively, it is possible to increase the choice of trigger timing during one synchronization period, which is very convenient.
◆ 2) It is not possible to latch "signal state corresponding to output open or open output".
Note: The above-mentioned "Fuji Algebra" has a unique output method of "releasing output".
◆ 3) It does not have a latching function according to the "numerical value to be output", which results in waste.
→ → If only part of the full value latching function is used, waste occurs in terms of effective use of the part and circuit as well as power loss.
◆ 4) Multi-level circuit to be used {Example: multi-level logic circuit, multi-level operation circuit (or multi-base arithmetic circuit), multi-level memory circuit, multi-level digital circuit, etc. It is desirable that there are many options of multi-level synchronous latching means connected to the subsequent stage according to the configuration of}. If there are many such options, flexibility is created in the configuration of the entire multilevel circuit.
◆ 5) It is desirable that there are a lot of options for the latching part “Where to latch in the entire circuit”.
→ → Conventionally, multi-level synchronous latching means must be provided between multi-level circuits and multi-level circuits, and the latching location is fixed. If there are many options for the latching point, flexibility is created in the configuration of the entire circuit.
JP-A-2006-345468 (Multi-value storage means, multi-value transfer gate means, multi-value synchronous latch means and multi-value synchronous signal generating means).

■ ■ Purpose of the first application first invention ■ ■
Therefore, the object of the first application is to provide "multi-level logic means having a synchronous latching function" having the following five effects.
{Circle over (1)} Each trigger method (for example, edge trigger, level trigger, pulse trigger) of the binary synchronous flip flop means can be used.
(First effect of the first application of the first application)
◆ 2) "Signal state corresponding to output open or open output" can be latched.
(Second effect of the first application of the first application)
3) Since there is no latching function for "each numerical value other than the outputted numerical value (= output specific integer)", the latching function according to "the outputted numerical value" is provided and no waste occurs.
(Third effect of the first application of the first application)
→ → There are no unnecessary parts and no unnecessary components, so parts and circuits can be used efficiently and power consumption can be saved.
◆ 4) Multilevel circuit to be used {Example: multilevel logic circuit, multilevel operation circuit (or multilevel arithmetic circuit), multilevel storage means, multilevel digital circuit, etc. According to the configuration of}, there are more options for multi-level synchronous latching means connected to the subsequent stage, which is convenient. Flexibility arises in the configuration of the entire multi-valued circuit. (The fourth effect of the first application)
→ → In the case of each multilevel logic circuit based on “Fuji Algebra”, the “numerical value” to be latched can be easily changed by the constant potential supply means (eg power supply line, power supply plate etc.) to which this circuit is connected. The circuit used can be selected from among the various multilevel logic circuits. In the first application of the first application, each multi-level logic circuit is provided with a synchronous latching function, so eventually the number of options for the multi-level synchronous latching means increases.
→ → The various multi-level logic circuits are called, for example, “(multi-level) AND circuit, (multi-level) OR circuit, OVER circuit, EVEN circuit, UNDER circuit, IN circuit, OUT circuit, etc.” by the inventor. There is a circuit.
◆ 5) “Latching place in the entire circuit” is more convenient as it has more options for latching. Flexibility occurs in the configuration of the entire circuit. (Fifth effect of the first application)
→ → → Since the multi-value logic means of the first application of the invention · itself has a synchronous latching function, the option “it is not necessary to provide the multi-value synchronous latching means between the multi-value circuit and the multi-value circuit” Is added.

■ ■ ■ ■ Problem to be solved by the prior application second invention ■ ■ ■
As described above (paragraph numbers [ 0174 to 0180 ]), "hazard" is generally regarded as "ghost signal, ghost data or ghost information" as "signal noise" in both conventional binary circuits and multilevel circuits. Equivalently, it prevents the transmission of the real "signal, data or information", "where" and "where", or from "where" to "where" is that real "signal, data or information" Make it difficult to understand. Then, the "hazard" adversely affects other circuit operations (such as malfunction or unnecessary circuit operation).
In addition, the five problems of the conventional multilevel logic circuit are summarized as follows.
◆ 1) In addition to the problem of hazard that occurs with the same mechanism as the conventional binary hazard, because there are three or more of both the logical value and the logic level, “when the logic level of a certain multilevel signal changes, In particular, there are many problems inherent in multi-level circuit problems and multi-level hazards, in which transient hazards are generated by passing through the logic levels of
(First Problem of the Second Invention of the Prior Application)
★ Reference: Lines 13 to 10 from the bottom of the bottom of Non-Patent Document 8 below. Multi-value inherent hazard.
◆ 2) "Similarly, when the logic level of a certain multilevel signal changes, it overshoots by overshooting or undershooting and passes to the next logic level area beyond the logic level area to be originally intended, and then to that direction In particular, there are multi-valued hazards, such as multi-valued hazards such as transient hazards that occur due to the return or convergence to the logic level area to be performed. (Second Problem of the Second Invention of the Prior Application)
◆ 3) In the multi-level circuit, there is a problem that "multi-level hazards lead to amplification / increase of power loss". (The third problem to be solved in the second application of the prior application)
◆ 4) The larger the multi-level number, the larger the adverse effect of each of the above first to third problems. Therefore, "the larger the number of multi-level logic circuits, the larger the adverse effect of multi-level hazards".
(The fourth problem to be solved by the second application of the prior application)
◆ 5) Even when using the conceivable conventional multi-level hazard elimination circuit, the influence of the multi-level hazard can not be avoided in the circuit part of the previous stage before removing the multi-level hazard, but the circuit subrange I want to make it as small as possible.
Therefore, there is a problem that "If possible, the range in the circuit affected by the generated multilevel hazards should be narrowed as little as possible". (First Problem of the Second Invention of the Prior Application)
"High-tech classroom multi-level logic circuit IC integration degree increase binary numbers and three values also go", Nikkei Sangyo Shimbun (Tokyo version) published November 22, 1985. Writing: Ishizuka Kohiko.

■ ■ Purpose of the prior application second invention ■ ■
Therefore, in the prior application second application, “in addition to the multi-level hazard that occurs in the same mechanism as the binary hazard, the multi-level inherent multi-level hazard can also be removed”, The range within the circuit affected by the value hazard can be narrowed as little as possible.

手段 ◆ Means to solve the problem ◆ ◇ ◇
■ ■ ■ ■ "Means for solving the problems" of the first application first invention ■ ■ ■
That is, the first application of the first invention is:
When a predetermined plurality of three or more is represented by N and a predetermined natural number is represented by S,
“The“ N constant potentials where these constant potentials increase or decrease from the first constant potential to the N-th constant potential in numerical order are supplied ”, and each constant potential and 0 to (N First constant potential supply means to Nth constant potential supply means defined as that each integer of -1) corresponds one by one to each of the first constant potential and its integer 0 in order;
“First inlet means to S inlets for S input potential signals” to “Sth inlet means”;
"Exit means serving as the exit of the output potential signal";
When connected between ““ the first constant potential supply means to one specific constant potential supply means for output predetermined among the Nth constant potential supply means ”and the outlet means and driven off” Pull switching means which are turned off in one or both directions;
"" If S = 1, an input integer corresponding to one of the input potential signals; if S 、 2, then all of the S input integers corresponding one to one with each of the S input potential signals Or [S at least one of S input integers corresponding to each of the S input potential signals one by one]] is predetermined in [[integer 0 to (N-1) [Equal to or not equal to a specific input integer], [is larger than or not to a predetermined specific input integer among the integers 0 to (N-2)], [integer 1 to (N 1) whether or not it is smaller than a specific integer for input predetermined in [1], [predetermined in integers 0 to (N-1), two of which have a difference of at least 2] Any one among the specified integers for input] For, to determine positive or negative based on "following (= in paragraphs [0187 to 0188]) Two or four threshold potential" to be applied thereto, and outputs the determination result as a determination result signal "Numerical discrimination means"
"A binary synchronous flip flop means which inputs the" as it is or matches "as the holding signal based on the synchronization signal and outputs the" positive output signal or the complementary output signal "of the holding signal" ,
"Synchronous signal supply means for supplying the synchronous signal to the binary synchronous flip flop means";
The pull switching means is driven on / off based on "the positive output signal or the complementary output signal", but if the output signal of the one based on it indicates that the determination result at the input is affirmative. For example, drive it on, drive it off if negation, or "drive it off if oppositely positive, drive it on if negation" on / off drive means,
And a multilevel logic means having a synchronous latching function.
However, the above-mentioned meaning “less than one input specific integer” does not include the one input specific integer, and the above mentioned “one input specific integer larger” means the one input The specific integers for the input are not included, and the two input specific integers for the input are not included in the meaning of “being between the two specific integers for input” described above.

■ ■ 2 or 4 threshold potentials ■ ■
(1) When these constant potentials increase in numerical order from the first constant potential to the Nth constant potential, further,
● a) "Equal or not":
* In "is equal to", "the positive threshold potential and the negative threshold potential determined in advance with reference to the" specific constant potential for input corresponding to the specific integer for input ". However, when the input specific integer is 0, it is only the positive threshold voltage, and when the input specific integer is (N-1), it is only the negative threshold voltage.
* "If not so", "of the first constant potential to the N-th constant potential, the negative threshold potential determined in advance with reference to the constant potential one higher than the specific constant potential for input" “A plus-side threshold potential predetermined among the first constant potential to the N-th constant potential with reference to a constant potential one level lower than the input specific constant potential”. However, when the input specific integer is 0, it is only the negative threshold voltage, and when the input specific integer is (N-1), it is only the positive threshold voltage.
● b) "Big or not":
* In "is large", it is determined in advance based on the constant potential one higher than "the specific constant potential for input corresponding to the specific integer for input" among "the first constant potential to the Nth constant potential" Negative side threshold potential.
* In "if not", "a positive threshold voltage predetermined based on the specific constant potential for input".
C) "Small or not":
* In the case of "smaller", it is determined in advance based on a constant potential one lower than "the specific constant potential for input corresponding to the specific integer for input" among "the first constant potential to the Nth constant potential" Positive threshold potential.
* In "if not", "minus negative threshold potential determined with reference to the specific constant potential for input".
● d) "Is it between the two specific integers for input or not?":
* In “Is there any between the two?” “The first constant potential to the Nth constant potential, the lower one of the two input specific constant potentials corresponding to the two input specific integers Of the two constant potentials for input among the first constant potential to the Nth constant potential, and the “minus side threshold potential determined in advance based on the constant potential one level higher than the potential” and “the first constant potential to the Nth constant potential “Positive side threshold potential predetermined on the basis of a constant potential lower by one than the higher constant potential”.
* In "If not,""the positive side threshold potential determined in advance based on the lower one of the two specific constant potentials for input" and "the two specific constant potentials for input. Among them, the negative threshold potential determined in advance with reference to the higher constant potential.

(2) When these constant potentials decrease in order of the number from the first constant potential to the Nth constant potential, further,
● a) "Equal or not":
* In "is equal to", "the positive threshold potential and the negative threshold potential determined in advance with reference to the" specific constant potential for input corresponding to the specific integer for input ". However, when the input specific integer is 0, it is only the negative threshold voltage, and when the input specific integer is (N-1), it is only the positive threshold voltage.
* "If not so", "of the first constant potential to the N-th constant potential, the negative threshold potential determined in advance with reference to the constant potential one higher than the specific constant potential for input" “A plus-side threshold potential predetermined among the first constant potential to the N-th constant potential with reference to a constant potential one level lower than the input specific constant potential”. However, when the input specific integer is 0, it is only the positive threshold voltage, and when the input specific integer is (N-1), it is only the negative threshold voltage.
● b) "Big or not":
* "Is large" is determined in advance with reference to a constant potential one lower than "the specific constant potential for input corresponding to the specific integer for input" among "the first constant potential to the Nth constant potential" Positive side threshold potential.
* In "if not", "minus negative threshold potential determined with reference to the specific constant potential for input".
C) "Small or not":
* In the case of "small", it is determined in advance based on a constant potential one higher than "the specific constant potential for input corresponding to the specific integer for input" among "the first constant potential to the Nth constant potential" Negative side threshold potential.
* In "if not", "a positive threshold voltage predetermined based on the specific constant potential for input".
● d) "Is it between the two specific integers for input or not?":
* In “Is there any between the two?” “The first constant potential to the Nth constant potential, the lower one of the two input specific constant potentials corresponding to the two input specific integers Of the two constant potentials for input among the first constant potential to the Nth constant potential, and the “minus side threshold potential determined in advance based on the constant potential one level higher than the potential” and “the first constant potential to the Nth constant potential “Positive side threshold potential predetermined on the basis of a constant potential lower by one than the higher constant potential”.
* In "If not,""the positive side threshold potential determined in advance based on the lower one of the two specific constant potentials for input" and "the two specific constant potentials for input. Among them, the negative threshold potential determined in advance with reference to the higher constant potential.

By this, the "means for solving the problems" of the first application of the prior application is the provision of the binary synchronous flip flop means and the synchronous signal in the conventional "multi-valued logic circuit based on" fuge algebra "". It becomes a "multi-level logic means with synchronous latching function" incorporating means etc.
The conventional multilevel logic circuit comprises the "first constant potential supply means to the Nth constant potential supply means", the "first inlet means to the Sth inlet means", the "outlet means", the "pull · · · In this conventional multilevel logic circuit, the on / off driving means has its pull / switching means based on the judgment result signal. Drive on / off.
As described later (Paragraphs 0195 to 0196 ), the reason why a binary circuit can be incorporated into a multilevel circuit in this way is that "in the middle of the multilevel signal transmission (example: the above-mentioned numerical value determination unit and ), Even if a binary circuit is inserted and connected, the connectivity between the binary circuit and the preceding and succeeding stages is extremely good, even between [the preceding stage and the binary circuit] [the binary circuit There is a special effect that “no special interface is necessary even in the latter part”] in “multi-valued logic circuit based on the principle of the fuse algebra”.
However, there are also cases where it is possible to connect the two as they are, but there are also cases where they are connected for matching.
In addition, the end of paragraph (◇ 1 of paragraph number [ 0201 ]) described later. In some cases, the binary synchronous flip flop means doubles as the on / off driving means.
Furthermore, it is determined whether “the S input integers (= S integers corresponding to each of the S input potential signals one by one) are equal to or not equal to the one input specific integer. Is the same as “determining whether the S input integers are between“ the two integers next to one of the input specific integers ”” or “the S “Determining whether the input integer of s is equal to or not equal to 0” is the same as “determining whether the S input integers are smaller than 1 or not”, and further, “Determining whether the input integer is equal to or not equal to (N−1)” is the same as “determining whether the S input integers are larger than (N−2) or not”. The discrimination of numerical values of the There.

◆ As a result, since it is possible to incorporate the binary synchronous flip flop means between the numerical value judging means and the on / off driving means, each of the binary trigger methods (eg, positive and negative edges)・ Trigger, level trigger, pulse trigger) can be used as it is. (First effect of the first application of the first application)
In particular, the step-like multilevel synchronization signal considered by the present inventor (waveform in FIG. 4 of Patent Document 7; there are a plurality of rising portions or falling portions or horizontal portions thereof) can be used more effectively. Since it is possible, the choice of trigger timing increases during one synchronization signal cycle, which is very convenient.
The reason is that there are a plurality of “rising point or falling point or horizontal portion” depending on which two constant potential supply means (for example, two power supply lines) are connected between the binary synchronous flip flop means. Because you can choose one.
If the output current capacity of the binary synchronous flip flop means is large and the binary synchronous flip flop means satisfies the requirements of the on / off driving means, the binary synchronous flip flop means Of course, the flop means may double as the on / off driving means.
◆ In addition, since the binary synchronous flip-flop means only latches either "a signal state corresponding to a specific integer for output of the multi-valued logic means" or "a signal state corresponding to an open output or an open output". Naturally, "signal state corresponding to output open or open output" can be latched. (Second effect of the first application of the first application)
◆ Furthermore, since there is no latching function for "each numerical value other than the outputted numerical value (= output specific integer)", the latching function corresponding to "the outputted numerical value" is provided and no waste occurs. (Third effect of the first application of the first application)
→ → There are no unnecessary parts and no unnecessary components, so parts and circuits can be used efficiently and power consumption can be saved.
◆ Then, multi-level circuit to be used {Example: multi-level logic circuit, multi-level arithmetic circuit (or multi-base arithmetic circuit), multi-level digital circuit, etc. According to the configuration of}, there are more options for multi-level synchronous latching means connected to the subsequent stage, which is convenient. Flexibility occurs in the overall circuit configuration.
(The fourth effect of the first application)
→ → → In the case of multi-valued logic circuit based on “Fuge algebra”, the specific integer for input by the constant potential supply means (eg power supply line, power supply plate etc.) connected by the numerical value judgment means and pull / switching means respectively In addition to being able to easily change either of the output specific integers, it is possible to select the circuit used from among the various multilevel logic circuits. In the first application of the first application, each multi-level logic circuit is provided with a synchronous latching function, so eventually the number of options for the multi-level synchronous latching means increases.
→ → The various multi-level logic circuits are called, for example, “(multi-level) AND circuit, (multi-level) OR circuit, OVER circuit, EVEN circuit, UNDER circuit, IN circuit, OUT circuit, etc.” by the inventor. There is a circuit.
◆ And, the choice of latching location “Where to latch in the whole circuit” is increased and convenient. Since synchronous latching can be performed in multi-valued logic means · unit, flexibility is generated in the entire circuit configuration. (Fifth effect of the first application)
→ → → Since the multi-value logic means of the first application of the invention · itself has a synchronous latching function, the option “it is not necessary to provide the multi-value synchronous latching means between the multi-value circuit and the multi-value circuit” Is added.
JP-A-2006-345468 (Multi-value storage means, multi-value transfer gate means, multi-value synchronous latch means and multi-value synchronous signal generating means).

Note that N (≧ 3) indicates a multi-valued number N of N values, and the integer used is 0 to (N-1). The first constant potential is an integer 0, the second constant potential is an integer 1, and the third constant potential is an integer 2, ......... << Likewise, both increase by one, >> ........., and The Nth constant potential is defined to correspond to an integer (N-1), respectively.
→ → [Potential mode (or voltage mode)]
Therefore, in terms of the logic level at the input side, it is defined as follows. However, since the expression "H level, L level" of the binary circuit can not be used in multi-level circuits, for example, numerical values are specifically output as "logical level of integer ..." or "logical level of specific integer ..." It can not but be expressed. Also, as a matter of course, the respective logic level areas do not overlap, and one two-area spare area is set between each “two logic level areas adjacent to each other”.
◆ When these constant potentials “go up” in numerical order from the first constant potential to the Nth constant potential:
The “first constant potential region lower than the positive threshold voltage based on the first constant potential” is a logic level region of integer 0, and “the negative threshold voltage potential relative to the second constant potential” The second constant potential region “between the positive threshold voltage and the positive threshold voltage” is an integer 1 logic level region. Likewise, similarly, “a third constant between the negative threshold potential and the positive threshold potential with reference to each constant potential from the third constant potential to the (N−1) th constant potential sequentially The potential area to the (N-1) constant potential area "are sequentially" the logical level area of integer 2 to the logical level area of integer (N-2) ". The “Nth constant potential region higher than the minus side threshold potential based on the Nth constant potential” is an integer (N−1) logic level region.
◆ When these constant potentials “go down” in numerical order from the first constant potential to the Nth constant potential:
The “first constant potential region higher than the negative threshold voltage based on the first constant potential” is a logic level region of integer 0, “the positive threshold voltage potential based on the second constant potential” The second constant potential region “between the negative threshold voltage and the negative threshold voltage” is an integer 1 logic level region. Likewise, similarly, “a third constant between the plus side threshold potential and the minus side threshold potential with reference to each constant potential from the third constant potential to the (N−1) th constant potential in sequence” The potential area to the (N-1) constant potential area "are sequentially" the logical level area of integer 2 to the logical level area of integer (N-2) ". The “Nth constant potential area lower than the plus side threshold potential based on the Nth constant potential” is an integer (N−1) logic level area.
As a result, if the input potential signal is in the first constant potential region in any of "when going high" and "when going low", it is assumed that "the corresponding input integer" is 0. If the input potential signal is in the second constant potential region, it is determined that "the corresponding input integer" is 1. Likewise, if the input potential signal is sequentially present in the third constant potential region to the Nth constant potential region, “the corresponding input integer” is sequentially from 2 to (N−1). It is determined that

However, the above-mentioned "what is the value for the predetermined one or two input specific values" described above (eg, whether it is equal, not, large or not, small or not, etc. Or not)) only two or four of these threshold potentials are applied. However, “a specific input integer for one input can take any one integer value of“ integer 0 to integer (N-1) ””, that is, “when taking integer 0, when taking integer 1, integer 2 In the case of taking..., Taking the integer (N-1), each case is assumed. After all, "the relationship between each integer, each logic level and each threshold potential" Is derived.
As for the two input specific integers, the smaller input specific integer can take any one value of integer 0 to integer (N-3), while the larger input specific integer Since any one of integer 2 to integer (N-1) can be taken according to the specific integer for input, the relationship between each integer, each logic level, and each threshold potential can be similarly obtained after all. Is derived.
By the way, when determining whether the S input integers (= S integers corresponding to each of the S input potential signals one to one each) are “whether or not between 2 and 5” Even if the S input integers are, for example, between 3 and 4, it can be clearly determined that "there is between 2 and 5" even if "there is not". Similarly, when it is determined whether the S input integers are greater than 5 or not, even if the S input integers are, for example, between 7 and 8 and "do not go out", of course "5 It can be determined that “larger”. Similarly, when it is determined whether the S input integers are less than 6 or not, even if the S input integers are between 2 and 3, for example, even if “nowhere”, “6 It can be determined that “smaller”.

Now, the output specific integer is represented by m, and the logic level on the output side will be described. In the case of the multi-valued logic means of the first application, the output is either the specific integer m for output or the output open. The output specific constant potential supply means is selected from one of the first constant potential supply means to the Nth constant potential supply means, so the output specific integer m is an integer 0 to (N-1 ) Can take any one integer value. Regardless of which integer value the output specific integer m takes, the logical level area of the output specific integer m is always included in the "input side logic level area of the integer m" of the subsequent circuit with a margin. It is set to be The one or two margin regions are the "noise margin (or noise margin) with respect to noise". This is easy to understand if it is considered by the extension of the binary circuit.
Here, considering the (international) unification and standardization of the standards and specifications of each threshold potential, “what can be said about each input side logic level area of its subsequent circuit” is each of the respective multi-level logic means. Since the same applies to the input side logic level area, the explanation of the output side and the logic level will be the multilevel logic means itself "the output logic level area of specific integer m" and the "input side logic level area" Will be explained. When that happens, the specific integer m for the output may take any integer value from "integer 0 to integer (N-1)", so on the output side each integer from 0 to (N-1) It is necessary to determine the corresponding logic level area.
Therefore, when these constant potentials “go up” in numerical order from the first constant potential to the N-th constant potential, the negative side threshold value of each input side logic level of integer 1 to integer (N−1) The “negative threshold voltage of its output logic level” is higher than the potential by the noise margin on the negative side, and the positive logic threshold of each of the integer 0 to integer (N−2) input logic levels The "plus side threshold potential of the output side logic level" is lower than the value potential by the noise margin on the plus side. The respective threshold potentials are as described above (paragraph numbers [0007 to 0020]).
On the other hand, when these constant potentials “go down” in numerical order from the first constant potential to the Nth constant potential, positive side threshold values of the input side logic levels of integer 1 to integer (N−1) The plus side threshold potential of its output side logic level is lower than the potential by the noise margin on the plus side, and the minus side threshold of each input side logic level of integer 0 to integer (N-2) The “negative threshold voltage of the output logic level” is higher than the value potential by the noise margin on the negative side. The respective threshold potentials are as described above (paragraph numbers [0007 to 0020]).
These things are the relationship between “H level input potential (or input voltage), H level output potential (or output voltage), and H level noise margin” of the binary circuit and “L level input potential (or This can be easily understood by considering the relationship between the input voltage), the L-level output potential (or output voltage), and the L-level noise margin. In the positive logic of the binary circuit, substantially each lower limit value of the input potential and output potential of the H level is the input side logic level of numerical value 1 and each negative side threshold potential of the output side logic level, “L level input potential, upper limit value of output potential is each input side logic level of numerical value 0, each positive side threshold potential of output side logic level”.
In the case of a CMOS inverter circuit, for example, in the case of a CMOS inverter circuit, what is normally called "threshold potential (or voltage)" in a binary circuit is "a boundary where the operation state of PMOS and NMOS is inverted", or "circuit threshold potential (or Voltage). Then, there is an on / off threshold voltage of the semiconductor element.

“Introduction to logic circuits”, “(1) Signal voltage value and noise margin” on page 126-128. Author: Ryuji Hamabe, published by Morikita Publishing Co., Ltd., September 28, 2001. "Well-understood digital electronic circuits", "[1] Logic level ~ [2] Noise margin" on pages 76-80. Author: Sekine Keitaro, Inc. Ohm company published on July 25, 1997. “Introduction course 5: Concept of digital circuit”, “4.6 Notes on using logic circuit [1] Logic voltage level and noise margin” on page 46-47. Supervision: Yoshifumi Amamiya, Norii Kojima (Tsuneori). Author: Kenshi Shimizu (Masaru). Published by Ohm Co., Ltd. May 20, 1982. Pulse Digital Circuit, Amplitude Characteristics of 5.1 Pulse Digital Circuit, page 125-130. Author: Kawamata Minoru. Published by Nikkan Kogyo Shimbun Inc. on February 15, 1995. “Pulse and Digital Circuits”, “Threshold Level” on page 128 and “Logical Level” on page 129. Editor: Masao Yoneyama. Writing: Ohara Shigeyuki, Yoshikawa (Kikikawa) Sumio, Shibasaki Toshio, Takahashi Shiro. Published by Tokai University Press on April 5, 2001. “Introduction to practical use series CMOS circuit usage [1]”, “element threshold voltage” on page 44 and “circuit threshold voltage” on page 50. Author: Suzuki Eighty Two (Yasoji). Published by October 15, 1997, the Industrial Research Association.

Then, the "multi-level logic circuit based on the first invention of the prior application" is an implementation or realization of a new multi-level logic "fuge algebra". In the case of this multi-level logic circuit, "the circuit [Means on the preceding stage side (eg, said numerical value discrimination means or said ON state in three stages of the circuit part during the internal signal transmission (eg: said numerical value discrimination means, said ON / OFF drive means and said pull switching means) · Connectivity between the output side of the off drive means and the binary circuit] and [Input side of the means on the subsequent stage side (eg, the on / off drive means or the pull switching means) and binary values Connectivity between circuits], and there are no special interfaces (eg binary / multi-level code converter, multi-level / binary code converter) between the two. There is a feature. (Unique effects and features of the multilevel logic circuit based on the first invention of the prior application)
The reason is as follows. The signal during transmission in the circuit is "on the output side of the numerical value determination means and the on / off drive means" Affirmative or negative [the said determination result signal and its on / off drive signal] ", that is, a binary signal Such as “High / Low signal” and “on the input side of the on / off driving means and the pull switching means“ the output for a specific integer for the output (during on driving) and the output open (off Since the [on / off signal and the on / off drive signal] corresponding to the driving time], that is, a binary signal, high / low signal, etc., the signal transfer midway portion in the multilevel logic circuit is The compatibility with the binary circuit is very good.

However, "if the determination result signal and the on / off drive signal (both like binary signals, high and low signals)" are the same as "the same H level and L level of a normal binary signal" Although there are cases of "temporary binary signal" like H level and L level "but different from ordinary binary signal" H level and L level "", "generally The "temporary" binary signals are different from each other only in "the height of the potential level" or "the magnitude of the amplitude at the time of level change".
For example, if the magnitude of each power supply voltage is different as in TTL and CMOS even in a binary circuit, “the height of the H level potential (or voltage)” and “the size of the amplitude when the level changes” also differ. In the positive logic, even if the potential level is different, the H level is still at the H level, and the numerical value 1 is also the numerical value 1.
On the other hand, when dealing with the H level and L level of the “normal or temporary” binary signal in the multilevel circuit, “three or more constant potentials corresponding one to one with their respective integers” or Among the added constant potentials {example: power supply potential v ₋₁ of power supply line V _{−1 in} FIG. 73 } not included in these, it will be selected which two constant potentials are to be used, From the whole multi-value circuit, "the height of each constant potential corresponding to the H level and L level" and "the level change according to" which two constant potentials should be selected and used as the power supply for the binary circuit " The magnitude of the amplitude of the hour is different.
If the heights of the constant potentials corresponding to the H level and the L level are different, the respective numerical values corresponding to each other in the multilevel circuit are also different. For example, "2 numbers corresponding to H level and L level" become "9 and 0", "8 and 5", "3 and 1", etc., and they are not usually "1 and 0" of the binary circuit. There are many cases. The reason is that the multi-valued circuit is considered as the center and reference, and each constant potential and each of the constant potentials in the first part of the "means for solving the problems" of the first application of the prior application (→ paragraph number [ 0186 ]) Because it defines an integer relationship. Or, in the case of the "whole another added constant potential", the corresponding integer itself is not defined.
However, in general, a positive logic binary circuit is originally considered to be at the center or reference, and "it determines that the input potential signal higher than the lower limit value of its own is at the H level, while its own L level It has a function of “determining an input potential signal lower than the upper limit value as L level”. The first application of the prior application utilizes this discrimination function effectively in the multilevel circuit. For this reason, the binary synchronous flip flop means has a (voltage) matching function (for example, a voltage dividing function by a voltage dividing resistor connected to its input portion) if necessary in addition to its discrimination function. And the above-mentioned provisional binary signal can be converted into a usual binary signal. The necessity of the matching is due to the withstand voltage of the input portion of the binary synchronous flip flop means.
Alternatively, potential (or voltage) clamping means (for example, two clamp diodes etc.) at the input of the binary synchronous flip flop means may have an upper limit of the provisional binary signal. While clamping to the positive side constant potential of the binary circuit power supply, clamping the lower end of the provisional binary signal to the negative side constant potential of the binary circuit power supply, the provisional binary signal is normally Can be converted into binary signals. The first application of the prior application also makes effective use of this conversion function in a multilevel circuit. In this case, by having (impedance) matching function of a kind necessary (eg. Insertion connection of the power supply circuit preventing resistor the resistance 28. in Figure 1) the output of the preceding stage via the clamping means Prevent power supply short circuit.
The above is also true for a general negative logic binary circuit.

As described above, although the correspondence between the logical values is always taken into consideration, the binary circuit and the multi-valued circuit are slightly complicated. However, if considered only with a pure electronic circuit, the above story is a matter of course So easy to grasp.
The synchronization signal supply means supplies "a synchronization signal usable by the binary synchronous flip flop means" for the synchronous signal of the binary synchronous flip flop means, but if necessary, the synchronization may be performed. The signal supply means has each matching function described above, or utilizes the discrimination function of the binary circuit described above or the “conversion function by clamp”.
In addition, if the output current capacity of the binary synchronous flip flop means is sufficiently large, the binary synchronous flip flop means satisfies the requirements of the on / off driving means, the binary synchronous type Of course, the flip flop means may double as the on / off driving means.

■ ■ "Means for solving the problems" of the second application invention ■ ■ ■
In the "means for solving the problems", that is, the "multi-level logic means having a synchronous latching function" of the first invention described above (paragraph numbers 0186 to 0188 ),
The binary synchronous flip-flop means “as it is or matches the detection result signal as a holding signal during the“ period in which no hazard appears in the determination result signal and the determination result signal is stable ”based on the synchronization signal. Means for removing multi-level hazards.

By this, since the conventional binary hazard removal method can be utilized for "the binary multi-level hazard appearing in the discrimination result signal", the multi-level hazard can be removed. (effect)
The reason is as follows. Even if a certain multilevel signal is input to the multilevel logic circuit, it can be handled like a binary signal as described above (Paragraphs 0195 to 0196 ) during signal transmission in that circuit. Even if multi-level hazards occur before or at the time of input, the multi-level signal can be handled like a binary signal including binary hazards during signal transmission. Binary hazard removal circuits and methods can be utilized during their signal transmission.
In addition, since the period in which the multi-level hazard appears can be grasped in advance in the circuit design stage or the operation check stage, etc., the multi-level hazard appearance timing and the timing of the synchronization signal (or clock pulse signal etc.) It can be adjusted. For this reason, the binary synchronous flip-flop means ignores the discrimination result signal based on the synchronization signal during the "period in which the binary hazard appears in the discrimination result signal" and holds the signal until then (or Keep holding data).
On the other hand, the binary synchronous flip-flop means incorporates the discrimination result signal based on the synchronization signal during the "period in which the binary hazard does not appear in the discrimination result signal and the discrimination result signal is stabilized". , And holds the new hold signal (or new hold data), and drives the on / off as the on / off signal “positive output signal or complementary output signal” based on the new hold signal (or held data) Output to means.
Similarly, the binary synchronous flip flop means rewrites the hold signal (or hold data) based on the synchronization signal, and outputs a positive output signal or a complement output based on the hold signal (or hold data). Since the signal is outputted, the binary synchronous flip flop means "binary signal obtained by removing the binary hazard from the binary signal in the process of transmission" is used as the on / off driving means of the latter stage. Can be supplied. As described above, the multilevel hazard removal means (= multilevel logic means having the multilevel hazard removal function) of the second application of the prior application converts the multilevel hazard into a binary hazard during signal transmission, It can be removed by applying a conventional binary hazard removal method. As a result, only the real "signal, data or information" portion can be extracted from the "multi-level signal including multi-level hazard".
By the way, in the case of most conventional multilevel logic circuits, such a multilevel hazard elimination method in which a binary circuit (eg, flip flop etc.) is provided in the middle of signal transmission can not be applied. This is because, in most cases, the signal during signal transmission is also a complete multilevel signal.

Then, since the binary synchronous flip flop means is immediately after "the numerical value discriminating means as one source of multivalued hazards of multilevel", the binary synchronous flip flop means is Since the multi-value hazard generated by the numerical value determination means is immediately cut off, the multi-value hazard is not propagated to the on / off drive means or the pull / switching means in the multi-value logic means and in the subsequent stage. .
As a result, "the range in the multi-level logic means affected by the generated multi-level hazard" is limited to only the numerical value determining means, so "within the multi-level logic means affected by the generated multi-level hazard" You can narrow the range of

効 効 効 発 願 効 効 効 効 効
■ ■ ■ ■ effect of the first application first invention ■ ■
The effects of the first application of the prior application are summarized as follows.
1) Since the binary synchronous flip flop means can be built in between the numerical value discriminating means and the on / off driving means, each binary trigger system (eg, each edge of plus or minus)・ Trigger, level trigger, pulse trigger) can be used as it is. (First effect)
In particular, the step-like multilevel synchronization signal (the waveform of FIG. 4 of JP-A-2006-345468. There are a plurality of rising portions or falling portions or horizontal portions) which the present inventor considered is used more effectively. Since the trigger timing options can be increased during one cycle of the synchronization signal, it becomes very convenient. The reason is that there are a plurality of “rising point or falling point or horizontal portion” depending on which two constant potential supply means (for example, two power supply lines) are connected between the binary synchronous flip flop means. Because you can choose one.
If the output current capacity of the binary synchronous flip flop means is large and the binary synchronous flip flop means satisfies the requirements of the on / off driving means, the binary synchronous flip flop means Of course, the flop means may double as the on / off driving means.
2) The binary synchronous flip-flop means only latches either "signal state corresponding to a specific integer for output of the multi-valued logic means" or "signal state corresponding to output open or open output" Naturally, "signal state corresponding to output open or open output" can be latched. (Second effect)
◆ 3) Since there is no latching function for each value (= each integer other than the output value (= output specific integer)), it has a latching function corresponding to the “output value”, There is no waste. (Third effect)
→ → There are no unnecessary parts and no unnecessary components, so parts and circuits can be used efficiently and power consumption can be saved.
◆ 4) Multi-value circuit to be used {Example: multi-value logic circuit, multi-value operation circuit (or multi-adic operation circuit), multi-value digital circuit, etc. According to the configuration of}, there are more options for multi-level synchronous latching means connected to the subsequent stage, which is convenient. Flexibility occurs in the overall circuit configuration.
(4th effect)
→ → → In the case of multi-valued logic circuit based on “Fuge algebra”, the specific integer for input by the constant potential supply means (eg power supply line, power supply plate etc.) connected by the numerical value judgment means and pull / switching means respectively In addition to being able to easily change both of the output specific integers, it is possible to select a circuit to be used from among various kinds of multilevel logic circuits (eg, AND circuit, OR circuit, OVER circuit, UNDER circuit, etc.). In the first application of the first application, each multi-level logic circuit is provided with a synchronous latching function, so eventually the number of options for the multi-level synchronous latching means increases.
→ → The various multi-level logic circuits are called, for example, “(multi-level) AND circuit, (multi-level) OR circuit, OVER circuit, EVEN circuit, UNDER circuit, IN circuit, OUT circuit, etc.” by the inventor. There is a circuit.
◆ 5) “Which part of the entire circuit should be latched?” With more options for latching, it becomes convenient. Flexibility occurs in the overall circuit configuration. (Fifth effect)
→ → → Since the multi-value logic means of the first application of the invention · itself has a synchronous latching function, the option “it is not necessary to provide the multi-value synchronous latching means between the multi-value circuit and the multi-value circuit” Is added.

■ ■ ■ effect of the prior application second invention ■ ■
The effects of the second application of the prior application are summarized as follows.
In addition to multi-level hazards that occur in the same manner as binary hazards, multi-level intrinsic multi-level hazards can also be removed. (First effect)
→ → Only the true "signal, data or information" part can be extracted from the "multi-level signal including multi-level hazard".
In addition, the range in the circuit affected by the generated multilevel hazard can be narrowed as little as possible. (Second effect)
These effects lead to the reduction of multi-level hazard noise and the reduction of power loss.

形態 形態 形態 形態 形態 形態 形態 形態 ◇ 形態 形態 形態 形態 形態
In order to explain the first and second inventions in more detail, they will be described below according to the attached drawings. In addition, the following seven notes are described first.
1) The following explanation includes "explanation from the viewpoint of electronic circuit" and "explanation from the viewpoint of logic and mathematics", and there is also a description in which both are mixed.
{Circle around (2)} Each embodiment in the case where these constant potentials “go up” in numerical order from the first constant potential to the Nth constant potential will be mainly described.
On the other hand, regarding each embodiment in the case where these constant potentials "go down", each power supply potential (corresponding to each of these constant potentials in "the embodiments to be described or their respective derivative embodiments"). With each controllable switching means being replaced by “controllable switching means complementary to it (eg P-channel MOS • FET for N-channel MOS • FET)”, and the voltage direction or This corresponds to “an embodiment having a symmetrical relationship with respect to the voltage direction or the voltage polarity with respect to the original embodiment” in which the direction of each component (for example, the diode) having the voltage polarity is reversed. However, in that case, the multi-level logic function may be the same as or different from the original circuit.
{Circle over (3)} n in each embodiment corresponds to the above N (predetermined plurality).
◆ 4) The integer m corresponds to a specific integer for output, and corresponds to “a specific constant for output of the specific constant potential supply means for output (example: power supply line V _m ) described above (example: specific power supply potential v _m )” Is an integer. There is a relationship of "n-1 ≧ m」 0 ".

◆ 5) Each of “V _G , V _H , V _m , V ₋₁ , V ₀ , V _{1 to} V _{n −1} , V _n ”, etc. represented by capital letter V is a power supply line, represented by small letter v etc. “V _G , v _H , v _m , v ₋₁ , v ₀ , v _{1 to} v _{n −1} , v _n ” etc. represent the potentials of the power supply lines (= constant potentials) in sequence The power supply potentials of v _{−1 to} v _n increase in this order. In addition, of course, the power supply line V ₀ or other power line is "the main body case of the circuit" or "body of the circuit device" or "the hull of the ship, or the like" or "automobile, motorcycle, car body, such as a bicycle," or "land and water Dual-purpose main body such as hovercraft, or "main body of flight means such as airplane or helicopter" or "main body of space navigation means such as spacecraft or space station / space floating means" or "stellar bodies such as earth, moon, Mars The potential of the main body, the vehicle body, the hull and the celestial body becomes the reference potential such as the ground potential.
However, although one DC power supply for DC voltage supply is connected between each of “two power supply lines adjacent to each other at the level of the power supply potential”, they are not illustrated.
◆ 6) For example, diodes 10, 12, 35, 36, “Zener diode pair in which two Zener diodes are connected in series in the reverse direction”, dotted line “connection of circuit configuration means itself or connection of circuit configuration means” In the case of showing it, it means that there is "the case with or without the connection or insertion / connection".
◆ 7) “Each gate terminal is connected to the Q terminal (positive output terminal) of the D-type flip flop 27 or the gate terminals or common gate terminals of the transistors 41, 47, 48 are drawn two by two. , Q bar terminals (complementary output terminals) are shown by dotted lines.
As a matter of course, "change the connection from Q terminal to Q bar terminal" and "change the connection from Q terminal Q to Q terminal""do the circuit after the connection change to the circuit before the connection change" It means that "it becomes a negative circuit".
As a precaution, "Q bar" means a letter drawn above the letter Q.

先 ◆ Prior application / example 1 of Fig. 59 ◆ ◇
In the prior application / example 1 (multi-level logic means having synchronous latching function and multi-level hazard removal means) of FIG. 59 , the respective constituent means are described above (paragraph numbers [ 0186 to 0188 ]) as follows. In S = 1, there is a relationship of “n「 3 ”and“ n−1 ≧ m ≧ 0 ”. Since the one output specific integer m doubles as the one input specific integer m, the output specific power supply potential v _m doubles as the input specific constant potential (→ paragraph number [ 0187 ]).
However, as described above (the last nine lines of paragraph number [ 0189 ]), “determining whether or not the one input integer is equal to the one input specific integer m” is “the one input integer Is the same as “determining whether or not there is between the two input specific integers (m−1) and (m + 1). Further, when n> m + 1, the power supply line V _{n and the} like are not shown.
A) The power supply potential v ₀ to the power supply potential v _n-1 are the first to Nth constant potentials described above (paragraph numbers [ 0186 to 0188 ]).
B) The power supply line V ₀ to the power supply line V _n-1 are the first constant potential supply means to the Nth constant potential supply means described above.
However, further or there is a power supply line _{V -1} supply potential _{v -1} under the power potential _{v 0,} or there is a further power supply line _{V n} of the power supply potential _{v n} on the power potential _{v n-1} There are also cases where you Further, not illustrated only power supply line part in Figure 59.
◆ c) the inlet means of the first input terminal _{T in} is the aforementioned (S = 1).
D) The output terminal _Tout is the exit means described above.
◆ e) output power supply line V _m is the aforementioned specified constant potential supply means (= input certain constant potential supply means).
F) The specified power supply potential v _m is “the specified constant potential for input described above” and “the specified constant potential for output supplied by the specified constant potential supply means for the output”.
G) The series circuit of the transistors 3 and 4 is the above (bidirectional) pull switching means. ☆ Reference: Japanese Patent Laid-Open No. 2005-236985 (Patent Document 3)
H) "The circuit section formed by the transistors 1, 2, 17, the diode 35 and the resistors 20, 21" is the numerical value determination means described above.
◆ i) “The circuit section formed by the transistors 41 and 37, the diode 39 and the resistor 15” is the on / off driving means described above.
J) D-type flip flop 27 is the binary synchronous flip flop means described above.
◆ k) The circuit portion formed by the synchronization signal generation means 60, the transistor 61 and the resistors 26, 28 is the above-mentioned synchronization signal supply means.

If “D-type flip flop 27, sync signal generating means 60, transistor 61 and resistors 26, 28” are removed and the gate of transistor 41 is directly connected to the anode of diode 35, then {{power supply line V ₋₁ , Power supply line V ₀ to power supply line V _n-1 {, power supply line V _n }, transistors 1, 2, 3, 4, 17, 37, 41, diodes 35, 39 and resistors 15, 20, 21 etc. (DC The power supply is not shown.) Is a multi-valued logic circuit based on the "Fuji Algebra" described above.
The gate of the transistor 41 is connected to the Q terminal (positive output terminal) of the D-type flip flop 27. However, the gate of the transistor 41 may of course be connected to the Q bar terminal (complementary output terminal).
Furthermore, the transistor can be changed by simultaneously changing only the portions of the power supply lines V _{m-1 to} V _{m + 1} to which the transistors 1, 2, 17, 41 and the D-type flip flop 27 etc are connected simultaneously to the same high potential. If the source of 41 is changed to the power supply line V _{m + 2} or “arbitrary power supply line higher than this”, a resistor or “two zener diodes are connected in series in reverse direction for voltage drop instead of the diode 39 You can use In this case, the transistor 37 may be a normally on type (depletion mode).
Then, D-type sync signal input of the flip-flop 27 "identify the lower limit of the potential of the CP terminal power supply potential v clamping diode for clamping the _m (not shown.)" It is connected and the particular power supply potential v when _m is higher than the power supply potential v _0, the clamp diode and a transistor 61 a resistor 28 to a short circuit between two power supply lines V _m · V ₀ is prevented. When the specific power supply potential v _m = power supply potential v ₀ , the resistance value of the resistor 28 may be zero.
And, of course, one DC power supply means (not shown) is connected between each of the "two power supply lines adjacent to each other at the level of the power supply potential".

As described above, the specific integer for output (= integer corresponding to the specific constant for output) m also serves as the specific integer for input (value), and the power supply line _Vm is for supplying the specific constant potential for input and the specific constant potential for output The specific power supply potential v _m serves as both a means and a specific constant potential for input and a specific constant potential for output.
"Input voltage v _{in (=} the potential of the input terminal T _in)", the relationship "the logic level of the threshold potential of the input specific integer m" and "input numerical value N _in corresponding to the input voltage v _in" following It is street.
◆ 1) When specific integer m = 0:
If the input potential v _in is lower than the positive side threshold potential with respect to the power supply potential v ₀ , the input numerical value N _in is determined to be an integer 0, and the input potential v _in is “one more than the power supply potential v ₀ If it is higher than the negative threshold potential based on the power supply potential v ₁ ", it is determined that the input numerical value N _in is not the integer 0.
◆ 2) When the specific integer m is "n-2 m m 1 1":
If the input potential v _in is "between the positive side threshold potential and the negative side threshold potential with reference to the specific power supply potential v _m ", the input numerical value N _in is determined to be an integer m, and the input potential v _in the "" specific power supply potential v power supply potential on the one than _m v _{m + 1} "higher than the negative threshold voltage relative to the" or "" specific power supply potential v below one than _m power supply potential v _{m- In the} case where it is lower than the plus side threshold potential based on ₁ ′ ′, it is determined that the input numerical value N _in is not an integer m.
◆ 3) When specific integer m = (n-1):
Is higher than the minus side threshold potential input potential _{v in} is the power supply potential _{v n-1} to the reference, the input numerical value _{N in} is determined that the integer (n-1), the input potential _{v in} the "power supply potential _{v n} If it is lower than the plus side threshold potential based on the power supply potential v _n-2 "one less than _-1, it is determined that the input numerical value is not an integer (n-1).
Note that while the negative side threshold potential of the input side logic level of the specific integer m is usually taken into consideration of the specific power supply potential v _m , the “specific power supply potential v _m and the“ specific power supply potential v while being set between the middle potential "of one power supply potential v _m-1 of below" _m, the plus side threshold potential of the input side logical level of a particular integer m is from "" specific power supply potential v _m 1 One power supply potential v _{m + 1} "on the middle potential" of a particular power supply potential v _m is set during a particular power supply potential v _m.
Of course, although each noise margin (degree) is taken into consideration, it is not necessary to be such a setting like “each threshold potential of binary TTL without vertical symmetry”, and it may be a setting that is offset.

First, an explanation of the operation of the original asynchronous / multilevel logic circuit
“The prior application in FIG. 59 does not have insertion and connection of the D-type flip flop 27 in the first embodiment, and the gate of the transistor 41 is directly connected to the anode of the diode 35. The logic operation of the “multi-level logic circuit (Reference: the first in paragraph 0206 )” is as follows.
Input numerical value _{N in} the input terminal _{T in} the transistor 1,2,17,37 is turned on when a particular integral m, since the transistor 41,3,4 is turned off, the output from the output terminal _{T out} is opened . On the other hand, "On the other hand either 1, 2," when the transistor input numerical value _{N in} the other than the specific integer m, 17,37 is turned off, in order to transistor 41,3,4 is turned on, the potential of the output terminal _{T out} becomes the specific supply potential v _m, the specific integer m is output. For this reason, the inventor refers to this asynchronous type / multilevel logic circuit as a "(asynchronous type) / multilevel (specific value) NOT (= knot) circuit".
Therefore, when the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27 in the prior application, the first embodiment of FIG. 59, the present inventor has a prior application, the first embodiment of FIG. 59, "Synchronous • It is called “multi-value (specific value) NOT circuit”.
However, the asynchronous-multivalued logic "binary NOT circuit took its power from both the power supply line V _{m + 1 ·} V _m (not shown.)" In reverse the drain signal of the transistor 17 via the transistor Since the on / off operations of the transistors 41, 3 and 4 are also opposite if input to the gate of 41, in this case, the inventor of the present invention (Specific value) This is called an EQUAL (= equal) circuit. Alternatively, since there are "each circuit which the inventor has already called an asynchronous type (multi-level specific value) OVER (= over) circuit or an asynchronous type (multi-level specific value) UNDER (= under) circuit", their names The present inventor calls "asynchronous type (multi-level specific value) EVEN (= even) circuit" uniformly in golf terms. In this case, the negation circuit may be called "asynchronous (multivalued specific value) NEVEN (= even) circuit" instead of "asynchronous type · multivalued (specific value) NOT (= knot) circuit".
Thus, "synchronous EQUAL circuit prior application, the first embodiment of FIG. 59 when the gate of the transistor 41 is connected to the Q bar terminal of the D-type flip-flop 27 in the prior application, the first embodiment of FIG. 59, or , Called a synchronous EVEN circuit.
Incidentally, the specific power supply potential v _m that satisfies "n-1 ≧ m ≧ 0" corresponds to a specific output integer m, the pull-open output of the output terminal T _out in which the power supply potential, for example, "the output terminal T _out up or pull-down or "or" is either "or the like for connecting the output terminal T _out and the output terminal T _out of another similar multivalued logic circuit, the output terminal Tout in any case the" multi-level The corresponding constant potential can be output.

■ To synchronous type ・ multi-level logic circuit ■
The functions of the prior application and the first embodiment of FIG. 59 are as follows. "Drain output signal of the transistor 17 'is also a signal such as a binary circuit for a power supply also substantially both the power supply line V _{m + 1 ·} V _m voltage" gate input signal of the transistor 41'.
Therefore, as described above (paragraph number 0195 to 0196 ), the multi-valued logic circuit based on the "Fuge algebra" has very good connectivity with the binary circuit in the middle of signal transmission in that circuit. There is a unique effect that there is no need for an interface (eg, binary / multi-level code conversion means, multi-level / binary code conversion means).
(Unique effects of multi-valued logic circuits based on that "Fuji algebra")
Also, the combination of the resistors 26, 28 and "means such as binary / numerical discrimination means at the CP input of the D-type flip flop 27 or two clamp diodes" inherently has the function of "consider or convert". There is. The "think or convert" function is to swing "a high / low signal such as a binary signal swinging between power supply potential v ₀ and power supply potential v _{m + 1"} between "specific power supply potential v _m and power supply potential v _{m + 1"} It is a function that can be easily regarded as "ordinary binary signal" or can be easily converted to the ordinary binary signal.
However, High / Low signals such as binary signals can be regarded as multilevel signals depending on numerical interpretation. → → Paragraph number [ 0196 ] The first half.
The "see or convert" function is always "H (multi-value) potential signal or (multi-value) voltage signal" which is higher than the lower limit value of the H level of "general binary circuit is always" H Binary circuit that is determined to be level, and all “(multi-level) potential signals or (multi-level) voltage signals” lower than the upper limit value of that L level to be always “L level” It is due to. Alternatively, it is caused by the binary circuit / specific operation characteristic of “determining whether rising from L level to H level or falling from H level to L level”.

Alternatively, its “see or convert” function is based on “the upper limit of“ (multi-level) potential signal or (multi-level) voltage signal ”“ the two clamp diodes at the input of a general binary circuit ”. In the operation characteristics of a binary circuit, “clamping to the positive side constant potential (or positive side power supply voltage) v _{m + 1} while clamping the lower limit thereof to the binary negative side constant potential (or negative side power supply voltage) v _m It is due.
In the case of the prior application / example 1 shown in FIG. 59 , the CP terminal / input portion of the D-type flip flop 27 is used as “the numerical value determination portion or input portion of the binary circuit”. The same applies to the 27 D terminals and input units. In other words, the data input unit (for example, the input unit of the D terminal) of the binary synchronous flip flop means which is one of the constituent means with respect to the first and second inventions If the requirements of the numerical value discrimination means for discriminating "large or large or not" or "small or small" than a specific integer are satisfied, even if the binary synchronous flip flop means doubles as the numerical value discrimination means Of course I do not mind.
For prior application, the first embodiment of FIG. 59, both the power supply line as the power is supplied from the power supply line V _{m + 1} and the power source line V _m of the binary circuit (= D-type flip-flop 27) is selected ing.

Furthermore, multi-valued logic circuits based on the new multi-valued logic "Hooji algebra" have very unique effects and features. It is also very good that “connectivity with the previous stage binary circuit” and “connectivity with the binary circuit in the middle of signal transmission in the multilevel logic circuit” and “connectivity with the latter stage binary circuit” Regardless, regardless of the multi-level number N, all multi-level logic functions can be represented by one type or a combination of a plurality of basic multi-level logic circuits (complete system).完全 性 Integrity It is also "complete".
Reference: Non-Patent Document 9, "Multi-value information processing-post binary electronics-").
The proof of "completeness" of "Hooji algebra" has already been described in paragraph numbers [ 0134 to 0147 ].
For this reason, a multilevel signal is input to the one type of multilevel logic circuit, and is handled as a binary ( target ) signal as described above (paragraph number [ 0195 to 0196 ]) during signal transmission in the circuit. be able to. Even if a multi-level hazard occurs before or during the input, it can be treated as a binary (target) signal including a binary (target) hazard during the signal transmission, so the conventional binary Hazard removal circuits and methods can be utilized during their signal transmission.
Then, since the period in which the multi-level hazard appears can be predicted or understood in advance in the circuit design stage or the operation check stage, the appearance timing of the multi-level hazard and the “synchronization signal (or clock pulse signal etc. input to the transistor 61) The timing of “can be rubbed together.
For example, during the period during which the binary hazard appears in the drain output signal of the transistor 17, the D-type flip flop 27 has its drain, since the input synchronization signal of the transistor 61 is set low or high. Ignore the output signal and keep holding the previous hold signal (or hold data).
On the other hand, since the input synchronization signal of the transistor 61 is set to fall during a period in which the binary hazard does not appear in the drain output signal of the transistor 17 and the drain output signal is stabilized, the D-type flip flop 27 takes in its drain output signal, holds it as a new hold signal (or hold data), and outputs it to the transistor 41 as it is.
Similarly, the D-type flip flop 27 "rewrites its hold signal (or hold data)" based on the output synchronization signal of the transistor 61 and "holds the new / hold signal (or new / hold data). Since the output is carried out, the D-type flip flop 27 is driven by the on / off driving means of the subsequent stage to the binary signal obtained by removing the binary hazard from the binary signal on the way thereof. It can be supplied to (transistors 41, 37 etc.).
As described above, since the prior art and the first embodiment of FIG. 59 can treat multilevel hazards as binary hazards during signal transmission, the prior binary hazard removal circuit and method are applied. It can be removed.

■ Operation explanation of synchronous type / multi-level logic circuit ■
When the gate of the transistor 41 is connected to the Q terminal of the D-type flip-flop 27 in the prior application, the first embodiment of FIG. 59, the present inventors the prior application, the first embodiment of FIG. 59 is "synchronous Neven ( It is called "even circuit" or "synchronous NOT circuit". The circuit operation is as follows.
The “synchronizing signal supply means consisting of the synchronizing signal generating means 60, the transistor 61 and the resistors 26, 28” supplies the synchronizing signal to the Q terminal of the D-type flip flop 27, but based on this synchronization signal The flop 27 takes the discrimination result signal from the transistor 17.
If shows a positive output signal of the intake discrimination result signal, that Q terminals may "input terminal T _in the input integer N _in the is an integer equal to the integer m", "on the transistor 41,37, etc. to form Since the off drive means drives off the transistors 3 and 4, the output from the output terminal T _out is opened.
However, if the positive output signal indicates that this is not the case, the on / off drive means drives the transistors 3 and 4 on, and the specific power supply potential v _m is output from the output terminal T _out in a circuit. , Logically, the output specific integer m is output.
Thereafter, the output state continues until the D-type flip flop 27 takes the next discrimination result signal from the transistor 17 based on the synchronization signal. Thereafter, similarly, the next discrimination result signal is taken, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q bar terminal of the D-type flip-flop 27 in the prior application, the first embodiment of FIG. 59, the present inventors the prior application, the first embodiment of FIG. 59, "Synchronization Type EVEN circuit "or" synchronous EQUAL circuit ".
Since this circuit operation is a negative operation of the above-mentioned "synchronous NEVEN circuit", only the way of the output from the output terminal T _out is opposite.

● In place of the D-type flip flop 27, one stage or a combination of “a binary 3-state buffer modified to be conductive / nonconductive with edge trigger” and “a binary memory means after that” It is also possible to use “two stages connected to the former stage and the latter stage” (→→ substantially a binary flip flop means). (Derivative embodiment)
● In addition, since there are three types of trigger methods below, the binary synchronous flip flop means and the binary three-state buffer means operate based on their synchronization signals (or clock pulse signals etc.) It is also possible to change to another trigger method. (Derivative embodiment)
B) Level trigger method b) Each edge trigger method of plus and minus c) Pulse trigger method (= master slave method)
Further, by re-connecting the drain of the transistor 3 from the power supply line V _m to any _one of the other power supply lines V _{0 to} V _{m -1,} a specific integer for the output from m to 0 (m -1) Can be changed to any one.
These things (the above combination, the above each trigger system, and the above-mentioned change of connection of the power supply line) are the same as in the other embodiments.
P. 79 to p. 88. Japan Riko Publishing Co., Ltd. published the fourth edition on April 25, 2008. Author: Nakamura Tsugio. Reference: Each trigger method.

◆ ◆ Prior application · Example 2 ◆ ◇
The prior application and embodiment 2 shown in FIG. 60 are derived from the prior application and embodiment 1 of FIG. 59 or their derivatives. As described above (line 6 to line 10 of paragraph number [ 0205 ]), “determining whether or not the one input integer N _in is equal to or not the specific integer for the one input” is “the one It is the same as “determining whether the input integer N _in is between the two input specific integers (m−1) and (m + 1) or not.
Then, although the prior application, the first embodiment of FIG. 59 is a case where the number of integers in between certain integer two for that input is one, the previous application, the second embodiment of FIG. 60 that the number is two That's the case. For this reason, “whether one input integer N _in is an integer that is between two of the input specific integers (== is equal to either) or is not any of them (== all is equal to either) It can be rephrased that “the prior application / example 2 of FIG. 60 determines”.
Prior application, the embodiment of FIG. 60 2 "in the prior application, Example 1 or each derivative embodiment thereof in FIG. 59 as" back gate of the source and the back gate and the transistor 17 of the transistor 1 "to connect the power supply line V _{m + 1} Once separated, the source or the like is "connected to any one power supply line V _H of the power supply line V _{m + 2} to the power supply line V _{n -1} ". That is, m + 2 ≦ H ≦ n−1.
However, if there is a "built-in clamp diode whose one end is connected to the power supply line V _{m + 1} " at the D terminal, the power supply short circuit resistance between the drain of the transistor 17 and "the connection point of the resistor 21 and the D terminal" Need to be inserted and connected. (A type of matching)
As a result, in the case of the NIN circuit and the IN circuit described below, the two specific integers for input in the prior application example 2 are integers (m-1) and "numbers of the power supply lines reconnected, that is, Among m + 2) to (n-1), one integer H corresponding to the power supply line is obtained. Details of this will be described later (paragraph numbers [ 0219 to 0223 ]).
Note that by connecting the drain of the transistor 3 from the power supply line V _m to any _one of the other power supply lines V _{0 to} V _{m -1} , the output specific integer can be set from m to 0 to (m-1) It can be changed to any one.

When the gate of the transistor 41 is connected to the Q terminal of the D-type flip flop 27 in the prior application and the second embodiment of FIG. 60, the inventor of the prior application and the second embodiment ) NOBETWEEN (= no bitten. BETWEEN not negative.) Circuit ”or“ unified in golf terminology, “synchronous (multi-value specific value) NIN (= Nin. IN not negative.) Circuit” or “synchronous (multiple) Value specific value) OUT (= out) circuit] Of course, removing the D-type flip flop 27 etc. in these circuits and connecting the gate of the transistor 41 directly to the anode of the diode 35 will make these circuits asynchronous.
However, in this case, two specific integers of the IN circuit and the NIN circuit are (m-1) and H, while two specific integers of the OUT circuit are m and (H-1). These things will be explained in detail later.
The circuit operation is as follows. The “synchronizing signal supply means constituted by the synchronizing signal generating means 60, the transistor 61 and the resistors 26, 28” supplies the synchronizing signal to the CP terminal of the D-type flip flop 27, but based on this synchronizing signal The flop 27 takes the discrimination result signal from the transistor 17.
Long as the positive output signal of the intake discrimination result signal, i.e. Q terminal indicates that the "input integer N _in the input terminal T _in is an integer there between the integer H integer (m-1)", " Since the on / off drive means formed by the transistors 41, 37 etc. drives the transistors 3, 4 off, the output from the output terminal T _out is released.
However, if the positive output signal indicates that this is not the case, the on / off drive means drives the transistors 3 and 4 on, and the specific power supply potential v _m is output from the output terminal T _out in a circuit. , Logically, the output specific integer m is output.
Thereafter, the output state continues until the D-type flip flop 27 takes the next discrimination result signal from the transistor 17 based on the synchronization signal. Thereafter, similarly, the next discrimination result signal is taken, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q-bar terminal of the D-type flip flop 27 in the prior application and the second embodiment, the inventor of the prior application and the second embodiment ) BETWEEN (= bi-tween) circuit "or" unified in golf terminology, "synchronous (multi-value specific value) IN circuit" or "synchronous (multi-value specific value) NOUT (= nauto. OUT not negated) circuit" I call it ".
Since this circuit operation is a negative operation of the above-mentioned "synchronous NIN circuit", only the way of the output from the output terminal T _out is opposite.

Of course, in these synchronous "IN, NOUT" circuits, the D-type flip flop 27 etc. are removed, and the power is taken from both power supply lines V _{m + 1} · V _m between the gate of the transistor 41 and the anode of the diode 35 By connecting the value inverter circuit to invert the drain signal of the transistor 17, these circuits become an asynchronous "IN, NOUT" circuit.
However, in the case of the synchronous OUT circuit and the synchronous NOUT circuit, the two specific integers for input are the integer m and “the number of the power supply line re-connected, that is, [integers (m + 2) to (n-1) , One integer H] '' corresponding to the power supply line minus one (H-1) ". This is true even in the asynchronous type. Details of this will be described later (paragraph numbers [ 0221 to 0222 ]).

The reason why the IN circuit and the NIN circuit are called based on the IN logic and the NIN logic is that “specific integers a and b (where N−1 ≧ b に お い て in an integer string in which the integers 0 to (N−1) are sequentially arranged) If a + 2 ≧ 2) two are specified, the integer sequence is "an inner integer part consisting of the inner [one or more integers] sandwiched between the two specific integers", ie, "the two specific integers respectively In the case of 塀, the inner integer part consisting of [one or more integers] of the three of the three separated by the specific integer two 塀 and the “inner part not included in the inner integer part” It can be divided into negative integer parts (including the integers a and b).
Therefore, the present inventor uses the former inner integer part as a numerical value determination criterion, and "multi-valued BETWEEN (bitwise) logic or multi-valued IN (in) logic", abbreviated "BETWEEN logic or or IN logic" On the other hand, using the latter inner negative integer part as the numerical discrimination criterion, "multi-valued NOBETWEEN (No-biteween) logic or multi-valued NIN (Nin) logic", abbreviated "NOBETWEEN logic or NIN logic" I decided to call it.
In addition, since "IN" has a smaller number of characters and it starts with a vowel, its negation is convenient because it only needs to be preceded by N to be "NIN". Moreover, the present inventors have already found that multi-level specified value OVER (over) logic (abbreviated OVER logic), multi-level specified value UNDER (under) logic (abbreviated underer logic), multi-level specified value EVEN (even) logic (abbreviated) (Even logic) is used, so it is convenient for unifying with golf terms so that it is easy to remember.
By the way, there is also the following analogy about multi-valued IN logic. If you think of the cross section of the golf "hole or cup" and consider the walls on both sides as "the two specific integers a, b in that integer row" as in the case of the chopsticks described above, "hole in or cup" The inventor thinks that the term “multi-level IN logic” is easy to remember from the association of “in”.

Here, the relationship between each of the numerical judgment criteria of IN logic and NIN logic and each of the logic outputs is as follows.
● IN logic (also known as BETWEEN logic):
It is determined whether the one input integer N _in is one of the inner integer parts. That is, it is determined whether or not the one input integer N _in is an integer between the particular integers a and b and two. However, N is a multi-value number (it is N of N value), and it is N-1> = b> = a + 2> = 2.
Therefore,
・ If b> N _in > a, output a specific integer for output determined in advance,
If N _in bb or a ≧ N _in , release the output.
● NIN logic (also known as NOBETWEEN logic):
Because of the negation of the IN logic, it is determined whether the one input integer N _in is one of its inner negative integer parts. That is, the way of its output is exactly opposite to IN logic.
Therefore,
• If b> N _in > a, release the output,
If N _in bb or a ≧ N _in , a predetermined output specific integer is output.

There is another way to call it, also a way of thinking. Specific integers a and b (where, N-1> b ≧ a + 2> 2) in an integer sequence in which the integers 0 to (N-1) are arranged in order, note: this inequality is different from the case of IN logic) If two integers are specified, the integer sequence is expressed as “each of the two specific integers is a pair, and the outer side is composed of a plurality of integers outside the three parts separated by the two specific integers. It can also be divided into "integer part" and "outside negative integer part not included in the outer integer part thereof (including two specific integers thereof)".
Therefore, the present inventor uses the outer integer part of the former as a numerical value determination criterion and calls it "multi-value OUT (out) logic, abbreviated as OUT logic", while using the outer negative integer part of the latter as a numerical value determination criterion. It is called "multi-valued NOUT (Nauto) logic, abbreviated NOUT logic".
***
★ ★ The difference between OUT logic and NIN logic ★ ★
The difference between OUT logic and NIN logic is that the two particular integers are not included in OUT, but NIN is included.
★ ★ The difference between IN logic and NOUT logic ★ ★
The difference between the IN logic and the NOUT logic is that the two specific integers are not included in the IN one, but are included in the NOUT one.
***
Therefore, OUT (a, b) = NIN (a-1, b + 1), IN (a, b) = NOUT (a + 1, b-1), that is, NOUT (a, b) = IN (a-1, b + 1) It holds. However, two integer values in each parenthesis (brackets) represent two specific integers for each input. Naturally, these things are true in both asynchronous type, mutual type and synchronous type, but naturally, in synchronous type, their synchronous condition and latching condition are the same.

Here, the relationship between each (numerical value) determination criterion of OUT logic and NOUT logic and each logic output is summarized as follows.
● OUT logic:
It is determined whether the one input integer N _in is one of the outer integer parts. However, N is a multi-value number (it is N of N value), and it is N-1>b> = a + 2> 2 (* Note: This inequality is different from the case of IN logic).
Therefore,
・ If N _in > b or a> N _in , output a specific integer for output predetermined,
If b ≧ N _in aa, release the output.
● NOUT logic:
Because of the negation of the OUT logic, it is determined whether the one input integer is one of its outer negative integer parts. That is, the way of the output is opposite to the OUT logic.
Therefore,
• If N _in > b or a> N _in , release the output,
If b ≧ N _in aa, a predetermined output specific integer is output.

The synchronous / multivalued logic circuit described above is of course included in the "multivalued logic means having a synchronous latching function" of the first application of the prior application. These are summarized below.
☆ Synchronous EVEN (even) circuit (also known as synchronous EQUAL circuit)
☆ Synchronous NEVEN (Neven) circuit (also known as synchronous NOT circuit)
☆ Synchronous IN (In) circuit (also known as synchronous BETWEEN circuit)
☆ Synchronous NIN (Nin) circuit (also known as synchronous NOBETWEEN circuit)
☆ Synchronous OUT (Out) Circuit ☆ Synchronous NOUT (Nauto) Circuit

◆ ◆ Prior application · Example 3 ◆ ◇
Prior application-example shown in FIG. 61 3 is also derived from the previous application, Example 1 or each derivative embodiment thereof in FIG. 59. As described above (line 6 to line 10 of paragraph number [ 0205 ]), “determining whether or not the one input integer N _in is equal to or not the specific integer for the one input” is “the one It is the same as “determining whether the input integer N _in is between the two input specific integers (m−1) and (m + 1) or not.
The first application in FIG. 59 and the first embodiment are for the case where the number of integers between the two input specific integers is one, while the first application for the third embodiment is the case in which the number is two. . For this reason, “whether one input integer N _in is an integer that is between two of the input specific integers (== is equal to either) or is not any of them (== all is equal to either) It can be rephrased that "presence of application / example 3 determines".
The prior application / embodiment 3 of FIG. 61 "disconnects the connection between the" source of transistor 2 and back gate in the prior application / embodiment 1 or its derivative embodiment in FIG. 59 "and the power supply line V _m-1 and The source or the like is “the power supply line V ₀ to the power supply line V _m-2 is reconnected to any one power supply line V _G” . That is, 0 ≦ G ≦ m−2.

When the gate of the transistor 41 is connected to the Q terminal of the D-type flip flop 27 in the prior application and the third embodiment, the inventor of the prior application and the third embodiment selects “synchronous NIN circuit” or “synchronous NOBETWEEN It is called "circuit" or "synchronous OUT circuit".
The circuit operation is as follows. The “synchronizing signal supply means constituted by the synchronizing signal generating means 60, the transistor 61 and the resistors 26, 28” supplies the synchronizing signal to the CP terminal of the D-type flip flop 27, but based on this synchronizing signal The flop 27 takes the discrimination result signal from the transistor 17.
Long as the positive output signal of the intake discrimination result signal, i.e. Q terminal indicates that "an integer there between the input integer N _in an integer G and an integer input terminal T _in (m + 1)", "the transistor 41 , 37 etc. drives the transistors 3 and 4 off, so that the output from the output terminal T _out is released.
However, if the positive output signal indicates that this is not the case, the on / off drive means drives the transistors 3 and 4 on, and the specific power supply potential v _m is output from the output terminal T _out in a circuit. , Logically, the output specific integer m is output.
Thereafter, the output state continues until the D-type flip flop 27 takes the next discrimination result signal from the transistor 17 based on the synchronization signal. Thereafter, similarly, the next discrimination result signal is taken, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q bar terminal of the D-type flip flop 27 in the prior application and the third embodiment of FIG. 61, the inventor of the prior application and the third embodiment Or "synchronous IN circuit" or "synchronous NOUT circuit".
Since this circuit operation is a negative operation of the above-mentioned "synchronous NIN circuit", only the way of the output from the output terminal T _out is opposite.

In the case of the IN circuit or the NIN circuit, the two specific integers for input are the integer (m + 1) and the number of the re-connected power supply line, that is, the power supply among "integers 0 to (m-2)" One integer G "corresponding to the line. On the other hand, in the case of the OUT circuit and the NOUT circuit, the two specific integers for the input are the integer m and “the number of the re-connected power supply line, ie [the integer 0 to (m-2) It is an integer (G + 1) obtained by adding 1 to the corresponding single integer G].
Further, by connecting the drain of the transistor 3 from the power supply line V _m to any _one of the other power supply lines V _{0 to} V _{m -1} , the output specific integer can be set from m to 0 to (m-1) It can be changed to any one.

◆ ◆ Prior application · Example 4 ◆ ◇
The prior application and the fourth embodiment shown in FIG. 62 are also derived from the prior application and the first embodiment of FIG. 59 or their derivatives. "Part one input integer N _in is possible to determine or not equal and its one input for a specific integer m", "" one of its inputs the integer N _in is for the first input before the description It is the same as “determining whether or not“ is larger than the specific integer (m−1) and smaller than the second specific input integer (m + 1) ”.
Then, “determining whether or not the one input integer N _in is between the two input specific integers a and b (+2 a + 2) and the two integers” is “” “the one input integer This is the same as “determining whether or not N _in is larger than the first input specific integer a and smaller than the second input specific integer b” or not.
For this reason, a part of the discrimination function of "the prior art, the embodiment 1 or the respective derivative embodiments of FIG. 59 ", that is, "the one input integer N _in is larger or not larger than the first input specific integer a. In the prior application example 4 in which the function of determining the "discrimination function" is eliminated, the synchronous UNDER (under) circuit or the synchronous NUNDER (under) circuit (= negation of the synchronous UNDER circuit) can be obtained.
Therefore, remove the transistors 2,17, diode 35 and resistor 20 in the previous application, Example 1 or each derived embodiments thereof prior application, the fourth embodiment of FIG. 62 is "59," the resistance 21 and the D-type flip- “The connection point of the D terminal of the flop 27” is connected again to the drain of the transistor 1 ”.

When the gate of the transistor 41 is connected to the Q terminal of the D-type flip flop 27 in the prior application and the fourth embodiment of FIG. 62, the inventor of the prior application and the fourth embodiment is referred to as “synchronous NUNDER circuit” or It is called a synchronous OVER (over) circuit. Of course, both specific integers for input are different.
The circuit operation is as follows. The “synchronizing signal supply means constituted by the synchronizing signal generating means 60, the transistor 61 and the resistors 26, 28” supplies the synchronizing signal to the CP terminal of the D-type flip flop 27, but based on this synchronizing signal The flop 27 takes its discrimination result signal from the transistor 1.
If positive output signal of the intake discrimination result signal, i.e. Q terminal indicates that the "input integer N _in the input terminal T _in is an integer (m + 1) is smaller than the integer", the transistor 41,37, etc. to form Since the “on / off driving means” drives the transistors 3 and 4 off, the output from the output terminal T _out is opened.
However, if a positive output signal is "otherwise" or "input integer N _in the input terminal T _in is an integer (m + 1) is greater than or equal to an integer" indicates the its on-off driving means transistor since 3,4 to on-drive, the circuit basis is output specific supply potential v _m from the output terminal T _out, the logical numerical output for a particular integer m is output.
Thereafter, the output state continues until the D-type flip flop 27 takes the next discrimination result signal from the transistor 1 based on the synchronization signal. Thereafter, similarly, the next discrimination result signal is taken, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q-bar terminal of the D-type flip flop 27 in the prior application and the fourth embodiment of FIG. 62, the inventor of the prior application and the fourth embodiment Or “synchronous NOVER (Nounbar) circuit (= negation of synchronous OVER circuit)”. Of course, both specific integers for input are different.
Since this circuit operation is a negative operation of the above-mentioned "synchronous NUNDER circuit" or "synchronous OVER circuit", only the way of output from the output terminal T _out is opposite.

The difference between the UNDER logic and the NOVER logic is that "UNDER does not include one specific integer for itself, and NOVER includes one specific integer for own". And the difference between the OVER logic and the NUNDER logic is that "the OVER does not include one specific integer for oneself, and the one for NUNDER contains one specific integer for oneself". Therefore, UNDER (m + 1) = NOVER (m) and NUNDER (m + 1) = OVER (m) hold. However, one integer value in each parenthesis (bracket) represents one specific input integer.
Moreover, although these things are valid in asynchronous type, mutual type and synchronous type, either, as a matter of course, in synchronous type, the synchronous condition and the latching condition are the same.
Furthermore, by re-connecting “source of transistor 1 and back gate” from power supply line V _{m + 1} to any _one of other power supply lines V _{m +2 to} V _n−1 , identification for each of the · · · · circuit of the UNDER circuit or NUNDER circuit The integer can be changed from (m + 1) to "any one of (m + 2) to (n-1)". However, when “a built-in clamp diode whose one end is connected to the power supply line V _{m + 1} ” is connected to the D terminal of the D-type flip flop 27, the power supply short circuit resistance is It is necessary to connect between the D terminal and the connection point of the resistor 21 ".
Then, by reconnecting the drain of the transistor 3 from the power supply line V _m to any _one of the other power supply lines V _{0 to} V _{m -1,} a specific integer for the output from m to 0 to (m-1) It can be changed to any one.

◆ ◆ Prior application · Example 5 ◆ ◇
The prior application and the fifth embodiment shown in FIG. 63 are also derived from the prior application and the first embodiment of FIG. 59 or their derivatives. "Part one input integer N _in is possible to determine or not equal and its one input for a specific integer m", "" one of its inputs the integer N _in is for the first input before the description It is the same as “determining whether or not“ is larger than the specific integer (m−1) and smaller than the second specific input integer (m + 1) ”.
Then, “determining whether or not the one input integer N _in is between the two input specific integers a and b (+2 a + 2) and the two integers” is “” “the one input integer This is the same as “determining whether or not N _in is larger than the first input specific integer a and smaller than the second input specific integer b” or not.
Therefore, a part of the discrimination function of "the prior art of the first embodiment of FIG. 59 or its respective derivative embodiment", that is, "whether one input integer thereof is smaller or smaller than the second input specific integer b The prior application example 5 in which the “function to be performed” is eliminated can be a synchronous OVER circuit or a synchronous NOVER circuit (= the negation of the synchronous OVER circuit).
Therefore, the prior art example 5 of FIG. 63 removes “the transistor 1 in“ the prior art example 1 or its respective derivative example in FIG. 59 , ”“ connection point of the source of the transistor 17 and the resistor 20 ” _It is directly connected to _{m + 1} .

When the gate of the transistor 41 is connected to the Q terminal of the D-type flip flop 27 in the prior application and the fifth embodiment of FIG. 63, the inventor of the prior application and the fifth embodiment It is called the negation of the type OVER circuit) or “synchronous UNDER circuit”. Of course, both specific integers for input are different.
The circuit operation is as follows. The “synchronizing signal supply means constituted by the synchronizing signal generating means 60, the transistor 61 and the resistors 26, 28” supplies the synchronizing signal to the CP terminal of the D-type flip flop 27, but based on this synchronizing signal The flop 27 takes the discrimination result signal from the transistor 17.
If positive output signal of the intake discrimination result signal, i.e. Q terminal indicates that the "input integer N _in the input terminal T _in is an integer (m-1) integer greater than", transistors 41,37 etc. Since the formed on / off drive means drives the transistors 3 and 4 off, the output from the output terminal T _out is released.
However, if a positive output signal is "otherwise" or "input integer N _in the input terminal T _in is an integer (m-1) is less than or equal to the integer" indicates the its on-off driving means Since the transistors 3 and 4 are driven on, the specific power supply potential v _m is output from the output terminal T _out in the circuit, and the output specific integer m is output in the logical numerical value.
Thereafter, the output state continues until the D-type flip flop 27 takes the next discrimination result signal from the transistor 17 based on the synchronization signal. Thereafter, similarly, the next discrimination result signal is taken, and the same thing is repeated.

On the other hand, when the gate of the transistor 41 is connected to the Q-bar terminal of the D-type flip flop 27 in the prior application and the fifth embodiment of FIG. 63, the inventor of the prior application and the fifth embodiment Or "Synchronized NUNDER circuit". Of course, both specific integers for input are different.
Since this circuit operation is a negative operation of the "synchronous NOVER circuit" or the "synchronous UNDER circuit", only the way of the output from the output terminal T _out is opposite.

The difference between the UNDER logic and the NOVER logic is that "UNDER does not include one specific integer for itself, and NOVER includes one specific integer for own". And the difference between the OVER logic and the NUNDER logic is that "the OVER does not include one specific integer for oneself, and the one for NUNDER contains one specific integer for oneself". Therefore, OVER (m-1) = NUNDER (m) and NOVER (m-1) = UNDER (m) hold. However, one integer value in each parenthesis (bracket) represents one specific input integer.
Moreover, although these things are valid in asynchronous type, mutual type and synchronous type, either, as a matter of course, in synchronous type, the synchronous condition and the latching condition are the same.
Furthermore, by re-connecting the source of the transistor 2 from the power supply line V _m-1 to any _one of the other power supply lines V _{0 to} V _m-2 , each specific input integer for the OVER circuit or NOVER circuit ( m-1) can be changed to "any one of 0 to (m-2)".
Then, by reconnecting the drain of the transistor 3 from the power supply line V _m to any _one of the other power supply lines V _{0 to} V _{m -1,} a specific integer for the output from m to 0 to (m-1) It can be changed to any one.

The synchronous / multivalued logic circuit described above is of course included in the "multivalued logic means having a synchronous latching function" of the first application of the prior application. These are summarized below.
☆ Synchronization type OVER (Ober) circuit ☆ Synchronization type EVEN (even) circuit = Synchronization type EQUAL (equal) circuit ☆ Synchronization type UNDER (under) circuit ☆ Synchronization type NOVER (Know bar) circuit ☆ Synchronization type NEVEN (Neven) circuit = Synchronization Type NOT (knot) circuit ☆ Synchronous NUNDER circuit

◆ ◆ Prior application · Example 6 ◆ ◇
It can be derived from the prior application in FIG. 59 and the prior application in FIG. 64 and the prior application in FIG. Prior application, the embodiment of FIG. 64. 6 there is a case where the diode 10 for reverse blocking in FIG. 64 are connected to when not connected.
"Prior application, the embodiment of Figure 64 when the diode 10 is not connected 6""Removing the transistor 3 in the prior application, the first embodiment of FIG. 59, the source of the" transistor 4, a drain and a resistance of the transistor 37 15 Directly connects the power supply line V _m to the above-mentioned pull switching means (in the paragraph [ 0186 ]) from the bi-directional controllable pull switching means to the reverse conduction type pull down switching This is an embodiment changed to means.
(First Preferred Embodiment in FIG. 59 ; Derivative Embodiment of First Embodiment)
"Furthermore, a reverse blocking diode is inserted between the drain of the transistor 4 and the output terminal T _out to connect the pull switching means described above from bidirectional controllable pull switching means reverse blocking pull down switching The embodiment “Modified to means” is “the prior application / embodiment 6 of FIG. 64 when the diode 10 is connected”. (First Preferred Embodiment in FIG. 59 ; Derivative Embodiment of First Embodiment)
As in these circuit configuration changes, the same "reverse conduction type pull" is also applied from "the prior application · embodiment 2, 3, 4 or 5 or the embodiment 8 or the like described later or their respective derivative embodiments". It is possible to derive each of the following embodiments: “down switching means, reverse blocking pull down switching means”.
Then, in each of the prior art and the sixth embodiment of FIG. 64 and the respective derivative embodiments, connection of the pull switching means is performed from the power supply line V _m to any of “the power supply line V ₀ to the power supply line V _m-1 It is possible to connect to “1” or “new one”, and new derivative embodiments are possible in which the input specific integer (value) and the output specific integer (value) are different from each other. (New / derived example)
"The Institute of Electrical Engineers of Japan Nomenclature No. 9 Power Electronics Authors: "Special Committee on Electrical Standards for Electrical Engineering", "Subcommittee for Semiconductor Power Converters for Electrical Engineering, Editors", Editor: Electrical Society, Inc., Corona Corp. February 28, 2000 Revised version 1st print issued. "Bidirectional switch, bi-directional controllable switch, reverse conducting switch, reverse blocking switch". Note that "valve" has almost the same meaning as "switch".

◆ ◆ Prior application · Example 7 ◆ ◇
It can be derived from the prior application in FIG. 59 and the prior application in FIG. 65 and the prior application in FIG. Prior application, Embodiment 7 of FIG. 65 there is a case where the diode 12 for reverse blocking in Figure 65 is connected to the case not connected.
"Prior application, Embodiment 7 of FIG. 65 when the diode 12 for reverse blocking is not connected" to remove the transistor 4 in the prior application, the first embodiment of "Figure 59, the" transistor 3 source of the transistor 37 This embodiment is an embodiment in which the output terminal T _out is connected to the connection point of the drain and one end of the resistor 15 to configure the reverse conduction type pull-up switching means.
(First Preferred Embodiment in FIG. 59 ; Derivative Embodiment of First Embodiment)
On the other hand, "the prior application, Embodiment 7 of FIG. 65 when the diode 12 is connected" is connected in the prior application, the first embodiment of "Figure 59, a diode 12 for reverse blocking in place of the transistor 4, The cathode terminal is an output terminal _Tout, and the reverse blocking type pull-up switching means is constituted by a series circuit of the diode 12 and the transistor 3 ".
(First Preferred Embodiment in FIG. 59 ; Derivative Embodiment of First Embodiment)
As in these circuit configuration changes, the same "reverse conduction type pull" is also applied from "the prior application · embodiment 2, 3, 4 or 5 or the embodiment 8 or the like described later or their respective derivative embodiments". It is possible to derive each of the following embodiments: “down switching means, reverse blocking pull down switching means”.
In each embodiment and each of its derivation embodiment of the prior application, Embodiment 7 of FIG. 65, either the connection of the pull switching means from the power supply line V _m "of the power supply lines V _{0 ~} power supply line V _m-1 It is possible to connect to “1” or “new one”, and new derivative embodiments are possible in which the input specific integer (value) and the output specific integer (value) are different from each other. (New / derived example)

◆ ◆ Prior application · Example 8 ◆ ◇
Prior application-example shown in FIG. 66. 8, "multi-value logic means having a synchronous latching function" replaced with a different type of numerical discriminating means that number discriminating means in the prior application, the first embodiment of FIG. 59 or "multi Value hazard removal means. “Circuit portion of the transistors 31 to 33, the diode 34 and the resistors 20 to 21, 62, 67” is the new / numerical value discriminating means replaced by the circuit portion.
However, with S = 1, the relationship of “n−1> H ≧ G ≧ m + 1” and “m ≧ 0 (zero)”, that is, “n−2> H−1 ≧ G−1 ≧ m ≧ 0 (zero)” The relationship is

In the case of H = G, the determination contents of the prior application / example 8 of FIG. 66 become “equal or not equal” in the above (in paragraph numbers 0186 to 0188 ). For the sake of simplicity, the logic operation in which the D input signal and the Q output signal of the D-type flip flop 27 coincide with each other without regard to the time delay associated with the synchronization operation is as follows.
When the input numerical value N _in is H, the transistors 31 to 33 and 37 are turned off and the transistors 41, 3 and 4 are turned on, so that the output terminal T _out outputs the specific power supply potential v _m . On the other hand, when the input numerical value N _in is not H, the transistors “31, 33” or 32 ”, 37 are turned on and the transistors 41, 3, 4 are turned off, so the output from the output terminal T _out is opened. Ru. After that, the normal operation of the D-type flip flop 27 is added.
For this reason, the inventor refers to this "multi-level logic means having a synchronous latching function" as a "synchronous EQUAL (equal) circuit" or a "synchronous EVEN (even) circuit".
However, when the gate terminal of the transistor 41 is reconnected from the Q terminal to the Q bar terminal, both on / off operations of the transistors 3 and 4 become opposite, so “specific potential v _m output and open output of the output terminal T _out Since the present invention is also opposite to the above, the present inventor refers to this "multi-level logic means having a synchronous latching function" as a "synchronous NOT (knot) circuit" or a "synchronous NEVEN (even) circuit".

● In the case of “H ≠ G, that is, H> G”, the contents of discrimination of the prior application and example 8 of FIG. 66 are “two input specific integers (H + 1) and (G−)” of (paragraph number ★ 0270 to 0272). Is it between 1) or not? For the sake of simplicity, the logic operation in which the D input signal and the Q output signal of the D-type flip flop 27 coincide with each other without regard to the time delay associated with the synchronization operation is as follows.
When "H + 1> (input numerical value N _in )>G-1", that is, when "H ≧ (input numerical value N _in ) ≧ G", the output terminal T _out outputs the specific power supply potential v _m while When the input numerical value N _in ) ≧ H + 1 or G-1 ((the input numerical value N _in ), that is, the output when “(input numerical value N _in )> H or G> (input numerical value N _in )” The output from the terminal T _out is open. After that, the normal operation of the D-type flip flop 27 is added.
For this reason, the inventor of the present invention has made this "multi-level logic means having a synchronous latching function""a synchronous BETWEEN circuit or a synchronous IN circuit in which two specific integers for input are (H + 1) and (G-1)". , And “a synchronous NOUT (Nauto) circuit where the two input specific integers are H and G (= the negation of the synchronous OUT circuit)”.
However, when the gate terminal of the transistor 41 is reconnected from the Q terminal to the Q bar terminal, both on / off operations of the transistors 3 and 4 become opposite, so that “the specific power supply potential v _m output of the output terminal T _out is opened. The output is also the opposite. For this reason, the inventor of the present invention has made this "multi-level logic means having a synchronous latching function""a synchronous NOBETWEEN circuit or a synchronous NIN circuit" in which the two specific integers for input are (H + 1) and (G-1). , “Also referred to as a synchronous OUT circuit in which the two input specific integers are H and G”.

By the way, the difference between the "synchronous IN circuit and the synchronous NOUT circuit" in which the two input specific integers in the previous application and the example 8 in FIG. 66 are H and G does not include the former two specific input integers. , The latter is to be included. Therefore, in order for the synchronous IN circuit to include H and G, the two specific integers for input become (H + 1) and (G-1).
Similarly, the difference between a synchronous OUT circuit and a synchronous NIN circuit in which two specific integers for input are (H + 1) and (G-1) does not include the two specific integers for input but the latter includes It is. Therefore, in order for the synchronous OUT circuit to include (H + 1) and (G-1), the two specific integers for input become H and G.

In addition, in the case of H = G and in the case of H ≠ G, that is, H> G in the prior application / example 8 of FIG. 66, the pull-up resistance 26 or “26, 28” and D-type flip each operation flop 27 "is the same as in the prior application, the first embodiment of FIG. 59 (paragraph [0212-0213].).
In addition, the fact described in paragraph numbers [ 0212, 0228 to 0238 ] can be similarly applied to the prior application and the eighth embodiment. The same applies to the other embodiments utilizing the numerical value determination means of the prior application and the eighth embodiment. However, the "(m + 1) in the prior application, Example 1 and the like in FIG. 59, (m-1) of possible ways for each value""H in the prior application, Example 8 or the like in FIG. 66, for each value of G Furthermore, by re-connecting the drain of the transistor 3 from the power supply line V _m to any _one of the other power supply lines V _{0 to} V _{m -1} , the specific integer for the output is from m to 0 (m It can be changed to any one of -1).

In Japanese Patent Application Laid-Open No. 2005-236985, paragraph “[0033]” of asynchronous type “AND”, “NAND”, “OR”, “NOR” and an asynchronous type “BETWEEN”, “NO BETWEEN”. It describes about the combination of].
Likewise, asynchronous "AND", "NAND", "OR", "NOR" groups and asynchronous "IN", "NIN", "OUT", "NOUT" The combination of (Nauto) 'groups can be considered as follows.
However, basically, AND means "that all the plurality of input integers are ...", and OR means "at least one of the plurality of input integers is ...".
In addition, when the present inventors first proposed these classifications and classification names, some of these multi-valued logic functions were given because each function was given redundancy. Although overlapping, if the Hooji Algebra goes widely used, these circuit names and functions will be converged to be easy to use.

■■ About various IN circuits and various NIN circuits ■■
● AND · IN circuit (also known as AND · BETWEEN circuit)
If the plurality of input integers are all "an integer between the two specific integers a and b for input", the output specific integer is output, and otherwise the output is released.
In other words, if at least one input integer of the plurality of input integers is "an integer smaller than or equal to (≦ a) or an integer larger than b (≧ b)", the output is Release, otherwise output a specific integer for output.
In this case, since b ≧ a + 2, it is natural that there is no integer which is “≧ b” and “a ≧”.

☆☆☆☆☆☆☆
In the set theory, a set "is an A or B" is a union of a set "is only A", a set "is only B" and a set "is a and B (intersection)".
Therefore, if the set “A and B” is empty, the set “A or B” is a union of the set “only A” and the set “B only”.

● NAND · IN circuit (also known as NAND · BETWEEN circuit)
Since this circuit is the negation of the AND-IN circuit, the way of its output is opposite. Therefore, if all of the plurality of input integers are "an integer between the two specific integers a and b," the output is released, otherwise the specific output integers are output. .
In other words, if at least one input integer of the plurality of input integers is "an integer smaller than or equal to (≦ a) or an integer larger than b (≧ b)", for output Output a specific integer, otherwise release the output.
● AND · NIN circuit (also known as AND · NO BETWEEN circuit)
If all of the plurality of input integers are "integer less than or equal to a (≦ a), or integers greater than or equal to b (≧ b)", that is, each of the plurality of input integers is "a If the integer is smaller than or equal to (≦ a) or “integer to be equal to or larger than b (≧ b)”, the output specific integer is output, otherwise, the output is released.
In other words, if at least one input integer among the plurality of input integers is "an integer between the two and the specific integers a and b for input", the output is released, otherwise, Output the specific integer for output.
● NAND · NIN circuit (also known as NAND · NO BETWEEN circuit)
Since this circuit is the negation of the AND · NIN circuit, the way of its output is opposite. Therefore, if all of the plurality of input integers are "integers smaller than or equal to (≦ a) or integers greater than or equal to b (≧ b)", that is, each of the plurality of input integers is If either "integer less than or equal to a (≦ a)" or "integer greater than or equal to b (≧ b)" release the output, otherwise output a specific integer for the output Do.
In other words, if at least one input integer among the plurality of input integers is “an integer between the two and the specific integers for input a and b”, the specific integer for output is output, and so If not, open the output.

● OR · IN circuit (also known as OR · BETWEEN circuit)
If at least one of the plurality of input integers is "an integer between the two specific integers a and b for input", the output specific integer is output, otherwise the output is output. Open.
In other words, if all of the plurality of input integers are "integer less than or equal to a (≦ a), or integers greater than or equal to b (≧ b)", that is, each of the plurality of input integers If is either an integer less than or equal to a (≦ a) or an integer greater than or equal to b (≧ b), then release the output, otherwise, use a specific integer for the output Output.
● NOR · IN circuit (also known as NOR · BETWEEN circuit)
Since this circuit is the negation of the OR-IN circuit, the way of its output is opposite. Therefore, if at least one of the plurality of input integers is “an integer between the two specific integers a and b,” the output is released, otherwise the output specific Output an integer.
In other words, if all of the plurality of input integers are "integer less than or equal to a (≦ a), or integers greater than or equal to b (≧ b)", that is, each of the plurality of input integers If is either an integer less than or equal to a (≦ a) or an integer greater than or equal to b (≧ b), then output a specific integer for that output, otherwise Open.
● OR · NIN circuit (also known as OR · NO BETWEEN circuit)
If at least one of the plurality of input integers is “an integer smaller than or equal to (≦ a) or an integer larger than b (≧ b)”, a specific integer for the output is output, Otherwise, release the output.
In other words, if all of the plurality of input integers are "an integer between the two specific integers a and b between them," the output is released, otherwise, the specific integer for output is output Do.
● NOR · NIN circuit (also known as NOR · NO BETWEEN circuit)
Since this circuit is the negation of the OR-NIN circuit, the way of its output is opposite. Therefore, if at least one of the plurality of input integers is "an integer smaller than or equal to (≦ a) or an integer larger than b (≧ b)", the output is released, and so Otherwise, the output specific integer is output.
In other words, if all of the plurality of input integers are "an integer between the two and the specific integers a and b for input," the specific integer for output is output, otherwise the output is released .

■■ Regarding various OUT circuits and various NOUT circuits ■■
When the two specific integers for input are a and b, they are as follows.
If the plurality of input integers are all "smaller than a (<a) or larger than b (>b)", that is, each of the plural input integers is " If it is either an integer less than or equal to a (≦ a) or an integer greater than or equal to b (≧ b), output a specific integer for its output, otherwise release its output .
In other words, if at least one of the plurality of input integers is "an integer equal to a or b, or an integer between a and b", the output is released, otherwise, Output a specific integer for output.
● NAND · OUT circuit This circuit is the negation of the AND · OUT circuit, so the way of its output is opposite. Therefore, if all of the plurality of input integers are "integer smaller than a (<a) or integer greater than b (>b)", that is, each of the plurality of input integers is smaller than "a If it is either an equal integer (≦ a) or an integer greater than or equal to b (≧ b), the output is released, otherwise, a specific integer for the output is output.
In other words, if at least one of the plurality of input integers is "an integer equal to a or b, or an integer between a and b", a specific integer for the output is output, otherwise For example, release the output.
· · · · · · · AND · NOUT circuit If the plurality of input integers are all "an integer equal to a or b, or an integer between a and b", output a specific integer for the output, otherwise, Release the output.
In other words, if at least one of the plurality of input integers is "an integer smaller than a (<a) or an integer larger than b (>b)", the output is released, otherwise , Output specific integers for output.
● NAND · NOUT circuit This circuit is the negation of the AND · NOUT circuit, so the way of its output is opposite. Therefore, if all of the plurality of input integers are "integers equal to a or b or integers between a and b", the output is released, otherwise, the specific integer for output is output Do.
In other words, if at least one of the plurality of input integers is "an integer smaller than a (<a) or an integer larger than b (>b)", the output specific integer is output, and so Otherwise, release the output.

● OR · OUT circuit If at least one of the plurality of input integers is "an integer smaller than a (<a) or an integer larger than b (>b)", the output specific integer is output. If not, release the output.
In other words, if all of the plurality of input integers are "integers equal to a or b or integers between a and b", the output is released, otherwise, the specific integer for the output Output
● NOR · OUT circuit This circuit is the negation of the OR · OUT circuit, so the way of its output is opposite. Therefore, if at least one of the plurality of input integers is "an integer smaller than a (<a) or an integer larger than b (>b)", the output is released, otherwise, Output the specific integer for output.
In other words, if all of the plurality of input integers are "integers equal to a or b or integers between a and b", the output specific integer is output, otherwise, the output Open
-OR NOUT circuit If at least one of the plurality of input integers is "an integer equal to a or b, or an integer between a and b", a specific integer for the output is output, so Otherwise, release the output.
In other words, if all of the plurality of input integers are "an integer smaller than a (<a) or an integer larger than b (>b)", that is, each of the plurality of input integers If the integer is smaller than or equal to (≦ a) or “integer greater than or equal to b (≧ b)”, the output is released. Otherwise, the specific integer for output is output.
● NOR · NOUT circuit This circuit is the negation of the OR · NOUT circuit, so the way of its output is opposite. Therefore, if at least one of the plurality of input integers is "an integer equal to a or b, or an integer between a and b", the output is released, otherwise, the output Output specific integers for
In other words, if all of the plurality of input integers are "an integer smaller than a (<a) or an integer larger than b (>b)", that is, each of the plurality of input integers If the integer is smaller than or equal to (≦ a) or “integer greater than or equal to b (≧ b)”, the output specific integer is output, otherwise the output is released.

The identities that hold for these multilevel logic circuits are summarized below. As a matter of course, “each of a plurality of logic variables, each of two input specific integers, an output specific integer, and each other” of each and both circuits are the same. Furthermore, if each and both circuits are synchronous and each other, the synchronization conditions such as the synchronization frequency and the latching conditions are also the same.
However, in the "IN circuit, NIN circuit" and "OUT circuit, NOUT circuit" that are the sources of each circuit, as described above, these two specific integers for input are shifted by one each in either integer.
★ a) AND · IN circuit = NOR · NIN circuit ★ b) NAND · IN circuit = OR · NIN circuit ★ c) AND · NIN circuit = NOR · IN circuit ★ d) NAND · NIN circuit = OR · IN circuit ★ e ) AND · OUT circuit = NOR · NOUT circuit ★ f) NAND · OUT circuit = OR · NOUT circuit ★ g) AND · NOUT circuit = NOR · OUT circuit ★ h) NAND · NOUT circuit = OR · OUT circuit

These identities also mean that “asynchronous type, mutual synchronization type, mutual synchronization type, only the same multilevel logic circuit is simply called by two names”. Has an important meaning.
For example, since the NAND IN logic is the negation of the AND IN logic, the AND IN logic and the NAND IN logic are complementary to each other, and the NAND IN logic and the OR NIN logic are the same. The NIN logic will also be complementary to each other. Similarly, NAND 同 様 IN logic and NOR ・ NIN logic are complementary to each other.
In this case, the “complementary relationship” means that “when a predetermined plurality of logic variables are simultaneously given to the two logics, one logic becomes the value of a specific integer for its output, and the other logic The opposite output, that is, an open output, is meant.
Incidentally, for example, since the above-mentioned ★ a) term means AND · IN logic means "combination of OR · NIN logic and NOT logic", the synchronous AND · IN circuit can be added to the latter stage of the synchronous OR · NIN circuit. Connect an asynchronous NOT circuit and connect a pull-up resistor or pull-down resistor for matching between the two circuits or connect a synchronous NOT circuit after the asynchronous OR NIN circuit Can be configured alternatively with a pull-up or pull-down resistor connected for matching between the two circuits. However, "time delay, power loss, and multi-level hazards" can be used. It is also conceivable to use it for “time adjustment, timing alignment or matching of two logic signals” in reverse. In this case, it is conceivable to synchronize both circuits.

先 ◆ Prior application / example 9 shown in Fig. 67 ◆ ◇
FIG. 67 shows the "ON / OFF driving means", the "bidirectional pull switching means" and the like of the prior application and the ninth embodiment. "Prior application, Example 8 shown in FIG. 66," or "the embodiment of the prior application, Examples 1 to 5 shown in each of FIGS. 59-63" or as pre-stage circuit portion including the D-type flip-flop 27 The pre-stage circuit portion in “Example 16 shown in FIG. 75 described later” or “Prior to Example 17 illustrated in FIG. 76 described later” is connected. The "circuit portion of the transistor 41, 22-25 (the diode 36) and the resistor 15" is its on / off driving means, and the series circuit of the transistors 3 and 5 is its bidirectional pull switching means.
However, the diode 36 shown by a dotted line may not exist, but if not, if the potential of the output terminal T _out is higher than the power supply potential v _{m + 1} when the transistor 5 is turned off, the charge current of the gate Flows from the output terminal T _out to the power supply line V _{m + 1} via the transistor 5 built-in diode and the transistor 22.

Alternatively, the drain terminals of the transistor 41 may be used as the output terminal T _out by removing the transistors 22 to 25, 3 and 5 and the resistor 15. In this case, the transistor 41 may be used as a reverse conducting pull-up switching means by forming the built-in diode, or a reverse blocking diode is connected in series to the transistor 41 to serve as a reverse blocking pull-up switching means. There is also a case to use. (Another embodiment)
Or, as in the prior application example 6 of FIG. 64 , “use reverse blocking diode 10 instead of transistor 5 to configure reverse blocking pull-down switching means together with transistor 3” or “use transistor 5 Alternatively, the drain terminal of the transistor 3 may be used as the output terminal T _out to constitute a reverse conduction type pull down switching means.
(Derivative embodiment)
Or, remove the Examples, "Remove the transistor 3 constitutes a reverse conduction-type pull-up switching means is directly connected to the source of the transistor 5 to the power supply line V _m" as the seven "transistor 3 in FIG. 65, directly the source of the transistor 5 to the power supply line V _m, and inserting and connecting the reverse blocking diode between the drain and the output terminal T _out of the transistor 5, reverse blocking pull a series circuit of the diode and the transistor 5 It is also possible to "configure up switching means". (Derivative embodiment)
The same applies to “the prior application / example 11 shown in FIG. 69 ” described later.

先 ◆ Prior application / example 10 shown in Fig. 68 ◆ ◇
The prior application · embodiment 10 shown in Fig. 68 is a modification of the prior application · embodiment 9 shown in Fig. 67 . Although this prior application, Example 10 is "a multi-level logic circuit called a multi-level logic circuit which the inventor calls a synchronous multi-level EVEN circuit or a non-inversion buffer circuit", connection of both gates of the transistors 22 and 23 is If the Q terminal is changed to the Q bar terminal, the prior application example 10 becomes "the present inventor is a synchronous multi-value NOT circuit or a multi-value NEVEN circuit".
Since the D-type flip flop 127 in FIG. 68 operates at twice the power supply voltage of the D-type flip flop 27 (in FIG. 67 ), power is supplied from both power supply lines V _m-1 and V _{m + 1} . Therefore, since the D-type flip flop 127 directly drives the transistors 22 to 25 on and off, the transistor 41 and the resistor 15 in FIG. 67 are not necessary.
In addition, the output portion (= the circuit portion of the Q terminal and the Q bar terminal) of the D-type flip flop 127 has the same configuration as “the on / off driving means constituted by the transistors 22 to 25 (and the diode 36)” If the output current capacity of each of the Q terminal and the Q bar terminal is sufficiently large, the D-type flip flop 127 can directly drive the transistors 3 and 5 on and off.
That is, one gate of the transistors 3 and 5 is connected to the Q terminal, and the other gate is connected to the Q bar terminal. In this case, the D-type flip flop 127 doubles as the on / off driving means described above (paragraph number [ 0186 ]).

先 ◆ Prior application / example 11 shown in Fig. 69 ◆ ◇
FIG. 69 shows the "ON / OFF driving means", the "bidirectional pull / switching means", and the like of the prior application and the eleventh embodiment. As pre-stage circuit unit including a D-type flip-flop 27 "prior application, Example 8 shown in FIG. 66," "prior application, each example of Examples 1 to 5 shown in each of FIGS. 59-63" or or " The pre-stage circuit portion in the prior application · embodiment 16 shown in Fig. 75 described later or the prior application · embodiment 17 shown in Fig. 76 described later is connected.
67 differs from the prior art and the ninth embodiment in that “connection order of transistors 3 and 5”, “how to connect each gate of transistors 3 and 5” and “on / off operation of transistors 3 and 5 are opposite to each other”. That is, therefore, that logic is the negation of the first application and the ninth embodiment.
However, in both the prior application and the ninth embodiment of FIG. 67 and the prior application and the eleventh embodiment of FIG. 69 , in order to accelerate the off drive of the output terminal T _out side transistor first, its gate is It is connected.

先 ◆ Prior application / example 12 shown in FIG. 70 ◆ ◇
Prior application, Example 12 shown in FIG. 70 is a modification of the prior application, Example 11 shown in FIG. 69. Although this prior application example 12 is “a multi-level logic circuit which the present inventor calls a synchronous multi-level NOT circuit or a multi-level NEVEN circuit”, connection of both gates of the transistors 22 and 23 is from the Q terminal to the Q bar. If the terminal is changed, the prior application example 12 becomes "a multilevel logic circuit which the inventor calls a synchronous multilevel EVEN circuit or a non-inversion buffer circuit".
Since the D-type flip flop 127 in FIG. 70 operates at twice the power supply voltage of the D-type flip flop 27 (in FIG. 69 ), power is supplied from both power supply lines V _m-1 and V _{m + 1} . Therefore, since the D-type flip flop 127 directly drives the transistors 22 to 25 on and off, the transistor 41 and the resistor 15 in FIG. 69 are not necessary.
In addition, the output portion (= the circuit portion of the Q terminal and the Q bar terminal) of the D-type flip flop 127 has the same configuration as “the on / off driving means constituted by the transistors 22 to 25 (and the diode 36)” If the output current capacity of each of the Q terminal and the Q bar terminal is sufficiently large, the D-type flip flop 127 can directly drive the transistors 3 and 5 on and off.
That is, one gate of the transistors 3 and 5 is connected to the Q terminal, and the other gate is connected to the Q bar terminal. In this case, the D-type flip flop 127 doubles as the on / off driving means described above (paragraph number [ 0186 ]).

◆ ◆ Prior application shown in Figure 71 · Example 13 ◆ ◇
FIG. 71 shows the "on / off driving means" and the "bidirectional pull switching means" in the prior application · example 13. As pre-stage circuit unit including a D-type flip-flop 27 "prior application, Example 8 shown in FIG. 66," "prior application, each example of Examples 1 to 5 shown in each of FIGS. 59-63" or or " The pre-stage circuit portion in the prior application · embodiment 16 shown in Fig. 75 described later or the prior application · embodiment 17 shown in Fig. 76 described later is connected.
In order to accelerate the off speed of "bidirectional pull switching means formed by transistors 3 to 6 and diodes 9 to 12", each gate can be reverse biased.
If the transistors 3, 6 and the diodes 9, 12 are removed, the bidirectional switching means become reverse blocking pull down switching means. On the other hand, if the transistors 4, 5 and the diodes 10, 11 are removed, the bi-directional switching means become reverse blocking pull-up switching means.
Also, remove the transistor 41 and the resistor 15 in the previous application, Example 13 in FIG. 71, the prior application, examples 10 and 12 in "each of FIGS. 68, 70 as a pre-stage circuit unit including a D-type flip-flop 127 The pre-stage circuit portion in each embodiment of the present invention may be connected.
In this case, the output portion (= the circuit portion of the Q terminal and the Q bar terminal) of the D-type flip flop 127 has the same configuration as “the on / off driving means composed of the transistors 22 to 25 (and the diode 36)” If the output current capacity of each of the Q terminal and the Q bar terminal is sufficiently large, the D-type flip flop 127 can directly drive the transistors 3 to 6 on and off. That is, among the transistors 3 and 4 and the transistors 5 and 6, one common gate is connected to the Q terminal, and the other common gate is connected to the Q bar terminal. In this case, the D-type flip flop 127 doubles as the on / off driving means described above (paragraph number [★ 0236]).
Reference: Patent No. 3423780 (bidirectional switching means and unidirectional switching means)

◆ ◆ Prior application / example 14 shown in Fig. 72 ◆ ◇
FIG. 72 shows the "on / off driving means" and the "bidirectional pull switching means" in the prior application · 14th embodiment. As pre-stage circuit unit including a D-type flip-flop 27 "prior application, Example 8 shown in FIG. 66," or "the embodiment of the prior application, Examples 1 to 5 shown in each of FIGS. 135-139" or " The pre-stage circuit portion in the prior application · embodiment 16 shown in Fig. 75 described later or the prior application · embodiment 17 shown in Fig. 76 described later is connected. However, the power supply line V _m and the power supply line IV _m if there is also the same case, there is also a case of completely different.
In the prior application example 14 the “fully isolated bidirectional switching means” is used as the “pull switching means described above (Paragraph No. [ 0186 ])” and “the power supply to which one of the switch terminals is connected” The line IV _m "may be any of the power supply line V ₀ to the power supply line V _{n -1} . In short, it can be freely set the power supply potential iv _m of the power supply line IV _m.
The reason is as follows. When transistors 41, 23, 24, 47 are on, transistors 24, 47 and diodes 49-50, 65-66 gate reverse bias each of "transistors 3 to 6 forming their bi-directional switching means" and at the same time gate The capacitor 45 for forward bias is charged. At this time, since the transistors 3 to 6 are off, the power supply line IV _m and the output terminal T _out are blocked (shielded) in both directions with the gate-source portion, and thus the power supply line V _{m + 1} and the power supply line V Both _m-1 are blocked in both directions.
On the other hand, when the transistors 41 and 23 are off and the transistor 22 is on, the “transistors 24 and 47 and the diodes 49 to 50 and 65 to 66” are bi-directionally off. due to being blocked in the power supply line V _{m + 1} and the power supply line V _m-1 two-way, completely trouble no it is in a conductive state a gate-source unit and the power supply line IV _m and the output terminal T _out. At this time, the gate forward bias capacitor 45 simultaneously drives on all the "transistors 3 to 6 forming the bidirectional switching means" at the same time.
Reference: Patent 3423780 (fully isolated bidirectional switching means)

先 ◆ Prior application / example 15 shown in Fig. 73 ◆ ◇
In the prior application / example 15 shown in FIG. 73 , "conditionally isolated bidirectional switching means" is used as "bidirectional pull switching means". The specific power supply potential v _{m of the} power supply line V _{m and} the potential of “the post-stage circuit input connected to the output terminal T _out , the load, etc.” are both required to be higher than the power supply potential v ₀ . Specific supply potential v _m as long as this potential condition is satisfied, it is possible to freely set the height of the particular power supply potential v _m.
Therefore, the value of the output specific integer m is not restricted at all by the values of the input specific integers “H and G”, and the output specific integer m is set to a free value between n−1 ≧ mm1. be able to.
The reason is as follows. When the transistors 47 and 48 are on, the diodes 49 and 50 together with the diodes 49 and 50 reverse bias and turn off the "bidirectional pull switching means formed by the transistors 3 and 4" while charging the capacitor 45 for gate forward bias. . Unless the potential of a particular power supply potential _{v m} and the output terminal _{T out} this time is higher than the power supply potential _{v 0,} the gate-source section of the transistors 3 and 4 is cut off the power supply line _{V m} and the output terminal _{T out.}
On the other hand, when the transistors 47 and 48 are off, the capacitor 45 operates to turn on the bi-directional pull switching means, ie, the transistors 3 and 4, so that a reverse voltage passes from the power supply line _Vm through the transistor 3 to the diode. 49 and 50, both diodes are off. Therefore, the gate-source portion is cut off from both power supply lines V ₀ and V ₋₁ , so there is no problem even if the gate-source portion is electrically connected to power supply line V _m and output terminal T _out .
Reference: Patent No. 3321203 (conditional isolated switching means)

先 ◆ Prior application / example 16 shown in Fig. 75 ◆ ◇
The prior application · embodiment 16 shown in Fig. 75 is an application of "the prior application · embodiment 8 shown in Fig. 66 ". "Transistors 41,37 of is not shown in the prior application, Example 16 of Figure 75 in" prior application, Example 8 shown in FIG. 66 "is downstream of the D-type flip-flop 27, diode 39 and resistor 15 Are connected, and "a bidirectional pull switching means in which the transistors 3 and 4 are connected in series" is connected.
Alternatively, D-type "prior application, Example 9 shown in FIG. 67" is in the subsequent stage of the flip-flop 27 to the "on-off shown in any one of the" prior application, Example 14 shown in FIG. 72 " The driving means and the bi-directional pull switching means are connected. However, when using the "on / off driving means and bidirectional pull switching means" shown in the prior art and embodiments 10 and 12 of FIGS. 68 and 70 , a power supply is used instead of the D-type flip flop 27. A voltage doubled D-type flip flop 127 is used.
The prior application, Example 16 of Figure 75 the "prior application, Example 13 shown in FIG. 71," or "prior application, Example 9 shown in FIG. 67," or "prior application, Example 8 shown in FIG. 66," " The following four cases will be considered when the on / off driving means and the bidirectional pull switching means are connected.
◆ ◆ ◆ 1) If H = G:
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the non-inversion / logic operation of the original asynchronous / multilevel logic circuit and its inversion / logic operation" is as follows.
◆ a) Non-inversion, logic operation;
Therefore one input for a specific integer is H, the input integer _{N in1, N in2} certain integer m output from the output terminal _{T out} if integer both H at the input terminal _{T in1, T in2} is output, if not The output from the output terminal T _out is open. For this reason, the inventor further refers to the "multi-value logic means having a synchronous latching function" of the prior application / example 16 of FIG. 75 as a synchronous (multi-value) AND circuit.
◆ b) Inversion, logic operation;
If both input integers N _in1 and N _in2 are integers H, the output from the output terminal T _out is released, otherwise the output specific integer m is output from the output terminal T _out . Therefore, (in FIG. 66, in FIG. 67, in FIG. 71) transistor 41 in the prior application, Example 16 of Figure 75 when the gate terminal of the re-connection from the Q terminal to the terminal Q, the prior application, Example 16 The “multi-level logic means having a synchronous latching function” in “2” is “a circuit which the present inventor further calls“ a synchronous (multi-level) NAND circuit having H as a specific integer for input ”” ”.

◆ ◆ ◆ 2) If H> G:
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the non-inversion / logic operation of the original asynchronous / multilevel logic circuit and its inversion / logic operation" is as follows.
◆ a) Non-inversion, logic operation;
Input integer _{N in1, N in2} are both _{"H ≧ N in1, N in2 ≧} G " of the input terminal _{T in1, T in2} if certain integer m output from the output terminal _{T out} is output, the output terminal _{T out} if not The output from is released. For this reason, the inventor of the present invention has shown the prior art example 16 shown in FIG. 75 as “a synchronous AND · NOUT circuit (or a synchronous NOR · OUT circuit) having H and G as two specific integers (values) for input). Call it
◆ b) Inversion, logic operation;
If the input integers N _in1 and N _in2 are both “H ≧ N _in1 , N _in2 GG”, the output terminal T _out is opened, otherwise the output specific integer m is output from the output terminal T _out . Therefore, (in FIG. 66, in FIG. 67, in FIG. 71) transistor 41 in the prior application, Example 16 of Figure 75 when the gate terminal of the re-connection from the Q terminal to the terminal Q, the prior application, Example 16 Is a circuit that the inventor further calls “a synchronous (multi-level) NAND • NOUT circuit (or a synchronous OR • OUT circuit) having two specific integers (values) for H and G”.

◆ ◆ ◆ 3) When the transistors 32a and 32b, the diode 34 and the resistor 67 are removed:
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the non-inversion / logic operation of the original asynchronous / multilevel logic circuit and its inversion / logic operation" is as follows.
◆ a) Non-inversion, logic operation;
Input integer _{N in1, N in2} certain integer m output from the output terminal _{T out} if both integers H less than or equal to the input terminal _{T in1, T in2} is outputted, the output from the output terminal _{T out} if not open Be done. Therefore, the inventor of the present invention refers to the prior application example 16 shown in FIG. 75 as “a synchronous AND · NOVER circuit (or a synchronous NOR · OVER circuit) where H is a specific integer for one of its inputs.
◆ b) Inversion, logic operation;
If at least one of the input integers N _in1 and N _in2 is larger than the integer H, the output specific integer m is output, otherwise, that is, if both input integers N _in1 and N _in2 are smaller than or equal to the integer H The output from T _out is released. Therefore, (in FIG. 66, in FIG. 67, in FIG. 71) transistor 41 in the prior application, Example 16 of Figure 75 when the gate terminal of the re-connection from the Q terminal to the terminal Q, the prior application, Example 16 Is a circuit that the inventor further calls "a synchronous NAND.NOVER circuit (or a synchronous OR.OVER circuit) in which the specific integer for one of its inputs is H."

◆ ◆ ◆ 4) When the transistors 31a, 31b, 33a, 33b, the diodes 35a, 35b and the resistors 20a, 20b, 62 are removed:
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the non-inversion / logic operation of the original asynchronous / multilevel logic circuit and its inversion / logic operation" is as follows.
◆ a) Non-inversion, logic operation;
Input integer _{N in1, N in2} certain integer m output from the output terminal _{T out} if both greater than or equal to an integer G input terminal _{T in1, T in2} is outputted, the output from the output terminal _{T out} if not open Be done. Therefore, the inventor of the present invention refers to the prior application example 16 shown in FIG. 151 as “a synchronous AND · NUNDER circuit (or a synchronous NOR · UNDER circuit) in which one specific input integer is G).
◆ b) Inversion, logic operation;
The output specific integer m is output if at least one of the input integers N _in1 and N _in2 is smaller than the integer G, otherwise the output terminal if the input integers N _in1 and N _in2 are both greater than or equal to the integer G The output from T _out is released. Therefore, (in FIG. 66, in FIG. 67, in FIG. 71) transistor 41 in the prior application, Example 16 of Figure 75 when the gate terminal of the re-connection from the Q terminal to the terminal Q, the prior application, Example 16 Is a circuit that the inventor further calls "a synchronous NAND.NUNDER circuit (or a synchronous OR.UNDER circuit) in which the specific integer for one input is G."

The identities that hold for these multilevel logic circuits are summarized below. It goes without saying that “each of a plurality of logic variables, input specific integers, each other, output specific integers, each other” of each and both circuits are the same. Furthermore, if each and both circuits are synchronous and each other, the synchronization conditions such as the synchronization frequency and the latching conditions are also the same.
However, in the "OVER circuit, NOVER circuit" and "UNDER circuit, NUNDER circuit" which are the basis of each circuit, these input specific integers are shifted by 1 as described above.
★ a) AND · NUNDER circuit = NOR · UNDER circuit ★ b) NAND · NUNDER circuit = OR · UNDER circuit ★ c) OR · NUNDER circuit = NAND · UNDER circuit ★ d) NOR · NUNDER circuit = AND · UNDER circuit ★ e ) AND · NOVER circuit = NOR · OVER circuit ★ f) NAND · NOVER circuit = OR · OVER circuit ★ g) OR · NOVER circuit = NAND · OVER circuit ★ h) NOR · NOVER circuit = AND · OVER circuit

These identities also mean that “asynchronous type, mutual synchronization type, mutual synchronization type, only the same multilevel logic circuit is simply called by two names”. Has an important meaning.
For example, since NAND · NUNDER logic is the negation of AND · NUNDER logic, AND · NUNDER logic and NAND · NUNDER logic are complementary to each other, and NAND · NUNDER logic and OR · UNDER logic are the same, so AND · NUNDER logic and OR · The UNDER logic will also be complementary to each other. Similarly, NAND · NUNDER logic and NOR · UNDER logic are complementary to each other.
In this case, the “complementary relationship” means that “when a predetermined plurality of logic variables are simultaneously given to the two logics, one logic becomes the value of a specific integer for its output, and the other logic It means that "the opposite output, the open output".
In addition, for example, since the OR · UNDER logic means "combination of AND · NUNDER logic and NOT logic" from the above item b), the synchronous OR · UNDER circuit is "followed by the synchronous AND · NUNDER circuit. Connect an asynchronous NOT circuit to the circuit, and connect a pull-up resistor or pull-down resistor for matching between the two circuits or “a synchronous NOT circuit at the back of the asynchronous AND / NUNDER circuit. It can be alternatively configured by connecting and connecting a pull-up resistor or pull-down resistor for matching between the two circuits. However, “time delay, power loss, and multiple values can be used. It is disadvantageous in terms of hazards (No), it is used reversely to "time adjustment, timing alignment, or matching of two logic signals". It is also conceivable to. In this case, it is conceivable to synchronize both circuits.
In the same way, for example, from the above item a) to AND · NUNDER logic means “combination of OR · UNDER logic and NOT logic”, so that the synchronous AND · NUNDER circuit is “the synchronous OR · UNDER circuit Connect an asynchronous NOT circuit in the latter stage and connect pull-up resistor or pull-down resistor for matching between the two circuits or “Synchronized NOT circuit in the latter stage of asynchronous OR / UNDER circuit Can be configured alternatively by connecting a pull-up resistor or pull-down resistor for matching between the two circuits. It is disadvantageous from the aspect. It is also conceivable to use it for “time adjustment, timing alignment, or matching of two logic signals” in reverse. In this case, it is conceivable to synchronize both circuits.

Then, "on-off driving means and the bi-directional pull switching means, such as" prior application, Example 8 shown in FIG. 66 "above the subsequent stage of the D-type flip-flop 27 in the prior application, Example 16 of FIG. 75 the next time you connect to "on-off driving means and the bi-directional pull switching means" of the "no" prior application, example 11 shown in FIG. 69, "or" prior application, example 14 shown in FIG. 72 " Follow the street.
"The content when the gate terminal of the transistor 41 is connected to the Q terminal (= non-inverting logic) in the above-mentioned (paragraph number [ 0261 to 0264 ]) ◆ 1 ◆ 1) to ◆ ◇ 4 4" is "here When the gate terminal is connected to the Q-bar terminal (= inverted logic), and the gate terminal of the transistor 41 is connected to the Q-bar terminal in “above-mentioned ◆ ◇ ◆ 1) to ◆ ◆ ◆ 4) The content of (= inverted logic) is simply “here, the content when the gate terminal is connected to the Q terminal (= non-inverted logic)”.
Then, in each of the prior application, examples 8-14 shown in FIG. 66 to FIG. 72, has been described for each example was changed its output for a particular integer, previous application, Example 16 shown in FIG. 75 of them Since “the on / off driving means and the bidirectional pull switching means” of the embodiment are used, naturally, the specific integer for output can be changed also in the prior application and the sixteenth embodiment.
Furthermore, although the prior art example 16 of FIG. 75 uses the reverse series circuit of the transistors 3 and 4 as the bidirectional pull switching means, the pull switching means is used instead of the bidirectional pull switching means. As in the embodiment 6 of FIG. 64 and the embodiment 7 of FIG. 65, an embodiment using “reverse blocking type or reverse conducting type” “pull-up switching means or pull-down switching means” is also possible. is there.

先 ◆ Prior application / example 17 shown in Fig. 76 ◆ ◇
Prior application-example shown in FIG. 76 17 summarizes transistors 33a, 33b, etc. one in the prior application, Example 16 shown in FIG. 75. Therefore, for the "on-off driving means and the bi-directional pull switching means" and the like is the same as that in the prior application, Example 16 of FIG. 75.
In the prior art and embodiment 17 of FIG. 76 , a reverse series circuit of transistors 3 and 4 is used as the bidirectional pull switching means, but instead of the bidirectional pull switching means, the pull switching means is used. As in the embodiment 6 of FIG. 64 and the embodiment 7 of FIG. 65, an embodiment using “reverse blocking or reverse conducting” “pull-up switching means or pull-down switching means” is also possible. is there.

先 ◆ Prior application / example 18 shown in Fig. 77 ◆ ◇
Prior application-example is shown in FIG. 77. 18, is derived from the asynchronous-multilevel AND circuit shown in FIG. 50. Reference: FIG. 11 of JP-A-2005-236985.
◆ ◆ ◆ 1) When H = G + 2 The specific integer for one input is (H + G) / 2. Then, although this prior application example 18 is the “multi-value logic circuit that the present inventor calls a synchronous multi-value NAND circuit”, if the connection of the gate of the transistor 41 is changed from the Q terminal to the Q bar terminal, The prior application example 18 is a "multi-level logic circuit which the present inventor calls a synchronous multi-level AND circuit".
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the inversion / logic operation of the original asynchronous / multilevel logic circuit and its non-inversion / logic operation" is as follows.
◆ a) Inversion, logic operation;
If _all the input integers N _in1 , N _in2 , N _{in3 of the} input terminals T _in1 , T _in2 , T _in3 are integers (H + G) / 2, the output from the output terminal T _out is released, otherwise the output from the output terminal T _out A specific integer m is output. For this reason, the “multi-level logic means having a synchronous latching function” of the prior application and the example 18 of FIG. 77 is referred to as “the synchronous type (multi-level) NAND in which the present inventor sets the specific integer for input to (H + G) / 2”. It becomes a circuit called "circuit".
◆ b) non-inversion, logic operation;
Furthermore, when the gate terminal of the transistor 41 is reconnected from the Q terminal to the Q bar terminal, if all the three input integers N _in1 , N _in2 and N _in3 are integers (H + G) / 2, the output terminal T _out for output A specific integer m is output, otherwise the output from the output terminal T _out is released. For this reason, the “multi-level logic means having a synchronous latching function” of the prior application / example 18 of FIG. 77 is “a synchronous type (multi-level) in which the present inventor sets the specific integer for input to (H + G) / 2”. It becomes a circuit called "AND circuit".

◆ ◆ ◆ 2) When H> G + 2 The two specific input integers are H and G. Then, this prior application example 18 describes that “the present inventor sets“ two input specific integers (values) to H and G as synchronous (multi-value) NAND circuits and NOUT circuits (or synchronous OR · OUT circuits) is a circuit 'called "by changing the connection of the gate of the transistor 41 from the Q terminal to the terminal Q, the prior application, example 18 of Figure 77 is" present inventors' two inputs for a particular integer ( The circuit is called a circuit called “synchronous AND · NOUT circuit (or synchronous NOR · OUT circuit)” in which H and G are values).
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the inversion / logic operation of the original asynchronous / multilevel logic circuit and its non-inversion / logic operation" is as follows.
◆ a) Inversion, logic operation;
If all three input integers N _in1 , N _in2 , N _in3 are “H> N _in1 , N _in2 , N _in3 > G”, the output terminal T _out is opened, otherwise the specific integer for output from the output terminal T _out m is output. For this reason, the prior application example 18 in FIG. 77 shows that “the present inventors set the two-input specific integers (values) to H and G as synchronous (multi-level) NAND / IN circuits (or synchronous OR ··· NIN circuit) is a circuit called ".
◆ b) non-inversion, logic operation;
Furthermore, when the gate terminal of the transistor 41 is reconnected from the Q terminal to the Q bar terminal, all the three input integers N _in1 , N _in2 , N _in3 are “H> N _in1 , N _in2 , N _in3 > G” Nara output terminal T _out certain integer m output from is output and the output from the output terminal T _out if not opened. For this reason, the prior application example 18 further describes that “the present inventors further set“ two input specific integers (values) H and G as synchronous (multi-level) AND / IN circuits (or synchronous NOR / NIN circuits) ”. It becomes a circuit called ")".

◆ ◆ ◆ 3) When the transistors 2a to 2c, 17 and the resistor 20 are removed and the open end of the resistor 62 is reconnected to the drain of the transistor 1c:
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the inversion / logic operation of the original asynchronous / multilevel logic circuit and its non-inversion / logic operation" is as follows.
◆ a) Inversion, logic operation;
If all the three input integers N _in1 , N _in2 , N _in3 are smaller than the integer H, the output from the output terminal T _out is released, otherwise the output specific integer m is output. In other words, if at least one of the three input integers N _in1 , N _in2 , N _in3 is greater than or equal to the integer H, the output specific integer m is output, otherwise the output from the output terminal T _out is open Be done.
Therefore, the prior art example 18 in FIG. 77 "the circuit which the present inventor calls" a synchronous NAND · UNDER circuit (or a synchronous OR · NUNDER circuit) where the specific integer for one input is H "" It is.
◆ b) non-inversion, logic operation;
Furthermore, when the gate terminal of the transistor 41 is connected from the Q terminal to the Q bar terminal in the prior application and embodiment 18 of FIG. 77 , if all three input integers N _in1 , N _in2 and N _in3 are smaller than the integer H, for output A specific integer m is output, otherwise the output from the output terminal T _out is released. In other words, if at least one of the three input integers N _in1 , N _in2 , N _in3 is greater than or equal to the integer H, the output from the output terminal T _out is released, otherwise, for output from the output terminal T _out A specific integer m is output.
Therefore, the prior art example 18 in FIG. 77 “the circuit which the present inventor calls“ a synchronous AND / UNDER circuit (or a synchronous NOR / NUNDER circuit) where the specific integer for one input is H ””. become.

◆ ◆ ◆ 4) When removing the transistors 1a to 1c and reconnecting the source of the transistor 17 to the power supply line V _H :
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the inversion / logic operation of the original asynchronous / multilevel logic circuit and its non-inversion / logic operation" is as follows.
◆ a) Inversion, logic operation;
If all the three input integers N _in1 , N _in2 , N _in3 are larger than the integer G, the output from the output terminal T _out is released, otherwise the output specific integer m is output from the output terminal T _out . In other words, if at least one of the three input integers N _in1 , N _in2 , N _in3 is smaller than or equal to the integer G, the output specific integer m is output, otherwise the output from the output terminal T _out is open Be done.
For this reason, the prior application example 18 in FIG. 77 is a circuit called "the synchronous NAND OVER circuit (or synchronous OR NOVER circuit) where the inventor sets the one specific input integer to G". is there.
◆ b) non-inversion, logic operation;
Furthermore, when the gate terminal of the transistor 41 is connected from the Q terminal to the Q bar terminal in the prior application and embodiment 18 of FIG. 77 , if all three input integers N _in1 , N _in2 and N _in3 are larger than the integer G, for output A specific integer m is output, otherwise the output from the output terminal T _out is released. In other words, if at least one of the three input integers N _in1 , N _in2 , N _in3 is smaller than or equal to the integer G, the output from the output terminal T _out is released, otherwise, for output from the output terminal T _out A specific integer m is output. For this reason, the prior application example 18 in FIG. 77 further states that “the present inventors further described that“ a synchronous AND · OVER circuit (or synchronous NOR. It becomes a circuit called "NOVER circuit".
In the prior art of the embodiment shown in FIG. 77 , although the reverse series circuit of the transistors 3 and 4 is used as the bidirectional pull switching means, pull switching means is used instead of the bidirectional pull switching means. As in the embodiment 6 of FIG. 64 and the embodiment 7 of FIG. 65, an embodiment using “reverse blocking type or reverse conducting type” “pull-up switching means or pull-down switching means” is also possible. is there.

◆ ◆ Prior application · Examples 19 to 21 shown in Figs. 78 to 80 ◆ ◇
Prior application-example shown in FIG. 78. 19, is an application of the "prior application, Example 8 shown in FIG. 66," like the prior application, Example 16 shown in FIG. 75. The prior application · Example 20 (added this time) shown in Fig. 79 is an improvement of the prior application · Example 19 shown in Fig. 78 . Furthermore, although the prior application · Example 21 (added this time) shown in Fig. 80 is a modification of the prior application · Example 20 shown in Fig. 79 from 2 inputs to 3 inputs, the flip flop 27 etc. Not.
Figure 78 - not shown in the prior application, examples 19-21 are shown in 80 but is downstream of the D-type flip-flop 27 in the "prior application, Example 8 shown in FIG. 66," "transistors 41,37, The on / off driving means formed by the diode 39 and the resistor 15 and the bidirectional pull switching means in which the transistors 3 and 4 are connected in series are connected.
Alternatively, D-type "prior application, Example 9 shown in FIG. 67" is in the subsequent stage of the flip-flop 27 to the "on-off shown in any one of the" prior application, Example 14 shown in FIG. 72 " The driving means and the bi-directional pull switching means are connected. However, when using the "on / off driving means and bidirectional pull switching means" shown in the prior art and embodiments 10 and 12 of FIGS. 68 and 70 , a power supply is used instead of the D-type flip flop 27. A voltage doubled D-type flip flop 127 is used.

From here, shown or "Figure 71" prior application, Example 9 shown in FIG. 67, "or" prior application, Example 8 shown in FIG. 66, "each prior application, examples 19-21 shown in FIGS. 78-80 The following four cases will be considered when the "on / off driving means and bidirectional pull switching means" of the prior application example 13 "are connected.
◆ ◆ ◆ 1) If H = G:
In order to make it easy to understand now, each logic operation that “the D input signal of the D-type flip flop 27 and the“ Q output signal, Q bar output signal ”coincide with each other, ignoring the time delay associated with the synchronous operation. That is, the “non-inversion / logic operation of the original asynchronous / multi-level logic circuit and its inversion / logic operation” are as follows.
◆ a) Non-inversion, logic operation;
Since one input specific integer is H, if at least one of the input integers N _in1 and N _in2 of the input terminals T _in1 and T _in2 is an integer H, the output specific integer m is output from the output terminal T _out Otherwise, the output from the output terminal T _out is released. For this reason, the inventor further refers to the "multi-level logic means having a synchronous latching function" of the prior applications and embodiments 19 to 21 shown in FIGS. 78 to 80 as a synchronous (multi-level) OR circuit.
◆ b) Inversion, logic operation;
(In FIG. 66, in FIG. 67, in FIG. 71) transistor 41 in each further prior application, examples 19-21 shown in FIGS. 78-80 if the gate terminal of the connected from the Q terminal to the terminal Q, the input integer If at least one of N _in1 and N _in2 is an integer H, the output from the output terminal T _out is released, otherwise an output specific integer m is output from the output terminal T _out . Thus, "multi-value logic means having a synchronous latching function" the prior application, examples 19-21 shown in FIGS. 78-80 is "further present inventors' synchronous to a specific input integer and H (multi Value) becomes a circuit called “NOR circuit”.

◆ ◆ ◆ 2) If H> G:
In order to make it easy to understand now, each logic operation that “the D input signal of the D-type flip flop 27 and the“ Q output signal, Q bar output signal ”coincide with each other, ignoring the time delay associated with the synchronous operation. That is, the “non-inversion / logic operation of the original asynchronous / multi-level logic circuit and its inversion / logic operation” are as follows.
◆ a) Non-inversion, logic operation;
If at least one of the input integers N _in1 and N _in2 of the input terminals T _in1 and T _in2 is “equal to H or G, or an integer between H and G”, a specific integer m for output from the output terminal T _out Is output, otherwise the output from the output terminal T _out is open. For this reason, the inventor of the present invention has shown the synchronous OR NOUT circuit (or synchronous NAND with H and G specific integers (values) for two inputs as H and G shown in FIGS. 78 to 80 , respectively. · It is called "OUT circuit".
◆ b) Inversion, logic operation;
(In FIG. 66, in FIG. 67, in FIG. 71) transistor 41 in each further prior application, examples 19-21 shown in FIGS. 78-80 if the gate terminal of the connected from the Q terminal to the terminal Q, the input integer If at least one of N _in1 and N _in2 is “equal to H or G, or an integer between H and G”, the output terminal T _out is opened, otherwise a specific integer for output from the output terminal T _out m is output. For this reason, each of the prior applications and Examples 19 to 21 shown in FIGS. 78 to 80 “further indicates that“ the present inventor sets “two input specific integers (values) to H and G, synchronous (multi-valued) NOR / NOUT It becomes a circuit called “circuit (or synchronous AND · OUT circuit)”.

◆ ◆ ◆ 3) When the transistors 32a and 32b, the diode 34 and the resistor 67 are removed:
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the non-inversion / logic operation of the original asynchronous / multilevel logic circuit and its inversion / logic operation" is as follows.
◆ a) Non-inversion, logic operation;
Of the input integer _{N in1, N in2} input terminal _{T in1, T in2,} at least one output is specified integer m output from the output terminal _{T out} if or equal to an integer smaller than H, from the output terminal _{T out} if not Output is released.
In other words, if both of the input integers N _in1 and N _in2 are larger than the integer H, the output from the output terminal T _out is released, otherwise the output specific integer m is output.
Therefore, the present inventor has each prior application, examples 19-21 shown in FIGS. 78-80 "synchronous OR-Nover circuit for the one input for a specific integer and H (or synchronous NAND-OVER circuit) I call it ".
◆ b) Inversion, logic operation;
(In FIG. 66, in FIG. 67, in FIG. 71) transistor 41 in each further prior application, examples 19-21 shown in FIGS. 78-80 if the gate terminal of the connected from the Q terminal to the terminal Q, the input integer If at least one of N _in1 and N _in2 is smaller than or equal to the integer H, the output from the output terminal T _out is released, otherwise the output specific integer m is output from the output terminal T _out .
In other words, if both of the input integers N _in1 and N _in2 are larger than the integer H, the output specific integer m is output, otherwise the output from the output terminal T _out is released.
For this reason, each of the prior applications and Examples 19 to 21 shown in FIGS. 78 to 80 “in addition,“ the inventor further described that “the synchronous NOR · NOVER circuit (or synchronous AND · OVER for which one specific input integer is set to H It becomes a circuit called "circuit)".

◆ ◆ ◆ 4) When the transistors 31a, 31b, 33a, 33b, the diodes 35, 68a, 68b and the resistors 20a, 20b, 62 are removed:
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the non-inversion / logic operation of the original asynchronous / multilevel logic circuit and its inversion / logic operation" is as follows.
◆ a) Non-inversion, logic operation;
Of the input integer _{N in1, N in2} input terminal _{T in1, T in2,} at least one output is specified integer m output from the output terminal _{T out} if greater than or equal to integer G, from the output terminal _{T out} if not Output is released.
In other words, if both of the input integers N _in1 and N _in2 are smaller than the integer G, the output from the output terminal T _out is released, otherwise the output specific integer m is output.
Therefore, the present inventor has each prior application, examples 19-21 shown in FIGS. 78-80 "synchronous OR-Nunder circuit for the one input for a specific integer and G (or synchronous NAND-UNDER circuit) I call it ".
◆ b) Inversion, logic operation;
(In FIG. 66, in FIG. 67, in FIG. 71) transistor 41 in each further prior application, examples 19-21 shown in FIGS. 78-80 if the gate terminal of the connected from the Q terminal to the terminal Q, the input integer If at least one of N _in1 and N _in2 is greater than or equal to the integer G, the output from the output terminal T _out is released, otherwise the output specific integer m is output. In other words, both the input integer _{N in1, N in2} certain integer m output from the output terminal _{T out} if integer G smaller is output and the output from the output terminal _{T out} if not opened.
For this reason, each of the prior applications and Examples 19 to 21 shown in FIGS. 78 to 80 “in addition,“ the inventor further described that “the synchronous NOR · NUNDER circuit (or synchronous AND · UNDER circuit in which the specific input integer for one input is G). "Circuit" is called "circuit".
In each of the prior applications and Examples 19 to 21 shown in FIGS. 78 to 80 , reverse series circuits of the transistors 3 and 4 are used as the bidirectional pull switching means. using "pull-up switching means or pull-down switching means" as in the example 7 example 6 and FIG. 65 in FIG. 64 of the 'reverse blocking or reverse conduction type "as a pull switching means instead Embodiments are also possible.

先 ◆ Prior application / example 22 shown in Fig. 81 ◆ ◇
The prior application / Embodiment 22 shown in FIG. 81 is an application of the embodiment of FIG. 13 of JP-A-2005-236985.
◆ ◆ ◆ 1) When H = G + 2 The specific integer for one input is (H + G) / 2. Then, although the prior application and embodiment 22 shown in FIG. 81 are “multi-level logic circuit that the present inventor calls synchronous multi-level NOR circuit”, connection of the gate of transistor 41 is from Q terminal to Q bar terminal. If it is changed, the prior application · 22 shown in FIG. 81 becomes a "multi-level logic circuit which the present inventor calls a synchronous multi-level OR circuit".
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the inversion / logic operation of the original asynchronous / multilevel logic circuit and its non-inversion / logic operation" is as follows.
◆ a) Inversion, logic operation;
If at least one of the input integers N _in1 , N _in2 , N _in3 of the input terminals T _in1 , T _in2 , T _in3 is an integer (H + G) / 2, the output from the output terminal T _out is opened, otherwise the output terminal A specific integer m for output is output from T _out . For this reason, the “multi-level logic means having a synchronous latching function” of the prior application and the example 22 shown in FIG. 81 is “a synchronous type (multi-level logic unit in which the present inventor sets the specific integer for input to (H + G) / 2) ) A circuit called “NOR circuit”.
◆ b) non-inversion, logic operation;
Further, when the gate terminal of the transistor 41 is reconnected from the Q terminal to the Q bar terminal, the output terminal T if at least one of the three input integers N _in1 , N _in2 , N _in3 is an integer (H + G) / 2. _The output specific integer m is output from out, otherwise the output from the output terminal T _out is released. For this reason, the “multi-level logic means having a synchronous latching function” of the prior application and the example 22 shown in FIG. 81 is “a synchronous type (multi-level logic unit in which the present inventor sets the specific integer for input to (H + G) / 2) It becomes a circuit called "OR circuit".

◆ ◆ ◆ 2) When H> G + 2 The two specific input integers are H and G. Then, the prior application example shown in FIG. 81 shows that “the present inventors set“ two input specific integers (values) to H and G as synchronous (multi-level) NAND circuit and NOUT circuit (or synchronous OR · OUT circuit) "and called is a circuit", by changing the connection of the gate of the transistor 41 from the Q terminal to the terminal Q, the prior application, example 22 shown in FIG. 81, "the present inventors' two It is a circuit called “synchronous AND · NOUT circuit (or synchronous NOR · OUT circuit)” in which the input specific integers (values) are H and G ”.
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the inversion / logic operation of the original asynchronous / multilevel logic circuit and its non-inversion / logic operation" is as follows.
◆ a) Inversion, logic operation;
The output terminal T _out is opened if at least one of the three input integers N _in1 , N _in2 and N _in3 is “the integer between H and G> G”, otherwise the output terminal T _out for output A specific integer m is output. For this reason, the prior application example 22 shown in FIG. 81 is referred to as “a synchronous (multi-valued) NOR / IN circuit (or synchronous AND where the present inventor sets two input specific integers (values) as H and G).・ A circuit called “NIN circuit”.
◆ b) non-inversion, logic operation;
Furthermore, when the gate terminal of the transistor 41 is reconnected from the Q terminal to the Q bar terminal, at least one of the three input integers N _in1 , N _in2 , N _in3 is “an integer between H and G> If G ", the output specific integer m is output, otherwise the output from the output terminal T _out is released. For this reason, the prior application · Example 22 shown in FIG. 81 “Furthermore,“ The present inventors set “two input specific integers (values) to H and G as synchronous (multi-level) AND / IN circuit (or synchronous type It becomes a circuit called “NOR · NIN circuit”.

◆ ◆ 3) In the prior application example 22 shown in FIG. 81 , the transistors 2a to 2c, 17a to 17c, three diodes in the figure and the resistors 20a to 20c are removed, and all drain terminals of the transistors 1a to 1c are connected. If the open end of resistor 62 is reconnected to its common drain terminal:
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the inversion / logic operation of the original asynchronous / multilevel logic circuit and its non-inversion / logic operation" is as follows.
◆ a) Inversion, logic operation;
If at least one of the three input integers N _in1 , N _in2 and N _in3 is smaller than the integer H, the output from the output terminal T _out is released, otherwise the output specific integer m is output. In other words, if each of the three input integers N _in1 , N _in2 , N _in3 is equal to or larger than the integer H, the output specific integer m is output, otherwise the output from the output terminal T _out is released.
For this reason, the prior application · Example 22 shown in Fig. 81 is a circuit which the present inventor calls "the synchronous NOR · UNDER circuit (or synchronous AND · NUNDER circuit) where the specific integer for one input is H". ".
◆ b) non-inversion, logic operation;
Furthermore, in the prior application / example 22 shown in FIG. 81, when the gate terminal of the transistor 41 is connected from the Q terminal to the Q bar terminal, at least one of the three input integers N _in1 , N _in2 and N _in3 is an integer H If it is smaller, the output specific integer m is output, otherwise the output from the output terminal T _out is released. In other words, if each of the three input integers N _in1 , N _in2 , N _in3 is equal to or larger than the integer H, the output from the output terminal T _out is released, otherwise the output specific integer m is output.
Therefore, the prior art example 18 in FIG. 77 “the circuit which the present inventor calls“ a synchronous OR · UNDER circuit (or a synchronous NAND · NUNDER circuit) where the specific integer for one input is H ””. become.

◆ ◆ ◆ 4) When the transistors 1a to 1c are removed and all the sources of the transistors 17a to 17c are reconnected to the power supply line V _H :
In order to make it easy to understand now, the logic in each case that the D input signal of the D-type flip flop 27 and the "Q output signal, Q bar output signal" coincide with each other, ignoring the time delay associated with the synchronous operation. The operation "that is, the inversion / logic operation of the original asynchronous / multilevel logic circuit and its non-inversion / logic operation" is as follows.
◆ a) Inversion, logic operation;
If at least one of the three input integers N _in1 , N _in2 and N _in3 is larger than the integer G, the output from the output terminal T _out is released, otherwise the output specific integer m is output. In other words, if each of the three input integers N _in1 , N _in2 , N _in3 is equal to or smaller than the integer G, the output specific integer m is output, otherwise the output from the output terminal T _out is released.
For this reason, the prior application · 22 shown in FIG. 81 is a circuit which the present inventor calls "a synchronous NOR OVER circuit (or a synchronous AND · NOVER circuit) where the specific integer for one input is G". ".
◆ b) non-inversion, logic operation;
Furthermore, in the prior application / example 22 shown in FIG. 81, when the gate terminal of the transistor 41 is connected from the Q terminal to the Q bar terminal, at least one of the three input integers N _in1 , N _in2 and N _in3 is an integer G If it is larger, the output specific integer m is output, otherwise the output from the output terminal T _out is released. In other words, if each of the three input integers N _in1 , N _in2 , N _in3 is equal to or smaller than the integer G, the output from the output terminal T _out is released, otherwise the output specific integer m from the output terminal T _out Is output.
For this reason, the prior application example 22 shown in FIG. 81 is referred to as "Furthermore, the present inventors call it" synchronous OR · OVER circuit (or synchronous NAND · NOVER circuit) where the specific integer for one input is G ". It becomes a circuit.
Although in the prior application / Embodiment 22 shown in FIG. 81 , a reverse series circuit of transistors 3 and 4 is used as the bidirectional pull switching means, pull switching is used instead of the bidirectional pull switching means. It is also possible to use an embodiment using the "reverse blocking type or reverse conducting type""pull-up switching means or pull-down switching means" as in the embodiment 6 of FIG. 64 or the embodiment 7 of FIG. 65 as means. It is.

先 ◆ Prior application / example 23 shown in Fig. 74 ◆ ◇
In the prior application / embodiment 23 shown in FIG. 74 , the synchronous signal generating means 60 (= synchronous signal supply means) and the D-type flip flop 70 receive power supply from the same power supply lines V ₀ and V ₋₁ .
The on / off driving means is composed of transistors 71 and 72, a diode 39 and a resistor 15, and the bidirectional pull switching means is composed of transistors 73 and 74.
Furthermore, instead of "numerical value determination means formed by transistors 1, 2, 17 and resistors 20, 62", "numerical value determination means formed by transistors 31 to 33, diode 34 and resistors 20, 62 , 67 in FIG. "Figure 75 in transistor 31a~33a, 31b~33b, diodes 34,35A, 35b and resistors 20a, 20b, numerical discriminating means 62, 67 constitutes" transistors in "Figure 76 31a~32a, 31b~ An embodiment using “numerical value determination means constituted by 32b, 33, diode 34, 68a, 68b and resistors 20, 62, 67” is also possible.
Then, in place of each of the power supply lines V ₋₁ and V ₀ shown in FIG. 74 , each of the power supply lines V ₀ and V ₁ is used, that is, the respective power supply potentials are raised one by one. 39 and the resistor 15 can be removed, and the drain terminal of the transistor 71 can be used as the output terminal T _out . In this case, there is also a case where "the transistor 71 is used as a reverse conduction type pull down switching means by forming its built-in diode" or "a reverse blocking diode is connected in series to the transistor 71 to reverse block this series circuit. There is also a case where it is used as a type pull down switching means. (Another embodiment)
Or, although there is a difference between the N-channel type and the P-channel type, as in the prior application and the seventh embodiment of FIG. 65 , “the diode 12 is used instead of the transistor 74 and the reverse blocking type pull down switching means Alternatively, “the transistor 74 may be removed and the source terminal of the transistor 73 may be used as the output terminal T _out to constitute a reverse conduction type pull-down switching means”. (Derivative example)
Or, although differences in N-channel and P-channel type there, similarly to the previous application, Embodiment 6 of FIG. 64 and remove the "transistor 73, reverse conducting directly connected to the source or the like of the transistor 74 to the power supply line V _m constituting the pull-up switching unit "or remove the" transistor 73, directly connected to the source or the like of the transistor 74 to the power supply line V _m, the diode 10 inserted and connected between the drain and the output terminal T _out of the transistor 74 Thus, the reverse blocking pull-up switching means can be configured by the transistor 74 and the diode 10.
(Derivative example)

◆ ◆ Prior application · Example 24 ◆ ◇
Another embodiment (not shown) will be described. In the multi-valued logic circuit of FIG. 9 of Japanese Patent Application Laid-Open No. 2005-236985 (Patent Document 3), the aforementioned “First application shown in FIG. 59 ” does not include the diode 26 and the resistor 27. 59. Insert the D-type flip flop 27 in the previous application and example 1 of FIG. 59 between “the connection point of the resistor 23 and“ the gate of the transistor 24 ”and connect it, etc. off speed those expedited in the transistor 37 or the like prior application, in example 1 of FIG. 59 "is.
Similarly, the same is applied to each of the multi-valued logic circuits shown in FIG. 11, FIG. 13, FIG. 17, FIG. 20, FIG. 23 (b) and FIG. Each example is possible.
That is, Figure 17 of JP 2005-236985, the two there PMOS in each multi-valued logic circuit of FIG. 20, similarly "split supply line between the front of the PMOS drain and subsequent PMOS gate _{V m + 1} · Insert and connect the D-type flip flop 27 "supplied with power from V _m .
Further, the front stage of the drain and the subsequent PMOS similarly "split supply line _{V m + 1} · between the gate of the" PMOS having an input terminal In4 "in multi-valued logic circuit of FIG. 23 of JP-2005-236985 (b) A D-type flip flop 27 "supplied with power from V _{m is} to be inserted and connected.
Furthermore, in the multilevel logic circuit of FIG. 25 (b) of JP 2005-236985 A, similarly, power is supplied from both power supply lines V _{m + 1} and V _m between the drains of the four PMOSs of the former stage and the gates of the latter stages. The inserted D-type flip flop 27 "is to be inserted and connected.
In the same manner as “the prior application shown in FIG. 59 and the first application derived from the first embodiment shown in FIGS. 60 to 65 and the second embodiment to the seventh embodiment shown in FIGS. Alternatively, the pull switching means may be changed to the reverse conduction type or the reverse blocking type, or the power supply line connecting one of the switch terminals of the pull switching means may be changed. Respectively derived embodiments which are further derived from the respective embodiments of the present invention derived from the respective embodiments of the 2005-236985 are possible. Then, the respective embodiments or the turn-off of the bidirectional switching means in the transistor 37 or the like as the well-present invention on each, derived Example "prior application, the first embodiment shown in FIG. 59" of these invention Fastened alternatives are also possible. (Derivative example)
In other words, there are respective derived embodiments with and without the transistor 37 and the like.

Regarding the first and second inventions, finally, the data input part (eg, the input part of the D terminal) of the binary synchronous flip flop means which is one of the constituent means is The binary synchronous flip-flop means doubles as the numerical discrimination means if it satisfies the requirements of the numerical discrimination means for discriminating "large or large" or "small or small" than the input specific integer. Of course it does not matter.
Further, as an additional effect, since synchronous latching can be performed in multi-valued logic means / unit, there is flexibility in the way of setting up the entire circuit, and the options of the whole circuit configuration increase, which is convenient. Conventionally, it has been necessary to provide a multi-level synchronous latching circuit between the multi-level circuit and the multi-level circuit.
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆ ◆ ◆
As described above, various multilevel logic circuits based on the principle of hoody algebra, "multilevel logic means having synchronous latching function and multilevel hazard removal means", etc. of Japanese Patent Laid-Open No. 2012-075084 of Patent Document 7 will be described in the present invention. The present inventors have described those techniques and the like in the paragraph numbers [ 0164 to 0284 ] just in case, so that they can be treated in the same manner as the technical common sense.
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆

◆ ◆ ◆ ◆ ***** Various new and multivalued logics that can express "ambiguity" ***** ◆ ◆ ◆
***
● ● 25) 8 new multi-valued logics, “multi-valued OVER logic, multi-valued NOVER (knowr) logic, which were not found in the concept before that, which the inventor created in FUJI algebra By using multi-level logic circuits such as multi-level UNDER logic, multi-level NUNDER logic, multi-level IN logic, multi-level NIN logic, multi-level OUT logic, and multi-level NOUT logic Ambiguity can be defined and expressed freely and flexibly. The other various logics derived from these eight logics are described in paragraph numbers [ 0244 to 0252, 0262 to 0266 ].
For example, “ambiguity” can be freely and flexibly defined or expressed freely, as described below, using each of these multi-valued logic circuits.
◆ Example 1: In the case of expressing it as “numerical value of this side” in logical numerical terms. Among "0 to 9", "3 to 5" or "4 to 6" or "<2" or "7 <".
◆ Example 2: Yes (→ numerical value 9), No (→ numerical value 0) It can not be said either, and the case without either is expressed by numerical value "4, 5".
◆ Example 3: In the case of expressing “Somewhat yes, yes”. "6 to 7" when it is defined that "Numerical value 9 is Yes" and "Numerical value 0 is No".
◆ Example 4: In the case of expressing "If you say No". "2 to 3" when "number 9 is defined as Yes" and "number 0 is defined as No".
◆ Example 5: In the case of expressing “gray innocence close to conviction (→ numerical value 0) infinitely (→ numerical value 1)” by saying “in doubt to the accused's benefit”. In other words, when the number 0 means "complete guilty (full black)" and the number 9 defines "complete innocence (full white)", the number 1 expresses "infinitely guilty gray innocence" If.
***
After that, "the person who uses these various new / multi-valued logics" can freely define and express the meaning of each numerical value as they like and in any way.

The number of corresponding input integers in each multilevel logic circuit of “multilevel OVER logic, multilevel UNDER logic, multilevel IN logic, multilevel OUT logic” is, for example, “the specific integer value for input is 4”. In the case of narrowing down three of the corresponding integers 5, 6 and 7 gradually from one to one in the multi-level IN logic of 8 ", each multi-level logic becomes a multi-level EVEN logic.
→ → The first six lines of paragraph number [ 0215 ] mentioned above.
In other words, because the narrowing means focusing from “fuzziness” to “definition” just like “focusing from“ blurring ”to“ matching ”of the focus of the photo,“ OVER logic, NOVER (NOVER ( Know bar) logic, UNDER logic, NUNDER logic, IN logic, NIN logic, OUT logic, NOUT logic, and “each of these multilevel logics and multilevel AND logic or multilevel OR logic The present inventors consider that expressing “ambiguity” by combinational logic is out of focus, not out of focus, and appropriate for reason.
So, using these multilevel logic and “combination of these multilevel logic and multilevel AND logic or multilevel OR logic”, a new “fuzzy logic (completely different from conventional fuzzy logic and fuzzy control technology The inventor believes that IMy [aimai]-Logic) and "fuzzy control technology (IM y [aimai]-Control-Technology)" can be developed.
Because, in the conventional fuzzy control theory, in order to express "fuzziness" in "numbers 0, 1 that clearly express YES and NO", "mathematical theory of probability and statistics" is introduced into Boolean algebra, In general, it is quite complicated and difficult to understand.
Also, since the statistics / probability itself does not yet exist with regard to “fuzziness” that a person (person) first defines and expresses as himself or “fuzziness” used unintentionally in the first place, the “fuzziness” It is impossible at all to define and express "" in conventional fuzzy logic. That is, there is a limit to the conventional fuzzy logic, and there is an impossibility.
Incidentally, as it is immediately understood from the pronunciation of [aimai], the English name IMy [aimai] is so named from the combination of the word name “fuzzy” of the Japanese name, that is, the present inventor.

◆ ◆ ◆ ◆ ***** New concept computer that does not use programs ***** ◆ ◆ ◆
***
◆ ◆ ◆ ***** New Concept Computers
not to use programs etc. **** ◆ ◆ ◆ ◆
***
●● 26) The present inventors have applied the “pre (pre) processing results” in their prior application invention [Japanese Patent Laid-Open No. 2007-035233] as “multi-concept related computer without new program, software, CPU, etc.” as multi-value related technology. A memory type (alias: input / output pattern memory type or functional memory type or processing result memory type) decimal computer (= Decimal Computers), binary computer, etc. are disclosed.
→ → (Decimal or binary, etc.) Computers of 'Processing-Result or Pre-Processing-Result'- Memorizing-Type etc. → → New Concept Computers
The present inventor was calling the type 'The Processing-Result-Memorizing-Type' or 'The Pre-Processing-Result-Memorizing-Type' (Input-Output-Pattern-Memorizing-Type or Function-Memorizing-Type 'in another name ).
In addition, before (pre) processing is collected before (pre) collection of information in advance, naturally, before (pre) processing result before (before) processing result before (before) information processing result Information collection results are also included. Regardless of whether it is the previous information processing result, the previous information collection result, the input / output pattern, or the function, one or more 'input data or input information' and 'one or more' Since the "output data or output information" relationship and new software representing correlation will be used, the "big data" often heard recently can be the new software as it is. Yes, that is, the compatibility between the new concept computer and its "big data" is outstanding.
'The Pre-processing' means 'pre-processing data or information' or 'pre-collecting data or information'.
In other words, 'Meanings of The Pre-processing' include 'pre-processing data or information' and 'pre-collecting data or information'.
The present inventor thinks that 'Big Data to become often a topic of conversation recently' can directly become 'Presult Software' written below.
The present inventor calls 'The Pre-processing Result Software''The Presult Software' for short.
So, in a word, Big Data fit the New Concept Computers very much.

No, how to say that, the expression is not correct. To be precise, it is quite natural. Because that big data is a part of the processing result software before that. What has been arranged by the big data is a part of the processing result software before that, and the big data is not useful at all unless it is arranged like a truth table, information collection and data It is because there is no meaning to collect.
No, that expression isn't right! Exactly speaking, it's quite natural! ! ! Because the Big Data are a part of 'The Presult Software'.
"Because of the Big Data are in the Big Data are not Part of the Big Data", and because, if the Big Data are placed in the order like truth tables, the Big Data are not usefulness and no meaningful to pre-collect them at all.
In the new concept computer, "pre-processing result software (abbreviated as" pre-form (or result) software (Presult Software) "will be called. } (Alias: input / output pattern software or function software or simply result software) and multi-valued logic circuits.
→ → ★ Presult-Memorizing-Type Computers
The Presult-Momorizing-Type Computers use 'The Presult Software' and multivalue logic circuits etc. .
Also, programming is equivalent to “Pulsating (or praising) = Presulting” (alias: patterning or functionaling or resulting), and programmers are equivalent to “Pulsarator (or pleader) = Presulter” (Pulvering). Alias: Patner or Functional or Reporter).
'The Presulting' means 'producing the Presult Software', and 'The Presulters' mean 'people producing the Presult Software'.

From the above, it is not necessary to think that "data scientist", which is often referred to recently in big data, as a big word difficult, and the inventor thinks that it is a simple story. Because, as mentioned above, the cells of the large truth value table (Marsume, empty column) are simply “permanently persevered in a steady way (jimichi)? Or efficiently using a computer "Because it is just a story to fill in with numbers. If all the big data are in place, you can complete the truth table.
The truth table represents the relationship between one or more inputs "data or information" and one or more outputs "data or information", and a logic function itself representing correlation. The inventor further believes that the big data can be directly analyzed using a presult memory type computer based on the truth table.
→ → Paragraph numbers [ 0122 to 0125, 0138 to 0139 ] described above and Patent Document 8 below.
The usage of the big data, for example, simply makes the result of a certain logic function a one-dimensional to three-dimensional graph or the like to make it easy to visually grasp "the tendency indicated by the big data".
Or effectively, “the result of inputting one or more inputs“ data or information ”to the logic function 1”, ie “the one or more outputs“ data or information ”” to the logic function Enter 2 Further, one or more outputs “data or information” of the logic function 2 are input to the logic function 3. As a result, the relationship between the “first one or more inputs“ data or information ”” and the one or more outputs “data or information” of the logic function 3 is newly obtained. (→ → new, logic function.) If necessary, continue with logic functions 4, 5.
At that time, it is not necessary to always use the entire "data or information" of each logic function, but there is also a usage that uses only the necessary part of each logic function. In short, only the "data or information" having correlation with each other are efficiently combined, and each logical function is generated in which each set is represented one by one in a large truth table. Then, each logical function is configured one by one with a multi-valued logic complete circuit. After that, these multi-valued logic complete circuits can be used alone or in combination to determine the "increase tendency, decrease tendency or increase / decrease tendency" of the "total logic function to be determined" or "minimum value, maximum value, minimum value or maximum condition under any condition" Make it easy to visually grasp "it becomes a value".
It should be noted that the present inventors think that the people who are called "data scientists" by the present inventor at first are "patterners or functioners", halfway through "reporters", and recently "pre-salters (or pre-sulters) = Presulter" themselves. ing.
In addition, when all the "data or information" to be collected is not complete, "If there is a blank space in the truth table to be created, find each blank data from the average value of the data of that circle. The present inventor thinks that it will be determined from the increase / decrease tendency (differentiation) of data around it.
Furthermore, if big data is handled by a computer, it is natural that using a prepare (or presult) memory type computer instead of a conventional program memory type computer is directly connected, and the processing speed is overwhelming. Fast.
Then, although the prepare (or prepare) memory type computer must initially use the binary system, it is better to use the multiple system, especially the decimal system, as described above (paragraph numbers [ 0122 to 0124 ]).・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Super-astronomical truth table representing, constructing multi-valued logic complete circuit corresponding to it, communication of "big data or big information" going to be huge in the future It is extremely convenient and necessary to perform and process information.

** Patent document 8 (Japanese Patent Application Laid-Open No. 2007-035233)
(JP2007-035233A). Paragraph number (= Paragraph number) [0003-0004, 0024-0034, 0082-0084].
→ → New Concept Computers and Multivalued Computers, specialy Decimal Computers.
→ → Their memories have functions to convert 'input-data or input-information' into 'output-data or output-information'.
** Patent document 22: Japanese Utility Model Application Publication No. 2-5937 ■ *
"Multi-valued logic driver", 1990 year.
* ◆ Nonpatent document 15: Nikkei Electronics (issued on December 18, 1972) ◆ *
(P. 116-p. 126), "Electronic fuel injection system for engines using MOS-ROM (to reduce exhaust gas pollution of automobiles)".
An electronic device to use MOS-ROMs and to inject fuel for an automobile engine. The purpose is to decrease pollution by its exhaust gas.
→ → Three-dimensional "information or data" representing the relationship between two-dimensional input "information or data" and one-dimensional output "information or data".
→ → 3 dimensions-'information or data' to express relations between 2 dimensions-input-'information or data' and 1 dimension-output-'information or data'.
Written by Malcolm Williams {Joseph Lucas (Electrical) Ltd. }.
“NIKKEI ELECTRONICS DEC. 18, 1972”, published by Nikkei Business Publications, Inc. in Japan. (From an article of “Electronics”)
* ◆ Nonpatent document 16: "How to use IC memory" ◆ *
"Chapter 7: Application Examples of IC Memory", Author: Matsuo Nitta, Ryoichi Omote, published by Sankei Gazette Co., Ltd. on June 20, 1978 (June 20, 1978 year).
Memories have functions to convert 'input-data or input-information' into 'output-data or output-information'.
* ◆ Nonpatent document 17: Nikkei Electronics No. 1125 ◆ *
(P.12 to p.13), “Toshiba proposes an architecture that calculates and stores only with memory, and uses STT-MRAM with high speed and low power consumption”. Writing: Masahide Kimura, published on January 6, 2014.
'Toshiba suggest's an architecture to calculate and memorize something needy by using only memories. Those are fast-&-low-power STT-MRAMs. 'This article was written by Masahide Kimura.
“NIKKEI ELECTRONICS No. 1125, JAN. 6, 2014”, published by Nikkei Business Publications, Inc. (In Japan).
* ◆ Nonpatent document 18: Nikkei Electronics No. 1151 ◆ *
(P. 57-p. 70), “Big Data and the Nature of IoT Hitachi's Reach”. Writing: Kazuo Yano, published on January 5, 2015.
'Big-Data and IoT', 'Essential qualities at which Hitachi has arrived'. Written by Kazuo Yano.

In the case of the conventional computer, for example, since "the content to be processed by the information processing" is given, the information processing is started and the result is output, so a long information processing time is required from the start to the result. On the other hand, in the case of this new concept computer, it is known in advance whether "the content to be processed by all of them" is known or completely understood, and "the content to be processed by all the information is processed" Pre) Information processing (processing) result (Result), that is, “Pleass (= Presult. Or Palisade)” is already stored in the memory area, so "For each content part to be input" (only), only "reads corresponding to it" is read out. For this reason, it is extremely obvious that, from the outside of the computer, the information processing speed is overwhelmingly fast. Whether it looks or not, it is extremely advantageous in real time processing because its information processing speed is practically overwhelmingly fast.
→ → International standardization of in-vehicle computer in paragraph number [ 0294 ] described later.
In the future, “this new concept“ Presult ”storage type computer” and “conventional program storage type (or built-in type) computer” may become (the former may become super-... Super-overwhelmingly high performance) Although the inventor thinks that there is a “size of the storage capacity that is permitted or required”, “high priority of information processing speed”, “necessity of using multi-valued logic” "The state of improvement and progress of 3D technology of IC and LSI""The state of improvement and progress of each performance such as MOS and FET""In terms of power saving""Requirement for cooling necessity or heat generation suppression" The present inventor is convinced that “the application fields of both can be distinguished from each other” by “the easiness of software creation”, “the condition of occurrence of a bug” or “resistance to an intrusion operation” or the like. There is.
Then, the present inventor is convinced that "in the future, there is a case where both methods are used in an organic combination in a good arrangement of both methods."

In the case of the conventional program storage type computer, quite a lot of instructions (instructions) are processed for "information processing for the input contents" every time, so a considerable amount of power is consumed. The CPU is in the heater state. On the other hand, in the case of a result (Presult) storage type computer, since "information processing for the input contents" can be performed by only one memory access each time, the power consumption can be overwhelmingly reduced. That's why replacing program storage computers around the world with Presult storage computers can save huge amounts of power. How much energy will it save at a nuclear power plant? ? No, since the power consumption in the information processing field and the information communication field etc. is expected to increase exponentially in the future, the saved power will be for the nuclear power plant / dozens (or hundreds) Is it? ?
However, the inventor thinks that utilization of a nuclear power plant can not be avoided from the viewpoint of global warming prevention. In particular, considering "the recent heavy rain damage" and "the further heavy rain damage caused by the expected future monster typhoon etc.", its use is a pressing issue. I think it is a matter of balance between global warming prevention and nuclear power generation avoidance. In addition, solar power such as solar cells may not be very useful for preventing global warming because it is expected that rain and cloudiness will increase (!?).
In addition, in the case of the conventional program storage type computer, with regard to the resistance to the unauthorized operation, the unauthorized intruder abuses “each command, each application software, each system software such as OS, etc. possessed by the computer to which the computer is to be invaded”. It would be possible, if unprotected, to completely control the computer with "a relatively small malicious program compared to the total amount of programs in the system". On the other hand, in the case of the sample storage type computer, if it is intended to completely control the computer completely, what is considered now is that it is necessary to rewrite the whole of the result software (= Presult Software). The inventor believes that it is almost impossible to completely dominate the.
Furthermore, regarding the storage capacity of the program storage type computer, for example, in the automotive field, the program has reached tens of millions of lines (→ several times as much as converted to its memory address?), And the required storage capacity However, it has become overwhelmingly more advantageous to use a Presult memory type computer, so its full use will gradually come into view.
Then, it is considered that the compatibility between the sample storage computer and the cloud computer is good. The reason is that the cloud computer side absorbs and bears the amount of memory capacity required.
However, it should be noted and warned that the use of the cloud computer is that the client itself provides the offer software (→ big data or big information) about itself for free. The reason is that, in the future, the inventor thinks that the end of the information collection will be the construction of the Clone-Artificial-Intelligence of the client. is there.
For example, when a company uses an external cloud computer in business, if "big data or big information" about the company passes to a third party, the clone company (Clone Company) of that company is strong Because there is a risk of appearing as a rival. The only way to prevent that would be to own a cloud computer on your own.
◇ 顧 顧 ■ み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 大 み て 大 大 み て 大 大 大 み て み て み て み て み て み て み て み て み て み て み て み て み て ■ み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て み て. ! !
Losing great interest by losing interest to small interests. Chinese proverbs.
***
And, in the case of personal use, well, so far, there is no way to go so far, the construction of very small Clone-Artificial-Intelligence leads to infringement of privacy. There is a risk of The inventor is very concerned about such a thing. After all, the inventor thinks that the fear is widely known in the world and "each personal computer returns to the type in which the OS is built in as usual" or the like.
By the way, even in the field of fuzzy control, all functions used in fuzzy control, characteristic curves, operations, etc. can be represented by a large truth table, so it goes without saying that this new concept computer Fuzzy control can also be performed using.
Also, with regard to the neuro computer (or neural network computer), if the memory capacity is increased enormously and rapidly, the memory capacity increase will eventually lead to the inventors that the neuro computer will become a precise memory type computer. Is thinking.
The reason is that the inventor thinks that the computer which has saved the memory capacity of the reserve memory type computer by a large amount of (super ・ ・ ・ ・ super ・) while being variously devised is a neuro computer. It is. If this idea is correct, the savings will, of course, introduce errors into the computer, so the neuro computer will have (super) precise, fine mechanical control (eg engine control, rocket control etc). I will not go for it.

◆ ◆ ◆ ◆ *** * Information processing means to make malicious programs harmless *** * ◆ ◆ ◆ ◆
***
◆ ◆ ◇ ** Information-processing-means
to be able to treat unjust-
programs as harmless rubbish ** ◆ ◆ ◆
***
●● 27) The inventor of the present invention has disclosed “the information processing means having the function of preventing unauthorized operation” in the prior invention “Japanese Patent Application No. 2006-190239 (◆ spontaneous withdrawal)” as a multi-value related technology. The inventor of the present invention voluntarily canceled the invention of the prior application because it has become an urgent situation such as cyber terrorism and cyber warfare in recent years.
● ○ 27) The present inventor is disclosing “Information-processing-means with working to prevent unjust-invasion-operation” in his prior invention 'JP2006-190239 A' as a relative technology to multivalue.
(But he voluntarily withdrew the prior invention, because “Crises such as a cyber terrorism and a cyber war, etc.” were progressively starting in to come during these several years.)
This prior application technology is based on the idea that "If an unauthorized entry is not tampered with, it is OK".
This prior invention-technology is on the basis of a simple-and-original idea of "that it's all right for no unjust program to be able to operate a computer system even if every unjust program can invade it".
For example, in this information processing means, an "instruction (instruction), program or command expressed by a ternary expression (eg, at least one digit of the machine language must be the numerical value 2) which can be clearly distinguished from a binary expression. A filter means that can only pass what is represented by a binary expression (eg, clamp diode) when using "etc." and incorporating "external data or external information" represented by a completely unreliable binary expression " Hardware means, etc.)).
For example, this information-processing-means uses "its instructions, programs or commands, etc." expressed by 3value-expression which can clearly be distinguished from 2value-expression.
In the 3 value expression, for instance, at least one digit of each machine language is numerical value '2'.
And this information-processing-means takes outside-data-or-outside-information into its own through its filter means, when taking that thereinto.
But The outside-data-or-outside-information aren't perfectly reliable and are expressed by 2value-expression.
And the filter means can pass only digital signals expressed by 2value-expression. As examples of the filter means, there are some hardware means such as clipping diode and so on.
That is, in this information processing means, only the "instruction (instruction), program or command" or the like expressed in three values is the target of the execution, and the internal or external "data or information" expressed in binary is the information The object of processing, and the binary expression "external data or external information" is included in the object of the input.
Namely, in this information-processing-means, "only the instructions, programs or commands, etc. expressed by the 3 value" are its object of execution, and "the inside-and-outside data-or-information expressed by the 2 value" are their object of information processing, and “the outside data—or information expressed by the 2 value” include its objects of input.
Then, the external reliable “[instruction (instruction), program or command] or the like, or data or information] expressed by a ternary expression that can be clearly distinguished from the binary expression is“ separate dedicated another Input / output from "I / O port".
→ → Reliable communication example: Direct communication using humans or machines, such as quantum communication (the drawback is that the amount of information to be transmitted is currently small).
And the following things are put into-and-out from its another input-output port isolated-and-prepared for only them.
★ Outside and reliable “instructions, programs, commands or data-or-information, etc.” expressed by 3value-expression which can clearly be distinguished from 2value-expression.
Example Example Examples of some reliable communication means:
Quantum communication means etc. , And direct communication means such as a human carrier or a machine carrier.
But communicable information-quantity of the quantum communication is very small now.
As a result, even if the information processing means can be illegally entered, the "illegal program, illegal command" etc. which has been illegally entered is not executed at all because it is not the execution target, so that the information processing means is illegally operated. Is completely missing. The illicit program, the illicit command, etc. become only harmless and worthless junk "data or information" for the information processing means.
As the result, it's absolutely impossible that the unjust 'program, command, etc. 'operate the information-processing-means, because they are executed at all on account of no object of execution, even if they can invade thereinto.
The unjust 'program, command, etc. 'are' mere, harmless and worthless'rubbish-'data or information' for the information-processing-means.
That is why, from the recent "tricks against measures against unauthorized entry operations" and "a strong request for the ultimate measures / means to end the mischief operation and the measures of the countermeasures", this future application technology is also immediate The inventor thinks that it is not wrong even if it is used.
By such reasons, the present inventor does not think it is that that prior prior-technology is now used when thinking both 'recent big trouble with respect to defense against unjust invade-operating' and 'recent great request for final defenses an end to a vicious circle between the unjust invade-operating and the defense '.
In addition, there is "an information processing means having an unauthorized entry operation preventing function" of JP-A-2011-103124 (spontaneous withdrawal for the same reason as the invention of the prior application described above).
Besides, there is another prior invention 'JP2011-103124 A' of “Information-processing-means with working to prevent unjust-invasion-operation”.
(But he voluntarily withdrew this invention too by the same reason with that of the first prior invention.)
With these methods of preventing intrusion operations, it may be possible to eliminate the war in the cyberspace (land, sea, air, space, and the fifth battlefield) itself, which has become particularly serious recently. Absent.
It may be possible to extinguish every war itself in cyber space, if using this way how to prevent unjust-invasion-operation.
The kind of war crises are recently becoming special-abe grave matter, and the cyber space is called the 5th battlefield next to the 1st to 4th battlefields of land, sea, sky and universe.

In addition, compatibility with this cloud operation prevention technology and the cloud computer is excellent. This is because, for example, even if the "instruction (= instruction), program or command", etc. is expressed in three values as described above, the request content of the client and the processing result content can be expressed in two values.
In addition, “this technology to prevent unjust-invasion-operation” fits a cloud-computer extremely well.
Because it's possible to express both 'every content for its client to request' and 'every result for the computer to have processed' by using the above-mentioned 2value-expression, even if only “the instructions, programs or commands, etc. . "Are expressed by the above-mentioned 3value-expression.
Also, when the difference between the numerical values 1 and 0 is expressed by the difference in frequency, the communication line itself can be used as a frequency filter. It is because it is good if the frequency corresponding to the numerical value 2 is not defined and prepared from the beginning in the communication means.
And because it's possible to use its communication-circuits themselves as frequency filters in a case of expressing the difference between the two numerical values '1 and 0' by the difference between two frequencies.
Or because it's good neither defining nor preparing a frequency corresponding to the numerical value '2' in their communication-means from the beginning.
By the way, "Hideover of in-vehicle computer" described in the specification of "Japanese Patent Application Publication No. 2006-190239" (information processing means having a function to prevent unauthorized entry operation) by the present inventor is subsequently demonstrated by two American universities in 2010 The experiment was confirmed and the paper was presented.
→ → The following non-patent literature 19:
By the way, the present inventor described “capture of computers equipped with an automobile” in the description of his invention 'JP2006-190239 A' of “Information-processing-means with working to prevent unjust-invasion-operation”.
After the disclosure, the capture was confirmed through experiments for confirming the possibility of the capture by two American university, and their paper about the capture was presented in 2010 year.
Follow follow The following document 16.
Therefore, a number of companies, including domestic and overseas automobile manufacturers, have begun to establish international standard specification and international standardization with the aim of securing "real time property and fail safe". Therefore, the inventor thinks that the real-time property of the new concept computer described above and the above-described intrusion operation preventing technique may be useful.
→ → The following non-patent literature 20.
For that reason, 'many companies of interior-&-exterior automobile-makers etc. 'starting attempting to make international standard-or-specification in order to ensure both' faster real-time processing 'and' stronger fail-safe working '.
From such a reason, the present inventor thinks the following two things useful for the ensuring.
(1) Very fast real-time processing of the above noted new concept computer.
(2) The above noted technology to prevent unjust-invasion-operation.
Follow follow The following document 17.
Then, adding that there is no misunderstanding with regard to Japanese Patent Application Laid-Open No. 2006-190239, Japanese Patent Application Laid-Open No. 2006-190239 has a description of "indication of public order and moral violation", but the present inventor and the present applicant We have not received any warning or punishment from the Patent Office. This is because it does not know that it is necessary to clearly indicate that "It is a registered trademark" with respect to Floppy (registered trademark) described in the specification, and it has not been made explicit.
And then, in order to clear misunderstanding with regard to his prior invention 'JP2006-190239A', the present inventor adds the things noted below.
“The indication of having violated public order and morality” is described in its Kokai publication, but the present inventor (= present applicant) has received neither warning nor penalty from Japan Patent Office in relation to the indication.
The indication was caused by that he did not know it was necessary to point out that “Floppy (registered trademark) (registered trademark)” was a registered trademark in spite of using the trademark in its description, and by that he did not point out so.
■ ◆ Nonpatent document (Nonpatent document) 19 ◆ ■
"Experimental Security Analysis of a Modern Automobile", 2010 IEEE Symposium on Security and Privacy.
■ ◆ Nonpatent document (Nonpatent document) 20 ◆ ■
Nikkei Electronics 1088 (August 6, 2012) p. 49 to p. 57 "Ethernet (registered trademark) gets on the car to ensure real-time and fail-safety". Published by Nikkei BP on August 6, 2012.
'Ethernet (registered trademark) (registered trademark) is equipped for automobiles, In order to ensure both "faster real-time processing" and "stronger fail-safe function"'.
NIKKEI ELECTRONICS No. 1088 (the 6th August 2012 year number) at pages 49 to 57, published by Nikkei Business Publications, Inc. (In Japan) on the 6th August in 2012 year.
■ ◆ Nonpatent document (Nonpatent document) 21 ◆ ■
Nihon Keizai Shimbun, morning edition (Tokyo version) (August 8, 2014 issue) p. 38 'Automotive car hijacking? , "Cyber Attack New Threat", "Remote Operation," Demonstrate "at a US conference.

◆ ◆ ◆ ◆ ********** 6th 10-valued logic complete circuit ********** ◆ ◆ ◆ ◆
***
●● 28) shows 10 values of the sixth logic complete circuits (= synthetic-multivalued logic circuit) in FIG. 43. Multivalued logic complete circuit of FIG. 43 is an equivalent circuit of the multi-valued logic complete circuit of FIG. 35. In the multi-level logic complete circuit of FIG. 35 , the multi-level OR equivalent circuit of FIG. 33 is used for each multi-level OR means, and each "multi-level AND circuit + multi-level NOT circuit" It has been replaced.
That is, substituting one equivalent circuit of the multi-level "OR (m) = m" circuit of Figure 33 each-multi-level "OR (m) = m" circuit in FIG. 35, "multi-value after the replacement Replace each series circuit of "AND (m) = m" circuit and multi-value "NOT (m) = m" circuit connected in the latter stage one by one with multi-value "NAND (m) = m" circuit And the above-mentioned multiple value equivalent circuit.
Of course, each integer value of m is set to each integer value shown in FIG. 35 , and each number of input terminals is also set to each number of input terminals shown in FIG.
In this case, when various multi-level synchronous logic circuits are used for the multi-level logic complete circuit of FIG. 43 , it is possible to make each synchronization timing and each signal propagation time uniform. For example, the synchronization timings of the “all-synchronous NOT circuit and the all-synchronous EVEN circuit” in the first stage are made to coincide, and the synchronization timings of the all-synchronous NAND circuit in the second stage are made equal, Match the synchronization timing of the synchronous NAND circuit. However, as a matter of course, the synchronization timings of the respective stages are completely different from each other and usually shifted. Alternatively, the first stage synchronization timing may be made to coincide with the third stage synchronization timing, and the second stage synchronization timing may be shifted from both synchronization timings.
The multi-level logic complete circuit of FIG. 43 is also a "multi-level logic complete circuit before improvement of the multi-level logic complete circuit of FIG. 44 described next." Multivalued logic complete circuit of Figure 44 is a "multi-value EVEN circuits to each portion where the input portion is directly connected to the multi-level NAND circuit and an input terminal Ty in multivalued logic complete circuit of" Figure 43 Pull-up resistor Or pull-down resistance]] is inserted and connected one by one.

◆ ◆ ◆ ◆ ********** 7th 10 value logic complete circuit ********** ◆ ◆ ◆ ◆
***
●● 29) shows 10 values of the seventh logic complete circuits (= synthetic-multivalued logic circuit) in FIG. 44. Multivalued logic complete circuit of FIG. 44 is an equivalent circuit of the multi-valued logic complete circuit of FIG. 40. In the multi-level logic complete circuit of FIG. 40 , the multi-level OR equivalent circuit of FIG. 33 is used for each multi-level OR means, and each "multi-level AND circuit + multi-level NOT circuit" It has been replaced.
That is, substituting one equivalent circuit of the multi-level "OR (m) = m" circuit of Figure 33 each-multi-level "OR (m) = m" circuit in FIG. 40, "multi-value after the replacement Replace each series circuit of "AND (m) = m" circuit and multi-value "NOT (m) = m" circuit connected in the latter stage one by one with multi-value "NAND (m) = m" circuit And the above-mentioned multiple value equivalent circuit.
Of course, each integer value of m is set to the integer value shown in FIG. 40, set to the number of the - input terminal shown in Figure 40 even if the number of the - input terminal.
Also in this case, when various multi-level synchronous logic circuits are used for the multi-level logic complete circuit of FIG. 40 , it is possible to make each synchronization timing and each signal propagation time uniform. For example, the synchronization timings of the “all-synchronous NOT circuit and the all-synchronous EVEN circuit” in the first stage are made to coincide, and the synchronization timings of the all-synchronous NAND circuit in the second stage are made equal, Match the synchronization timing of the synchronous NAND circuit. However, as a matter of course, the synchronization timings of the respective stages are completely different from each other and usually shifted. Alternatively, the first stage synchronization timing may be made to coincide with the third stage synchronization timing, and the second stage synchronization timing may be shifted from both synchronization timings.

◆ ◆ ◆ *** On the expansion, extensibility and universality of Hooji algebra ** ◆ ◆ ◆ ◆
***
◆ ◇ ** ***
About 'applicability, expansibility
and universality 'of “Hooji algebra”
in the field of multivalue-logic
*** ◇ ◆ ◆
***
● ● 30) So far, Houji algebra has been developed in potential mode (or voltage mode) electronic circuits, but in logic and mathematics it is possible to expand and extend Houji algebra more widely.
● ○ 30) We can more widely apply-&-expand “Hooji algebra” logic-mathematically, though the present inventor was applying “Hooji algebra” only in the field of the electronic circuit of electric-potential mode (or voltage mode) until now .
The problem in the expansion / expansion is how to define / represent "the output open or open output in the electronic circuit" in logical mathematics. As one example, the "output open or open output" may be defined and expressed like a "card game, 7 games" like Joker.
'A problem thought when applying so-and-expanding so' is how we should define-and-express 'opened-output (or output-opening) in the field of electronic circuit' in the field of logic-mathematics.
As one example, it's all right to define-and-express the opened-output (or output-opening) like Joker in a Japanese card-game 'Shichinarabe'.
'Shichinarabe' is translated into 'Fantan', 'Sevens' or 'Parliament' in English, and the game-rule of 'Shichinarabe' is similar to that of 'Fantan' according to an English = Japanese dictionary.
The reason for defining and expressing that way is that, as is well known, in "card game, nanababe", Joker is freely transformed into any value of "1 to 13 excluding 7" (or It is because it can be changed. Or, because that joker (Joker) is all mighty. On the other hand, the open output of the electronic circuit can be freely changed (transformed) to "the corresponding logical value" depending on "which power supply potential to pull up / pull down to".
'The reason why the present inventor define-and-express so' is as the following.
In the card game 'Shichinarabe', as well known in Japan, because its game players can freely convert Joker into one of the cards with numerical-value '1 to 13 except 7', or because the Joker is almighty.
And because we can freely convert 'opened-output too in the electronic circuit' into one of the logic-numerical-values used in “Hooji algebra” by pulling up-or-down the opened-output to the power-source-electric -Potential correspondent to the one logic-numerical-value.
So, for example, the meaning of NOT (7) = 7 is "when the input value is 7, the output is Jkr (Joker's abbreviation. 1 example: open circuit for potential mode electronic circuit), and the input value is When it is not 7, the output is expanded to the meaning of "number 7."
So, for the 1st example, the meaning of “NOT (7) = 7” is expanded into the meaning of the following.
Its output is Jkr (= an abbreviation of Joker) when its input-numerical-value is' 7 ', but its output is numerical-value' 7 'when its input-numerical-value is n' t '7'.
A concrete example of Jkr: open-output in the electronic circuit of electric-potential mode.
Also, for example, the meaning of AND (5) = 5 is that "when all of the plurality of input numbers are 5, the output is number 5, otherwise (= even one of the plurality of input numbers When it is not 5, its output is extended to the meaning of Jkr (abbreviation of Joker. 1 specific example: open output in the case of the above electronic circuit).
And, for the 2nd example, the meaning of "AND (5) = 5" is expanded into the meaning of the following.
Its output is numerical-value'5 'when all of its plural input-numerical-values are' 5 ', but its output is Jkr (= Joker) when being not so (= when at least one of its plural input-numerical- values aren't '5').
A concrete example of Jkr: open-output in the electronic circuit of electric-potential mode.
Furthermore, for example, the meaning of OR (3) = 3 is that when at least one of the plurality of input numbers is 3, the output is the number 3, otherwise (= all of the plurality of input numbers are When it is a numerical value other than 3, its output is expanded to the meaning of Jkr (abbreviation of Joker. 1 specific example: open output in the case of the above electronic circuit).
And, for the 3rd example, the meaning of “OR (3) = 3” is expanded into the meaning of the following.
Its output is numerical-value3 'when at least one of its plural input-numerical-values are' 3 ', but its output is Jkr (= Joker) when being not so (= when all of its plural input-numerical- values are 'a value or values' except '3').
A concrete example of Jkr: open-output in the electronic circuit of electric-potential mode.

Specifically, in the optical circuit, as one specific example of expanding the fuse algebra to the optical circuit, when making each logical value correspond to "lights different in frequency from each other" one to one, Joker also " It corresponds to "a light different from any frequency".
Concretely speaking of light-multivalue-logic-circuits on the basis of "Hooji algebra", one of the concrete examples is as follows.
In case when each logic-numerical-value is one by one corresponding to each of the lights whose frequencies are different from each other, Joker too is related to another light whose frequency is different from different from any of their light frequencies.
In this case, apart from whether or not the following optical frequency conversion etc. can be realized, it corresponds to the "pull-up connection work or pull-down connection work of the electronic circuit" etc. "Installation work to provide conversion means to convert to the optical frequency of one logical value" or "Installation work to provide stop / shutdown means to stop or shut off the output of the Joker light" or "for the Joker light Do nothing and just output.
In this case, setting apart when we can realize the following light-frequency-converting etc. or not,
'Pulling-up-or-down etc. in an electronic circuit are correspondent with 'converting the frequency of Joker-light into one of the frequencies of their logic-numerical-value-lights'or' stopping or interrupting the output of the Joker-light 'or' Letting the Joker- light pass through without doing anything to it '.
In a little more detail, the installation work of the optical frequency conversion means corresponds to “connection work for pulling up / pulling down the output potential to the power supply potential corresponding to any of the logical values”. "No output to light and output as it is" corresponds to "connection work to pull up / pull down the output potential to the power supply potential not corresponding to any of its logical values", and its Joker light output the installation work of stopping and interrupting means "output terminals of the multi-value OR circuit in the embodiment of FIG. 35 similarly pull-up resistor to them and (= output terminal Tf) may not connect a pull-down resistor" It corresponds.
A little minutely speaking, the 'converting light-frequency' is correspondent with 'pulling “the output-electric-potential of a logic-circuit” up-or-down to the power-source-electric-potential corresponding to one of the logic -Numerical-values'.
And, the Joker-light pass through without doing anything to it is corresponding with 'pulling the output-electric-potential up-or-down to the power-source-electric-potential corresponding to no one of the logic-numerical −values'.
And the 'stopping or interrupting the output of the Joker-light' is correspondent with 'connecting near pull-up-resister nor pull-down-resister to the common output-terminal' Tf 'of all the multivalue-OR (-logic) −circuits in the working example shown fig. 35 '.

Then, as another specific example of expanding the fuse algebra into an optical circuit, when making each logical value correspond to “the same number of lights having different polarization directions” one by one, Joker also describes “any of its polarization directions "Corresponding to different light".
And another concrete example on the basis of "Hooji algebra" is as follows.
In case when each logic-numerical-value is one by one corresponding to each of lights whose polarization-directions are different from each other, Joker too is corresponding to another light whose polarization-direction is different from different from any of the polarization-directions.
In this case, it corresponds to "pull-up connection work or pull-down connection work of electronic circuit", etc., regardless of whether "detection or discrimination" of the polarization direction or the following · polarization direction conversion can be realized. "Provide a conversion means for converting the polarization direction of the Joker into the polarization direction of any one logical value" or "provide a stop / shutoff means for stopping or blocking the output of the Joker light" “Installation work” or “do nothing to the Joker light and output it as it is”.
In this case, 'Pulling-up-or-down etc. in an electronic circuit are correspondent with 'conversion of the polarization-direction of Joker-light into one of the polarization-directions of their logic-numerical-value-lights'or' stopping or interrupting the output of the Joker-light 'or' Letting the Joker-light pass through without doing anything to it '.
But setting apart when we can realize the following means or not.
(1) A maens for detecting-or-discriminating their polarization-direction.
(2) A maens for converting as mentioned above.
(3) Etc. .
In a little more detail, the installation work of the light polarization direction / conversion means corresponds to “connection work for pulling up / pulling down the output potential to the power supply potential corresponding to any of the logical values”. “Doing nothing to Joker light and outputting as it is” corresponds to “connection work for pulling up / pulling down the output potential to a power supply potential not corresponding to any of the logical values”. installation work output stopping and interruption means "output terminals of the multi-value OR circuit in the embodiment of FIG. 35 similarly pull-up resistor to them and (= output terminal Tf) may not connect a pull-down resistor" Corresponds to
A little minutely speaking, the 'converting polarization-direction' is correspondent with 'pulling “the output-electric-potential of a logic-circuit” up-or-down to the power-source-electric-potential corresponding to one of the logic -Numerical-values'.
And the Joker light pass through without doing anything to it is corresponding with 'pulling the output-electric-potential up-or-down to the power-source-electric-potential correspondent to no one of the logic-numeral- values'.
And the 'stopping or interrupting the output of the Joker light' is correspondent with the 'connecting near pull-up-resister nor pull-down-resister to the common output-terminal' Tf 'of all the multivalue-OR (-logic)- circuits in the working example shown fig. 35 '.
As described above, if each light conversion means described above can be realized, the fuse algebra can be expanded to the optical circuit field in addition to the electronic circuit field, so that the application field of the fuse algebra can be expanded. No, I was able to expand and expand already as a way of thinking.
→ → Expansion, extensibility and universality of Houji algebra.
If you can realize the "Hooji algebra" to, because we can apply the "Hooji algebra" to the field of light circuit. −mentioned each light converting means etc. .
Namely, it has already been implemented as we think think when applying-&-expanding "Hooji algebra" to real light-circuits.
Although it is a snake foot, considering the light multilevel logic circuit, it is not compatible with translating multilevel in English into multi-level. Again, multivalue etc. is better.
Speaking a superfluous thing, the present inventor thinks it better to call widely 'multivalue or multivalued, etc. 'than to call' multilevel 'when thinking about Light-multivalue-logic-circuits, because it's nothing to be called high-level or low-level in each case of the light-frequencies and the light-polarization-angles.
→ → ● 'Applicability, Expandability and universality' of “Hooji algebra”.
→ → Paragraph number [★ 0312-0314].

■ Polarization angle detection / Polarization angle discrimination and output control of polarization angle ■
Currently, it is said that the detection accuracy of the polarization direction, the determination accuracy, and the resolution are 1/1000 degree = 0.001 °. If this is true, 360 ° / 0.001 ° = 360,000 ways can be determined if all 360 ° are used. That is, speaking of only the input part of the optical multilevel circuit, 360,000 multilevel values are possible, and are more than sufficient.
On the other hand, speaking of the output part of the optical multilevel circuit, a predetermined number (eg, one of 3 to 10, 000, 000) of polarizing plates having different polarization directions are prepared, and the respective polarizations are prepared. The light emitting means or the light guiding means for guiding predetermined light to the polarizing plate and the light shutter means may be combined one by one on the plate. In this case, by controlling each light emitting means or each light guiding means, it is possible to output the polarization direction discontinuously, so that the occurrence of the multi-level inherent multi-level hazard described in the second invention of the prior application itself In addition, since the output change becomes fast (?) In addition, the optical multi-valued circuit becomes extremely advantageous over the electronic multi-valued circuit in these respects. Moreover, since there are no problems of overshooting and undershooting, the optical multilevel circuit is extremely advantageous.
However, when it is converted to an optical IC or an optical LSI, for example, “it can withstand practical use between the output part of a preceding circuit in the circuit and the input part of its subsequent circuit, even if it does not say 0.001 °. Whether it is possible to form an optical multilevel circuit with “polarization attachment accuracy” is a problem when putting an optical multilevel computer into practical use. In addition, whether or not an optical multilevel memory can be realized only by an optical circuit is a problem when putting an optical multilevel computer into practical use.

■ About optical frequency conversion ■
□ about light-frequency-converting □
As a simple example, "A light is converted to electric power by photoelectric conversion, and the power is amplified, and then light emitting diode or laser light emitting means is used to output" B light different in frequency from A light " There is a possible optical frequency conversion method.
As a matter of course, it goes without saying that a (numerical) discrimination circuit for discriminating the input light signal is necessary.
For an easy example, there is a realizable light-frequency-converting-method as follows.
◆ Firstly, converting light-A into electric power by photoelectric-converting temporarily.
◆ Secondarily, amplifying the electric power.
◆ Thirdly, making 'a LED or a laser-emitting-means, etc. 'put out' light-B whose frequency is different from the frequency of light-A 'by using the amplified electric power.
Of course, it's needless to say to need a circuit for discriminating light-A.
In the case of this optical frequency conversion, it is necessary to mediate electric energy in the conversion, and it does not go with "a smart complete optical circuit that can be configured only with an optical circuit", but at least Houji algebra light It turns out that it can be expanded and expanded to the field.
In case of this light-frequency-converting, though it needs to be via electric-energy and the converter isn't constructed of only light-circuits, it's at least provided to be able to apply-&-expand “Hooji algebra "To the field of light.
Also in this case, the frequency of the output light can be changed discontinuously by controlling each of the optical frequency conversions, so that the occurrence of the multi-level inherent multi-level hazard itself described in the second application of the prior application is completely In addition to the elimination, the output change becomes faster (?), So that in these respects, the optical multilevel circuit becomes extremely advantageous over the electronic multilevel circuit. Moreover, since there are no problems of overshooting and undershooting, the optical multilevel circuit is extremely advantageous. However, also in this case, whether or not the optical multilevel memory can be realized only by the optical circuit is a problem when putting the optical multilevel computer into practical use.
◇ ■ Nonpatent document (Nonpatent document) ● 22 ■ ◇
Nikkei Electronics No. 1106, published by Nikkei BP on April 15, 2013. Writing: Tetsuo Nozawa.
'NIKKEI ELECTRONICS No. 1106 ', published by Nikkei Business Publications, Inc. (In Japan) on the 15th April in 2013 year. This article is written by Tetsuo Nozawa.
◆ a) “Si and SiC emit light in various colors Achieved with“ dressed photons ”Optical transmission, solar cells, displays and computers will be renewed”, p. 12 to p. 13.
“● Si and SiC emit lights with the many kinds of colors” and so on.
→ → "Discovery / invention of a light active device that controls light with light! ? ".
◆ b) “Optical transmission is between chips and light sources are also CMOS compatible”, p. 43 to p. 51.
→ → "Multi-value modulation, 1024-value QAM! ! ! ".
◇ ■ Nonpatent document (Nonpatent document) ● 23 ■ ◇
Nikkei Electronics No. 1129, issued March 3, 2014 by Nikkei BP (delivery: around February 28, the same year). Writing: Naoki Tanaka.
'NIKKEI ELECTRONICS No. 1129 ', published by Nikkei Business Publications, Inc. (In Japan) on the 3rd March in 2014 year. This article is written by Naoki Tanaka.
“The action of quantum dots, controlling the color of light by particle size”, etc. p. 55.
“● Controlling light-color by the largeness of particles”

Expansion and extension of the fuse algebra to current mode electronic circuits
◆ a) Each logical value is "one to one" with "the same number of different current values (any number from minus value to plus value)".
B) Joker also corresponds to “a current value different from any of the current values”.
C) "Installation work to provide current conversion means for converting the Joker current into a current corresponding to a predetermined logical value" using a current mirror circuit or the like, or "stop or shut off the output of the Joker current" Installation work to provide stop / cut-off means or "do nothing to the Joker current, and output as it is".
In that case, the installation work of the current conversion means in the current mode corresponds to “connection work for pulling up / pulling down the output potential to the power supply potential corresponding to one of the logical values in the potential mode” Do nothing to the Joker current and output as it is corresponds to “connection work to pull up / pull down the output potential to the power supply potential not corresponding to any of the logical values of the potential mode”. , installation work "Figure 35 likewise pull-up resistor to their output terminals of the multi-value OR circuit in example (= output terminal Tf) also pull the potential mode of Joker current output stop and interruption means It corresponds to "not connecting down resistance".
As a matter of course, when multi-level IC and multi-level LSI are realized, since each signal current in the circuit and each reference current for discrimination are kept flowing, reduction of total power loss becomes an extremely big issue. . For example, it becomes necessary to reduce the magnitude of each current as much as possible, and to zero the voltage drop at each point in the circuit as much as possible.

◆ ◆ ◆ *************** Resolving Power Challenges ************* ◆ ◆ ◆
***
● ● 31) In the multi-valued logic circuit in the potential mode (or voltage mode) · Each DC voltage supply is a big problem (see: Non-patent document 8), but DC-DC with high power conversion efficiency as described below There is technology related to converter circuits etc. If more precise constant voltage control is required, an analog type constant voltage means such as a 3-terminal regulator may be connected to the subsequent stage of the "constant voltage controlled DC-DC converter circuit" and the like.

■ ■ Patent Document 23: Patent No. 2,717, 963 ■ ■
◆ a) Constant voltage control by intermittent oscillation control using a Schmitt trigger circuit.
B) Combining self-oscillating DC-DC converter circuit (non-resonant type) with Schmitt trigger circuit is completely different from “hysteresis control before this invention (see: Non-patent document 28 described later)” is there. Since the hysteresis control method prior to the present invention has an oscillation function in itself, the inventor thinks that it would be difficult at the time to combine "two circuits having an oscillation function" on purpose.
C) A device has been devised to prevent “Abnormal oscillation, abnormal overheating, and abnormal power loss increase” caused by the Schmitt trigger circuit.
D) Application date: May 19, 1987 Priority date: June 25, 1986, August 25, the same year.

■ ■ Patent Document 24: Patent No. 3, 187, 470 ■ ■
◆ a) Complex resonance type DC-DC converter circuit (full current zero switching, zero switching loss at on / off switching). Prior to this invention, realization of perfect "zero current switching operation or zero voltage switching operation" for switching noise reduction (such as radio wave noise reduction) and switching loss reduction (向上 improvement of power conversion efficiency) Practical application was an extremely large technical problem to be solved.
→ → Non-Patent Document 24 (Special feature on switching power supply advertisement of Nikkei Sangyo Shimbun [Tokyo version])
B) In general, since the series resonance current damps and oscillates around current zero, the resonance current can not be zero at its minimum value or maximum value. However, the inventor of the present invention examined and discovered "experimental effects of the combination of the series resonant circuit, the parallel resonant circuit and the bidirectional constant voltage means" while experimenting. The unique effect is that the resonant current can be set to be zero at its local minimum or local maximum.
Reference: this patent publication, the current waveform of FIG. (Only the current waveform of the first closed circuit.)
⇒ こ れ This makes it easy to switch to zero current when the main switch is turned off because the time for which the resonance current stays at or near zero is long. On the other hand, when the turn on the resonant current starts to flow from the current zero with the turn on, the current naturally becomes the current zero switching.
At this time, something like a unique filter switching action (or impedance switching action) works, and it is considered that an effect by it appears.
Note that the switching loss at the time of on / off switching of the semiconductor switch used is the integration of time of (voltage across the switch) × (the main current) from “the turn off start to the turn off complete” or “the turn Since it is determined by performing “from on start to turn on completion”, “the voltage across the switch” or “the main current” should be as zero as possible during the turn off operation and the turn on operation. good. It is not good only if the resonant current is temporarily (at the moment) zero during "the turn-off operation" and "the turn-on operation".

C) For example, when using “two power diodes connected in anti-parallel” as the bi-directional constant voltage means, the bi-directional constant voltage means and the parallel resonant circuit are connected in parallel, Since the forward voltage of each diode and the parallel resonant capacitor voltage are the same, the parallel resonant capacitor voltage directly controls each forward current based on the respective forward voltage-forward current characteristics. Become. On the other hand, the bi-directional constant voltage means also clamps, suppressing the magnitude of the amplitude of the parallel resonant capacitor voltage by its constant voltage action.
Here, simply thinking, if the series resonant frequency and the parallel resonant frequency are the same, the parallel resonant circuit is impedance に 対 し て (during ideal operation) with respect to the series resonant voltage, so if it is alone it is usually the series resonance It should pass no current at all. Conversely, "two power diodes in anti-parallel connection" alone should normally pass any amount of current in both directions based on its constant voltage characteristics.
However, in order for the parallel resonant capacitor voltage to control each forward current, the impedance of “the parallel circuit of the parallel resonant circuit and the bidirectional constant voltage means” is “for each of the series resonant voltages”. "Switching from zero to 、" or "from ∞ to zero" bordering on each current value (= 1 current value and reverse current value) determined based on forward voltage-forward current characteristics It is believed that the "filter switching action (or similar impedance switching action)" acts on the series resonant voltage.
The respective current values change with the voltage of the parallel resonant capacitor, and the series resonant current can pass through the parallel circuit at both positive and negative current values (between). It is "● a new action / new effect like an alloy." It seems that a new type of circuit configuration means has been created by combining two circuit configuration means having mutually opposite properties with respect to the series resonance current.
If this (a combined circuit of series resonant circuit, parallel resonant circuit and bidirectional constant voltage means) is given a name, then “alloy circuit”! ?
→ → ● Variable type constant current method? ? ?
The inventor thinks that “the series resonance current does not oscillate due to the current zero due to the new action and the new effect”.
When the power supply line of this complex resonance type DC-DC converter circuit is released from the DC power supply, the magnitude of the DC resonance current described above naturally decreases with the decrease of the power supply capacitor voltage of the circuit. The inventors visually observed that the second extremum in the current waveform kept holding zero. Since this means that the new action and new effect of the "alloy circuit" is not influenced by the change in the magnitude of the power supply voltage, the alloy circuit may be able to be utilized in an AC power supply.

◆ d) The above explanation is for the case where the series resonance frequency and the parallel resonance frequency are the same, but actually, when one resonance frequency is fixed, the other resonance frequency is changed, The minimum value (second extreme value) of the series resonance current goes from a positive value to zero and further changes to a negative value. Or, it changes in the opposite direction. On the other hand, if the plus and minus of the series resonance current are exactly opposite, the maximum value (the second extreme value) of the series resonance current goes from a minus value to zero, and further changes to a plus value. Or, it changes in the opposite direction.
As a result, by adjusting both resonance frequencies, it is possible to set so that the minimum value or the maximum value (second maximum value) of the series resonance current becomes zero. Note that for the second extreme, if that of the first closed circuit is a local minimum, that of the second closed circuit is a local maximum. Alternatively, the former is the maximum value, and the latter is the minimum value.
Maybe because of such zero current switching! ? The on / off switching is performed gently and smoothly without the occurrence of a current surge at the on / off switching of the main switch. Also, unlike the other current zero switching methods, the time during which the resonance current remains at or near zero at the turn-off is longer, so the turn-off from the start of the main switch to the end of the turn-off is It can be done with some margin. This has a positive effect on the next turn-on operation.
Moreover, since the switching loss is expressed by the time integral of the product of the main current of the main switch and the voltage across the main switch, the time during which the resonance current remains at or near zero at the on / off switching time Is advantageous over other current zero switching schemes in terms of switching loss during on / off switching. However, as described above, it is necessary to always maintain the relationship between the two resonance frequencies.
Reference: Patent No. 3,187,470 · Current waveform in FIG. (Only the current waveform of the first closed circuit.)

E) Although the circuit constants and parts used described in this patent publication "are not the best choice because they use random parts", a third party can easily verify the circuit operation.
F) In the case of an ordinary resonant DC-DC converter circuit The switching is usually approximately half a resonant cycle (for example, each period of a sine wave “0 to π” and “π to 2π” periods) However, in the case of this invention technology, the switching half period is approximately 3⁄4 resonance period (for example, each period of “0 to 3π / 2” and “3π / 2 to 3π” of sine wave), The switching frequency may be low, for example, "the capacitance between the drain, source and gate of the power MOS-FET used" and the switching loss associated with charging and discharging of each may be reduced, so that the switching loss It is also advantageous in terms of reduction.
G) In the meantime, considering the general diode on / off operation, the manufacturer's specification of the above-mentioned power diode used (Non-Patent Document 25 described later) “its turn on delay” and “its turn · Regarding “off delay”, its measurement method, measurement condition and its measurement value (forward recovery time and reverse recovery time) are described. However, in the case of this complex resonant type DC-DC converter circuit, the two antiparallel-connected diodes operate in an analog manner, so the on / off operation is not applicable to this circuit.
Even if this circuit is considered as on / off operation, its use conditions are rather loose (loose). For example, comparing the "V _{max 1} volt AC voltage of the AC voltage and V _{max 100} volt" 1 kilohertz, (the slope of = AC voltage waveform) and the voltage change rate when the Instantaneous value is zero The former is much smaller. Moreover, with regard to the parallel resonant capacitor voltage, the slope is zero near the plus peak value and the minus peak value in the case of .pi. / 2, 3 .pi. Because the voltage change is very small, it takes time for the voltage to change, and it is sufficient for the power diodes to turn on and off. It is thought that time will be given.
H) The following Non-Patent Documents 26 and 27 also support the certainty and usefulness of the present invention technique.
◆ i) Application date: June 1, 1991, priority date: June 1, 1990.
J) The positive side waveform (current waveform of the first closed circuit) and the negative side waveform (current waveform of the second closed circuit) of the resonance current need to be symmetrical. Otherwise, the transformer used may become biased, or it may not be possible to simultaneously set both the “second extreme on the positive side” and the “second extreme on the negative side” to zero current. Do. That is, only one side can set current zero.
◆ k) After that, if the power semiconductor of SiC or GaN with small on resistance and on voltage is used for the main switch, the power conversion efficiency will be further enhanced.

■ ■ Patent Document 25: Patent No. 3,187, 411 ■ ■
(Resonant DC-DC converter circuit) [Self-oscillating type which improves the technology of Patent Document 26 below, saving of driving power and reduction of the number of parts by sharing driving transformer and output transformer].
■ ■ Patent Document 26: Patent No. 3,333,504 ■ ■
(Same as above) [Self-oscillating type, bi-directional constant voltage means (example: anti-parallel connection diode) and simple drive means using a drive transformer, bridge connection type, etc. to make the resonance voltage constant].
■ ■ Patent Document 27: Patent No. 3,477,136 ■ ■
◆ a) Constant voltage control by intermittent oscillation control using a Schmitt trigger circuit.
B) A combination of a resonant self-oscillation type DC-DC converter circuit and a Schmitt trigger circuit is a completely different point from "hysteresis control (refer to the following: non-patent document 28 below) prior to the present invention". Since the hysteresis control method prior to the present invention has an oscillation function in itself, the inventor thinks that it would be difficult at the time to combine "two circuits having an oscillation function" on purpose.
C) For this reason, since the resonance period and the intermittent period are independent of each other, the switching frequency becomes a constant switching frequency by the resonance operation.
D) The utility brought about by the zero current switching eliminates the need for the ingenuity and configuration means required in the invention of Patent Document 23 above, and the circuit configuration and the input / output voltage relationship are highly flexible.
◆ e) Divisional application of original application of Patent Document 24.
F) Before this invention technology, “constant voltage control and no-load standby power reduction” of the resonant DC-DC converter circuit was an extremely large technical problem to be solved. I was able to solve it at the same time.
→ → Non-Patent Document 24 (Special feature on switching power supply advertisement of Nikkei Sangyo Shimbun [Tokyo version])

■ ■ Patent Document 28: Patent No. 3,494, 303 ■ ■
(Resonant DC-DC converter circuit) [less winding number].
■ ■ Patent Document 29: Patent No. 3,521,055 ■ ■
(Same as above) [Reduction of control measures].
■ ■ Patent Document 30: Patent No. 3,645, 274 ■ ■
(Same as above) [Assist to start oscillation in a resonant DC-DC converter circuit of Patent Document 25 technology].
■ ■ Patent Document 31: Patent No. 3,730,354 ■ ■
(Non-controllable switching means = transistor type diode means) [reduction in magnitude of forward voltage, reduction in power loss].
Patent Document 32: JP-A-9-51677
(Compound resonance type DC-DC converter circuit) [less number of turns] {date of highest priority: October 17, 1994, deemed withdrawal} [disclosed a number of examples]. This main circuit is a simplification of the main circuit of Patent Document 24 technology, but one example of this main circuit and the main circuit of the following Non-Patent Document 26 technology are identical.
Importantly, it is necessary for the positive side and the negative side of the resonant current waveform to be symmetrical in order to prevent biased magnetization of the transformer or the like. Moreover, if the current waveforms on both sides are symmetrical, the second extreme value on either side is zero. In the case of asymmetry, only the second extremum of that one becomes zero.
■ ■ Patent Document 33: Patent No. 4,450, 295 ■ ■
(Resonant AC-DC converter, excitation type). Perfect power factor improvement requires even more plus alpha technology.
■ ■ Patent Document 34: Patent No. 4,694, 690 ■ ■
(Resonant type AC-DC converter device, diode clamp type). Perfect power factor improvement requires even more plus alpha technology.

■ ◆ Non-Patent Document 24: Nikkei Sangyo Shimbun (Tokyo version) dated January 12, 1990 ◆ ■
"Special feature on switching power supply advertising,""Switching power supply also used in communication equipment and artificial satellites," Switching Regulator, "written by: Kazuki (Katsuki?) Akihiko (Kyushu University Faculty of Engineering)
■ ◆ Non-Patent Document 25: <Semiconductor manual for electric power>, TOSHIBA Rectifier element · Thyristor medium and small edition 1989 ◆ ■
Explanation of "Forward Recovery Time and Reverse Recovery Time" (p.56-p.57), Specific examples of power diode recovery characteristics (p.383-p.384) .
Non-Patent Document 26: PESC '96 Record, 1913 (1996)
J. G. Hayes, et al. “Full-Bridge, Series-Resonant Converter Supplying the SAE J-1773 Electric Vehicle Inductive Charging Interface”. [Fast charger of storage battery for electric vehicle which is considered to apply the technology of the complex resonant type DC-DC converter circuit of Patent Document 26 and the like described above]. → → ● Prototype of non-contact type resonant charging circuit.
■ ◆ Non-Patent Document 27: "The Institute of Electrical Engineers of Japan Technical Report No. 687: High-performance switching technology for power converters" ◆ ■
p. 46 [DC-DC converter using current multiple resonance] in FIG. Author: High Performance Switching Technology Research Committee for Power Converters, published by the Institute of Electrical Engineers on August 25, 1998. [Introduction of the circuit technology of Non-Patent Document 26].
■ ◆ Non-Patent Document 28: Nikkei Electronics June 15 (2009), 1006 ◆ ◆
p. 78 to p. 86, “Analog Reinforcement 塾 The 6th High-Speed Feature Hysteresis Control Leads in Power Control Method”, Author: Katsushi Yamashita, Nikkei BP, published June 15, 2009.

◆ ◆ ◆ ***** True 3D IC (3D LSI) considered by the present inventor! **** ◆ ◆ ◆ ◆
***
●● 33) An LSI is also included in the IC, but “The one in which a plurality of two-dimensional IC chips are stacked and the chips are connected to each other by through electrodes is a three-dimensional“ ization ”IC,“ true three-dimensional The inventor believes that it is not "IC".
The difference between "3D IC" and "3D IC" lies in the flow of signals in the vertical direction of both. The difference is like the difference between a "flying helicopter" and a "car moving around in a multistory parking lot".
The former can move freely around the three-dimensional space in front and back, left and right, up and down, and so on. On the other hand, the latter can move freely around each parking floor of each floor (each) front and back, left and right, and its two-dimensional plane, but "up slope, down slope" or "car elevator" is installed up and down You can only move where you were. In addition, the upper and lower movement directions are also restricted, and it is impossible to move in the upper right direction, the upper left direction, or the upper rear direction. so! Indeed, the "up slope, down slope" and "car elevator" correspond to the through electrode.
Therefore, an IC in which a plurality of two-dimensional IC chips are stacked and respective circuits on the upper and lower sides are connected by through electrodes is a three-dimensional "conversion" IC, not a "true three-dimensional IC".
The "true three-dimensional IC" means that circuits can be expanded freely in "front and back, left and right two-dimensional xy directions", "upper and lower, front and back two-dimensional yz directions" and "upper and lower, left and right two-dimensional xz directions" Of course, it is ultimately an IC that can expand the circuit freely in the three-dimensional xyz directions.
A specific example will be described. For example, in the case of the multi-level memory in the selection diagram (FIG. 2) of Japanese Patent Laid-Open No. 2005-116168, "independent completed binary memories located on each floor (between each two power supply lines)" Is connected to the upper and lower sides simply by through electrodes, resulting in multi-valued memory.
On the other hand, for example, in the case of the multilevel memory shown in the selection diagram (FIG. 10) of Japanese Patent Application Laid-Open No. 2006-252742, each floor (between each two power supply lines) has no "independently fully operating binary memory". Since it becomes only one multi-level memory for the first time on the entire floor, it can not be said that it is sufficient to simply connect the upper and lower circuits with the through electrodes. A "true three-dimensional IC technology" is required for a multi-level memory circuit in which a large number of multi-level memories are efficiently integrated as memory cells. In addition, each of the embodiments shown in FIGS. 9 to 19 of JP-A-2007-35233 is one requiring the "true three-dimensional IC technology".
If you apply a 3D printer or the like to IC / LSI manufacture, you may be able to manufacture “True 3D IC · LSI”. No, the inventor is so strongly convinced that it will always be.
At that time, it is also extremely strongly convinced that the method of manufacturing semiconductors and electronic circuits by the following techniques such as printing and painting becomes essential.
■ ◆ Non-patent literature 30 ◆ ◆ Nikkei Sangyo Shimbun (Tokyo version) (issued March 24, 2009).
(A) Dainippon Printing, "Low cost for electronic circuit printing,""Fine-grained copper for ink,""One tenth of the price of silver," ⇒ 開 発 技術 Development of technology for forming printed circuit board wiring patterns
(B) Teijin, "Silicon particles in resin,""Successful creation of n-type and p-type nanoparticles of semiconductors!"". ⇒ 着手 Started creating electronic circuits consisting of transistors and diodes.
■ ◆ Non-patent literature 31 ◆ ■ The Nihon Keizai Shimbun (Tokyo version) (issued February 18, 2014).
(A) RIKEN and others, “Organic semiconductors with spray”, “Power generation and luminescence for the whole car”.
■ ◆ Non-Patent Document 32 ◆ ■ Nikkei Electronics No. 1146.
“Progress in fine printing technology, application to organic integrated circuits” (p. 61 to p. 73). Research & Development & Lecture: Toshinori Shikichi. Published by Nikkei BP October 27, 2014.
● 1) Development of p-type and n-type coating type low molecules.
● 2) It is possible to form electrodes and wiring by printing.
● 3) Variation is small V _TH is almost zero.
● 4) Make an integrated circuit and check the operation.
■ ◆ Non-Patent Document 33 ◆ ◆ Nikkei Electronics No. 1155.
“Affordable with paper and conductive ink Agricultural sensors: Sensprout” (p. 59). Writing: Nezu Akira. Published by Nikkei BP April 20, 2015.
● 1) Easy digital signage with conductive ink.

◆ ◆ ◆ ◆ ***** On the cooling method of 3D IC · LSI ******** ◆ ◆ ◆
***
●● 34) Finally, in the same way as automotive engine cooling systems and water jackets, liquid (eg water, etc.) or gas that will be the refrigerant will flow directly into the three-dimensional IC, three-dimensional LSI. The present inventor thinks that it will cool efficiently. At that time, conventional through electrode technology and technology such as 3D printer are useful. The refrigerant is allowed to flow in a cavity in each of the through electrodes (= conductive through pipes) or each through electrodes (= nonconductive and high thermal conductivity through pipes). Alternatively, the "air-insulated hole-like cavity" is provided in a three-dimensional IC or three-dimensional LSI, and the refrigerant is allowed to flow directly into the free cavity.
In addition, one or more pipe-like hollows are run in the "power supply line or power supply plate" of each power supply potential and the shield plate, and the refrigerant is similarly flowed.
Incidentally, at present, the liquid immersion cooling method described in the following non-patent document 34 can not directly cool the central portion of the three-dimensional IC / LSI or three-dimensional IC / LSI.
■ ◆ Non-Patent Document 34 ◆ ◆ Nikkei Electronics No. 1157.
“Redesigning semiconductors, cooling and connections for high-performance Exa class machines (top)” (p.99 to p.105). Research & Development & Writing: Saito Motoaki. Published by Nikkei BP June 20, 2015.
● 1) High-density mounting based on immersion cooling, 4 times the volume performance density with a dedicated design.

◆ ◆ ◆ ◆ ********** Eighth 10-value logic complete circuit ********** ◆ ◆ ◆ ◆
***
●● 35) shows 10 values of the eighth logic complete circuits (= synthetic-multivalued logic circuit) in FIG. 45. Multivalued logic complete circuit of Figure 45 is obtained by changing equivalently the configuration of a multilevel logic complete circuit of FIG. 41.
First, the multi-valued logic complete circuit of FIG. 41, taking into account the respective multilevel AND circuits one at that particular integer value in the "equivalent circuit of the multi-level AND circuit of Figure 34" (= specific value) replace.
Then, secondly, each combination of "multi-level OR circuit and multi-level NOT circuit in the subsequent stage" after the replacement is replaced one by one with a multi-level NOR circuit.
Furthermore, thirdly, each of the multi-value NOT 2-stage connection circuits on the input side of each of the multi-value NOR circuits after the replacement is "one equivalent circuit of FIG. It is applied to the multi-level EVEN circuit in one stage while considering the above.
Then, fourthly, "one equivalent circuit of FIG. 11 of Patent Document 18 below" is considered in each of the multi-value EVEN and NOT 2-stage connection circuits on the input side of each of the multi-value NOR circuits. While applying the multi-value NOT circuit is transformed into a single step.
As a result, it is understood that it is possible to derive a multivalued logic complete circuit of FIG. 45 from the multi-level logic complete circuit of FIG. 41.
Comparing the multi-level logic complete circuit of FIG. 41 with the multi-level logic complete circuit of FIG. 45 , the former is composed of a complete system centered on the multi-level AND circuit, while the latter is centered on the multi-level NOR circuit. It consists of a complete system. For this reason, whichever multi-level logic complete circuit is adopted, eventually, the types of usable basic and multi-level logic circuits increase, which is convenient.
Japanese Patent Application Laid-Open No. 2014-179977 (Multiple-valued NOT two-step connection means etc. based on the principle of Fuge algebra)

The configuration of the multivalued logic complete circuit of FIG. 45 will be described. The multivalued logic complete circuit of FIG. 45 satisfies a 10-value truth table (FIG. 36 ) representing the multivalued logic function f (x, y). When "multi-value EVEN circuit or multi-value NOT circuit" determines the input logic variable y, the multi-value NOT circuit is used if the y value and the f value in the truth table are the same, otherwise the multi-value EVEN circuit Is used. The specific value common to the input and output of each circuit is the y value to be determined. These things are the same also in x value discrimination.
Each multi-value NOR circuit expresses each correlation of the x value, y value and f value one by one "by connecting the three signals in its own circuit", and specifies a specific value common to its own input / output The f value is output to the output terminal Tf. Pre-stage output signal / Pull-stage input signal matching Pull-up / down resistance pulls up the pre-stage output potential to “power supply potential corresponding to values other than the same value” when the y value and f value are the same "Up or down", otherwise "pull up or down" to "power supply potential corresponding to the f value". The same applies to the side of the x value and the f value.

The multivalued logic complete circuit with an improved multi-valued logic complete circuit of FIG. 45 is shown in FIG. 46. In the multilevel logic complete circuit of FIG. 46 , unnecessary potential oscillations (or voltage oscillations), such as overshooting and undershooting, generated at each input portion of each multilevel NOR circuit are suppressed.
In the multi-level logic complete circuit shown in FIG. 45 , each “multi-level EVEN circuit or multi-level NOT circuit” is connected with a pull resistance that pulls up / down the output potential of the circuit when the output is open. However, in the multi-level logic complete circuit of FIG. 46 , in order to suppress the unnecessary vibration, each input potential of each multi-level NOR circuit is set to Among the predetermined constant potentials, one lower clamper is connected to clamp each constant potential, with the lower one being the low potential side and the higher one being the high potential side.
By this, the multi-level logic complete circuit of FIG. 46 can suppress each input potential oscillation (or input voltage oscillation) of each multi-level AND circuit. This suppression function is also useful for preventing the occurrence of multi-level hazards and the transmission delay of the transmission signal.

Also in these cases, when various multi-level synchronous logic circuits are used for each multi-level logic complete circuit of FIGS. 45 and 46 , it is possible to make each synchronization timing and each signal propagation time uniform. For example, the synchronization timings of the "all-synchronous NOT circuit and the all-synchronous EVEN circuit" in the first stage are made to coincide, and the synchronization timings of all the synchronous NOR circuits in the second stage are made to coincide. However, as a matter of course, the synchronization timings of the respective stages are completely different from each other and usually shifted.
As described above, the eighth 10-value logic complete circuit has been described to construct a multi-value logic complete circuit by using a plurality of basic / multi-value logic circuits based on the principle of Houji algebra. Can. These multi-valued logic complete circuits are unwavering evidence that proves that "Fuji's algebra has the feature of" perfect "". For this reason, the inventor feels a great potential in the Fuge algebra.
See Figure 35, each-multi-valued logic complete circuit of FIGS. 37 to 38, FIGS. 40 to 46.

With respect to the first to third inventions, although there is still a point to be improved based on these, there is the possibility of industrial use from the aspect of saving power consumption.

Claims (3)

Continuous three integers m-1, m, Table eagle with m + _{1, v m-1} three constant potential corresponding Part 3 consecutive integers and one-to-one in turn, v _m, with _{v m + 1} represents, _{V m-1} three constant potential supply means supplies the three constant potential in sequence, V _m, when Table Wa at _{V m + 1,}
The high side transistor in the bidirectional type when forming the first binary NOT circuit connected in series to two control electrodes insulated transistor to switch operation between the two constant potential supply means V _{m + 1 ·} V _m And
Bidirectional The low side transistor when forming a second binary NOT circuit connected in series between the control electrode insulated transistor 2 both constant potential supply means V _m · V _m-1 to switch operation Type and
Connecting the input terminals of the two binary NOT circuits together to form an entrance means,
The absolute value of the threshold voltage is smaller than the potential difference between both constant potentials v _{m + 1} · v _{m -1} between both output terminals of the two binary NOT circuits, and the potential difference between both constant potentials v _{m + 1} · v _m A normally-off, control-electrode-insulated fifth transistor, which is larger than the potential difference between the two fixed potentials v _m · v _m -1, a portion between the control terminal and the main terminal forming a pair for driving signal input " Are connected such that “when the high potential side transistor and the low potential side transistor are on, the fifth transistor is turned on”.
A multivalue numerical value discrimination circuit characterized in that the remaining main terminals of the fifth transistor are used as an outlet means. When the multivalue numerical value discrimination circuit according to claim 1 is provided between the two constant potential supply means _{Vm + 1} · _Vm-1 by a predetermined number, all the exit means have “ pull down function ” , or Either with a pull-up feature or
When connecting all its outlet means and providing a new common outlet means, one diode is aligned between the respective outlet means before its connection and its common outlet means in the direction of its pull function and connected one by one A multi-value OR logic discriminator circuit based on the principle of Fuge algebra characterized by that. In the multi-value numerical value discrimination circuit according to claim 1,
When the predetermined number is represented by k,
“A series circuit of k bidirectional control electrode insulated transistors for switching operation and a parallel circuit of k control electrode insulated transistors for switching operation” are disposed between both constant potential supply means V _{m + 1} · V _m Of the positive logic binary NOR circuit connected in series with the high potential side and the first binary NOT circuit,
Between the two constant potential supply means V _m · V _m-1 ““ a parallel circuit of k bidirectional control electrode insulated transistors to operate switch ”and“ a series circuit of k control electrode isolated transistors to operate switch ” Replace the second binary NOT circuit with the positive logic binary NAND circuit connected in series with the former on the high potential side,
Each of the k input terminals of the binary NOR circuit and the k input terminals of the binary NAND circuit are connected one by one to form k entrance means. Multilevel AND logic discriminator based on.