JPH01223696A - Multivalued storage circuit - Google Patents
Multivalued storage circuitInfo
- Publication number
- JPH01223696A JPH01223696A JP63048326A JP4832688A JPH01223696A JP H01223696 A JPH01223696 A JP H01223696A JP 63048326 A JP63048326 A JP 63048326A JP 4832688 A JP4832688 A JP 4832688A JP H01223696 A JPH01223696 A JP H01223696A
- Authority
- JP
- Japan
- Prior art keywords
- input
- transistor
- circuit
- inverter
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004044 response Effects 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000003786 synthesis reaction Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
- Dram (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は多値論理回路に関し、特に多値データを記憶し
うる多値記憶回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-value logic circuit, and more particularly to a multi-value storage circuit capable of storing multi-value data.
[従来の技術]
従来、この種の記憶回路に使用される多値入力と同じ論
理値を出力する論理回路としてそれぞれしきい値電圧の
異なるPMO3)ランジスタと8MO3)ランジスタを
用いたレベル判定回路と論理値に対応する電圧をCMO
Sアナログスイッチで切りかえる論理レベル合成回路を
組み合わせる方式がある(例えば電子情報通信学会論文
誌v。[Prior Art] Conventionally, level determination circuits using PMO3) transistors and 8MO3) transistors, each having a different threshold voltage, have been used as logic circuits that output the same logical value as the multi-value input used in this type of memory circuit. CMO the voltage corresponding to the logical value
There is a method that combines logic level synthesis circuits that can be switched using S analog switches (for example, IEICE Transactions v.
L、J70−D P、42r微小電力CMOS4値記
憶回路の構成」)。L, J70-D P, 42r Micro-power CMOS 4-value storage circuit configuration").
[発明が解決しようとする問題点]
上述した従来の多値記憶回路はレベル判定回路にしきい
値の異なるトランジスタを用いる必要があるため、しき
い値を制御するためのイオン注入工程を論理回路の論理
値の数に応じて設ける必要があり工程が複雑であった。[Problems to be Solved by the Invention] Since the above-mentioned conventional multi-value storage circuit requires the use of transistors with different threshold values in the level determination circuit, the ion implantation process for controlling the threshold value has to be performed in the logic circuit. The process was complicated because it needed to be provided according to the number of logical values.
また、論理レベル合成回路にCMOSアナログスイッチ
を用いるため単チャンネルのパストランジスタを使用す
る場合に比べ2倍以上の素子数を要した。また従来の回
路でCMOSアナログスイッチを単チャンネルのパスト
ランジスタに置きかえた場合には、バックゲート効果の
ため合成した電位がトランジスタのしきい値電圧外降下
し、十分なノイズ余裕度が得られない欠点があった。Furthermore, since a CMOS analog switch is used in the logic level synthesis circuit, the number of elements required is more than twice that of the case where a single channel pass transistor is used. In addition, when a CMOS analog switch is replaced with a single-channel pass transistor in a conventional circuit, the back gate effect causes the combined potential to fall outside the threshold voltage of the transistor, making it impossible to obtain sufficient noise margin. was there.
[発明の従来技術に対する相違点]
本発明は論理レベル判定回路に用いるトランジスタのし
きい値を特別な値に制御する必要がなく、論理レベル合
成回路を単チャンネルのパストランジスタで構成できる
。表1に従来例と本発明との相異を示す。[Differences between the invention and the prior art] According to the present invention, there is no need to control the threshold value of the transistor used in the logic level determination circuit to a special value, and the logic level synthesis circuit can be configured with a single-channel pass transistor. Table 1 shows the differences between the conventional example and the present invention.
表ユ
[問題点を解決するための手段]
本発明の多値記憶回路は、論理値の数と同数のそれぞれ
電位の異なる電源とそれぞれ次に高い電位を持つ電源間
に形成された同じしきい値電圧の入力インバータからな
るレベル判定回路と、それぞれの電源と単一の出力の間
に直列に接続された入力インバータと同数の単チャンネ
ルのパストランジスタによる論理レベル合成回路から構
成される。[Means for solving the problem] The multi-level memory circuit of the present invention has the same threshold value formed between the same number of logic values as power supplies with different potentials and the power supplies with the next highest potential. It consists of a level judgment circuit consisting of a value voltage input inverter, and a logic level synthesis circuit consisting of the same number of single-channel pass transistors as the input inverters connected in series between each power supply and a single output.
[実施例] 次に本発明について図面を参照して説明する。[Example] Next, the present invention will be explained with reference to the drawings.
第1図は本発明の第1実施例の回路図であり、3値記憶
回路の構成を示す。3値の真理値(0゜1.2)に対応
する電圧として(OV、 5V、 10V) を選
びOV、5V、l0V(7)3種の電源を用いた。入力
インバータ1,2はそれぞれ5■と10Vの電源間、0
■と5vの電源間に設けられる。インバータlの出力は
IOV電源に接続されたPチャンネルトランジスタ3.
5V電源に接続されたNチャンネルトランジスタ4.0
■電源に接続されたNチャンネルトランジスタ5のゲー
トに接続され、インバータ2の出力は同様にPチャンネ
ルトランジスタ6.7、Nチャンネルトランジスタ8に
接続される。また、ここで用いるトランジスタのバック
ゲート電位はそれぞれ接続されている電源の電位とする
。例えばトランジスタ3と6のバックゲート電位はIO
Vである。FIG. 1 is a circuit diagram of a first embodiment of the present invention, showing the configuration of a ternary storage circuit. (OV, 5V, 10V) were selected as the voltages corresponding to the three-value truth value (0°1.2), and three types of power supplies were used: OV, 5V, and 10V (7). Input inverters 1 and 2 are connected between 5■ and 10V power supplies, respectively.
(1) and 5V power supply. The output of inverter l is connected to the P-channel transistor 3. connected to the IOV power supply.
N-channel transistor 4.0 connected to 5V power supply
(2) It is connected to the gate of the N-channel transistor 5 connected to the power supply, and the output of the inverter 2 is similarly connected to the P-channel transistor 6.7 and the N-channel transistor 8. Furthermore, the back gate potential of the transistors used here is set to the potential of the power supply to which they are connected. For example, the back gate potential of transistors 3 and 6 is IO
It is V.
以上の構成て、3値の論理入力は入力インバータ1と2
により論理レベルが判別されトランジスタ3から8のパ
ストランジスタ群により論理レベルが合成される。すな
わち、入力論理値と同じ論理値を出力する多値論理回路
が実現できる。この回路は第2図の入出力特性に示され
るように3値の論理レベルが電圧降下することなく出力
される特徴を持つ、したがってこの論理回路の入力と出
力を接続することで容易に多値記憶要素が得られる。実
施例では出力と入力のフィードバックループにCM O
Sアナログスイッチ9を設け、記憶要素への書き込みが
より確実に行われる工夫をほどこした。また、“このア
ナログスイッチは回路の最高電位と最低電位に対応する
論理レベル、この例ではIOVとOvて駆動することが
、出力のフィードバックにおいて電圧降下を避けるため
に重要である。With the above configuration, the three-value logic input is input to inverters 1 and 2.
The logic level is determined by , and the logic level is synthesized by the pass transistor group of transistors 3 to 8. In other words, a multivalued logic circuit that outputs the same logic value as the input logic value can be realized. As shown in the input/output characteristics in Figure 2, this circuit has the feature that three logic levels can be output without voltage drop. Therefore, by connecting the input and output of this logic circuit, it is possible to easily A memory element is obtained. In the example, CMO is used in the output and input feedback loop.
An S analog switch 9 is provided to ensure that writing to the memory element is performed more reliably. "It is important to drive this analog switch at logic levels corresponding to the highest and lowest potentials of the circuit, in this example IOV and Ov, in order to avoid voltage drops in output feedback.
第3図は本発明の第2実施例の回路図であり、4値記憶
回路への応用である。真理値(0,L2.3)に対して
電圧(OV、 5V、 IOV、 15V)を割
り当て、第1実施例と同様なレベル判定回路、論理レベ
ル合成回路を構成できる。二のレベル判定回路と論理レ
ベル合成回路からなる論理回路の動作シミュレーション
結果を第4図に示す。FIG. 3 is a circuit diagram of a second embodiment of the present invention, which is applied to a four-value storage circuit. By assigning voltages (OV, 5V, IOV, 15V) to truth values (0, L2.3), it is possible to configure a level determination circuit and a logic level synthesis circuit similar to the first embodiment. FIG. 4 shows the results of an operation simulation of a logic circuit consisting of a second level determination circuit and a logic level synthesis circuit.
[発明の効果コ
以上説明したように本発明は多電源間に分布させた入力
インバータにより、各トランジスタのしきい値電圧に特
別な制御を加えなくとも簡単に多値論理のレベル判定回
路を実現できる。また、このインバータの出力電圧で論
理レベル合成回路に用いるパストランジスタを十分駆動
できるので電源電位が電圧降下することなく伝達される
利点を持つ。したがって本発明による多値記憶回路を用
いれば、高集積記憶素子の実現が可能になる。なお実施
例では3値記憶回路及び4値記憶回路への応用を示した
が、6値以上の多値を扱う場合でも全く同じ方法で拡張
できる。また最近の3次元素子のように絶縁膜を介して
多層に素子を形成する手段を用い、各階層に本発明にお
ける多値に対応する電源を割り当て、本発明による多値
記憶回路を構成すればさらに記憶密度の向上がはかれる
。[Effects of the Invention] As explained above, the present invention uses input inverters distributed between multiple power supplies to easily realize a multi-valued logic level judgment circuit without any special control on the threshold voltage of each transistor. can. Further, since the output voltage of this inverter can sufficiently drive the pass transistor used in the logic level synthesis circuit, there is an advantage that the power supply potential can be transmitted without voltage drop. Therefore, by using the multilevel memory circuit according to the present invention, it becomes possible to realize a highly integrated memory element. In the embodiment, application to a 3-value storage circuit and a 4-value storage circuit is shown, but the invention can be expanded in exactly the same way even when handling multi-values of 6 or more values. Furthermore, if a multi-value storage circuit according to the present invention is constructed by using a means of forming elements in multiple layers through an insulating film like the recent tertiary element, and by allocating a power supply corresponding to the multi-value of the present invention to each layer, Furthermore, storage density can be improved.
第1図は本発明の第1実施例の回路図、第2図は第1実
施例の入出力特性図、第3図は本発明の第2実施例の回
路図、第4図は第2実施例の人出力特性図である。
1、 2. 11. 12. 13・・・入力インバー
タ、3、 6. 7・・・・・Pチャンネルトランジス
タ、4、 5. 8・・・・・Nチャンネルトランジス
タ、14、 18. 19. 22゜
23.24・・・・・Pチャンネルトランジスタ、15
、 16. 17. 20゜
21.25・・・・・Nチャンネルトランジスタ、9.
26・・・・・・CMOSアナログスイッチ。
特許出願人 日本電気株式会社
代理人 弁理士 桑 井 清 −
第1図
:N入力を圧(V)
第2図人!7]!!憔
第3図
IN 入力T@瓜(V)
第4 図 入巴力特性Fig. 1 is a circuit diagram of the first embodiment of the present invention, Fig. 2 is an input/output characteristic diagram of the first embodiment, Fig. 3 is a circuit diagram of the second embodiment of the invention, and Fig. 4 is a circuit diagram of the second embodiment of the present invention. It is a human output characteristic diagram of an example. 1, 2. 11. 12. 13...Input inverter, 3, 6. 7...P channel transistor, 4, 5. 8...N-channel transistor, 14, 18. 19. 22゜23.24...P channel transistor, 15
, 16. 17. 20°21.25...N-channel transistor, 9.
26...CMOS analog switch. Patent Applicant: NEC Corporation Representative, Patent Attorney Kiyoshi Kuwai - Figure 1: Pressure N input (V) Figure 2: People! 7]! ! Fig. 3 IN Input T @ Melon (V) Fig. 4 Input power characteristics
Claims (1)
を出力する論理回路とアナログスイッチとにより構成さ
れる多値記憶回路において、入力論理値と同じ論理値と
出力する論理回路が論理値の数と同数のそれぞれ電位の
異なる電源と、それぞれ次に高い電位を持つ電源との間
に形成された入力インバータと、それぞれの電源と出力
の間に直列に接続された入力インバータと同数のパスト
ランジスタとから構成され、上記パストランジスタが最
低電位の電源に対してすべてNチャンネルであり最高電
位の電源に対してすべてPチャンネルであり中間電位の
電源に対してNチャンネルとPチャンネルの直列接続を
含みパストランジスタのゲート入力がそれぞれ上記イン
バータの出力と接続されていることを特徴とする多値記
憶回路。In a multi-value memory circuit composed of an analog switch and a logic circuit that outputs the same logic value as the input logic value in response to an input of three or more logic values, the logic circuit that outputs the same logic value as the input logic value is The number of input inverters formed between the same number of power supplies with different potentials and the power supply with the next highest potential, and the same number of input inverters connected in series between each power supply and the output. The pass transistors are all N-channel for the lowest potential power supply, all P-channel for the highest potential power supply, and series connection of N-channel and P-channel for the intermediate potential power supply. A multi-level memory circuit comprising: gate inputs of the pass transistors each connected to an output of the inverter.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63048326A JPH01223696A (en) | 1988-02-29 | 1988-02-29 | Multivalued storage circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63048326A JPH01223696A (en) | 1988-02-29 | 1988-02-29 | Multivalued storage circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01223696A true JPH01223696A (en) | 1989-09-06 |
Family
ID=12800291
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63048326A Pending JPH01223696A (en) | 1988-02-29 | 1988-02-29 | Multivalued storage circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01223696A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012069236A (en) * | 2011-09-23 | 2012-04-05 | Toshiyasu Suzuki | Multi-level buffer means |
JP2016029796A (en) * | 2014-07-16 | 2016-03-03 | 鈴木 利康 | Circuit for distinguishing numerical value for multiple values, circuit for distinguishing multivalued or logic based on principle of hooji algebra, circuit for distinguishing multivalued and logic based on principle of hooji algebra, and circuit for distinguishing numerical value for multi values having numerical value holding function |
CN114171082A (en) * | 2021-11-18 | 2022-03-11 | 清华大学 | Memory cell for tristable storage |
-
1988
- 1988-02-29 JP JP63048326A patent/JPH01223696A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012069236A (en) * | 2011-09-23 | 2012-04-05 | Toshiyasu Suzuki | Multi-level buffer means |
JP2016029796A (en) * | 2014-07-16 | 2016-03-03 | 鈴木 利康 | Circuit for distinguishing numerical value for multiple values, circuit for distinguishing multivalued or logic based on principle of hooji algebra, circuit for distinguishing multivalued and logic based on principle of hooji algebra, and circuit for distinguishing numerical value for multi values having numerical value holding function |
CN114171082A (en) * | 2021-11-18 | 2022-03-11 | 清华大学 | Memory cell for tristable storage |
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