JPH01223696A - Multivalued storage circuit - Google Patents

Abstract

PURPOSE:To simply obtain a level deciding circuit of multivalued logic and to realize a high integration of the circuit without adding a special control to a threshold voltage of each transistor by an input inverter which has been distributed among many electrodes. CONSTITUTION:As voltages corresponding to a ternary truth value, (0V, 5V, 10V) are selected, and these three kinds of power sources are used. An input inverter 1 and an input inverter 2 are provided between power sources 5V and 10V, and between power sources 0V and 5V, respectively. An output of the inverter 1 is connected to gates of a Pch transistor 3 connected to the 10V power source, an Ncn transistor 4 connected to the 5V power source and an Nch transistor 5 connected to the 0V power source. Also, an output of the inverter 2 is connected to Pch transistors 6, 7 and an Nch transistor 8 in the same way. A back gate potential of each transistor becomes a potential of the connected power source. In such a way, as for a ternary logical input, its logical level is discriminated by the inverters 1, 2, and the logical level is synthesized by a bus transistor group of the transistors 3-8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multi-value logic circuit, and more particularly to a multi-value storage circuit capable of storing multi-value data.

[Prior Art] Conventionally, level determination circuits using PMO3) transistors and 8MO3) transistors, each having a different threshold voltage, have been used as logic circuits that output the same logical value as the multi-value input used in this type of memory circuit. CMO the voltage corresponding to the logical value
There is a method that combines logic level synthesis circuits that can be switched using S analog switches (for example, IEICE Transactions v.

L, J70-D P, 42r Micro-power CMOS 4-value storage circuit configuration").

[Problems to be Solved by the Invention] Since the above-mentioned conventional multi-value storage circuit requires the use of transistors with different threshold values in the level determination circuit, the ion implantation process for controlling the threshold value has to be performed in the logic circuit. The process was complicated because it needed to be provided according to the number of logical values.

Furthermore, since a CMOS analog switch is used in the logic level synthesis circuit, the number of elements required is more than twice that of the case where a single channel pass transistor is used. In addition, when a CMOS analog switch is replaced with a single-channel pass transistor in a conventional circuit, the back gate effect causes the combined potential to fall outside the threshold voltage of the transistor, making it impossible to obtain sufficient noise margin. was there.

[Differences between the invention and the prior art] According to the present invention, there is no need to control the threshold value of the transistor used in the logic level determination circuit to a special value, and the logic level synthesis circuit can be configured with a single-channel pass transistor. Table 1 shows the differences between the conventional example and the present invention.

[Means for solving the problem] The multi-level memory circuit of the present invention has the same threshold value formed between the same number of logic values as power supplies with different potentials and the power supplies with the next highest potential. It consists of a level judgment circuit consisting of a value voltage input inverter, and a logic level synthesis circuit consisting of the same number of single-channel pass transistors as the input inverters connected in series between each power supply and a single output.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention, showing the configuration of a ternary storage circuit. (OV, 5V, 10V) were selected as the voltages corresponding to the three-value truth value (0°1.2), and three types of power supplies were used: OV, 5V, and 10V (7). Input inverters 1 and 2 are connected between 5■ and 10V power supplies, respectively.
(1) and 5V power supply. The output of inverter l is connected to the P-channel transistor 3. connected to the IOV power supply.
N-channel transistor 4.0 connected to 5V power supply
(2) It is connected to the gate of the N-channel transistor 5 connected to the power supply, and the output of the inverter 2 is similarly connected to the P-channel transistor 6.7 and the N-channel transistor 8. Furthermore, the back gate potential of the transistors used here is set to the potential of the power supply to which they are connected. For example, the back gate potential of transistors 3 and 6 is IO
It is V.

With the above configuration, the three-value logic input is input to inverters 1 and 2.
The logic level is determined by , and the logic level is synthesized by the pass transistor group of transistors 3 to 8. In other words, a multivalued logic circuit that outputs the same logic value as the input logic value can be realized. As shown in the input/output characteristics in Figure 2, this circuit has the feature that three logic levels can be output without voltage drop. Therefore, by connecting the input and output of this logic circuit, it is possible to easily A memory element is obtained. In the example, CMO is used in the output and input feedback loop.
An S analog switch 9 is provided to ensure that writing to the memory element is performed more reliably. "It is important to drive this analog switch at logic levels corresponding to the highest and lowest potentials of the circuit, in this example IOV and Ov, in order to avoid voltage drops in output feedback.

FIG. 3 is a circuit diagram of a second embodiment of the present invention, which is applied to a four-value storage circuit. By assigning voltages (OV, 5V, IOV, 15V) to truth values (0, L2.3), it is possible to configure a level determination circuit and a logic level synthesis circuit similar to the first embodiment. FIG. 4 shows the results of an operation simulation of a logic circuit consisting of a second level determination circuit and a logic level synthesis circuit.

[Effects of the Invention] As explained above, the present invention uses input inverters distributed between multiple power supplies to easily realize a multi-valued logic level judgment circuit without any special control on the threshold voltage of each transistor. can. Further, since the output voltage of this inverter can sufficiently drive the pass transistor used in the logic level synthesis circuit, there is an advantage that the power supply potential can be transmitted without voltage drop. Therefore, by using the multilevel memory circuit according to the present invention, it becomes possible to realize a highly integrated memory element. In the embodiment, application to a 3-value storage circuit and a 4-value storage circuit is shown, but the invention can be expanded in exactly the same way even when handling multi-values of 6 or more values. Furthermore, if a multi-value storage circuit according to the present invention is constructed by using a means of forming elements in multiple layers through an insulating film like the recent tertiary element, and by allocating a power supply corresponding to the multi-value of the present invention to each layer, Furthermore, storage density can be improved.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of the first embodiment of the present invention, Fig. 2 is an input/output characteristic diagram of the first embodiment, Fig. 3 is a circuit diagram of the second embodiment of the invention, and Fig. 4 is a circuit diagram of the second embodiment of the present invention. It is a human output characteristic diagram of an example. 1, 2. 11. 12. 13...Input inverter, 3, 6. 7...P channel transistor, 4, 5. 8...N-channel transistor, 14, 18. 19. 22゜23.24...P channel transistor, 15
, 16. 17. 20°21.25...N-channel transistor, 9.
26...CMOS analog switch. Patent Applicant: NEC Corporation Representative, Patent Attorney Kiyoshi Kuwai - Figure 1: Pressure N input (V) Figure 2: People! 7]! ! Fig. 3 IN Input T @ Melon (V) Fig. 4 Input power characteristics

Claims (1)

[Claims] In a multi-value memory circuit composed of an analog switch and a logic circuit that outputs the same logic value as the input logic value in response to an input of three or more logic values, the logic circuit that outputs the same logic value as the input logic value is The number of input inverters formed between the same number of power supplies with different potentials and the power supply with the next highest potential, and the same number of input inverters connected in series between each power supply and the output. The pass transistors are all N-channel for the lowest potential power supply, all P-channel for the highest potential power supply, and series connection of N-channel and P-channel for the intermediate potential power supply. A multi-level memory circuit comprising: gate inputs of the pass transistors each connected to an output of the inverter.