JP5881432B2 - Level conversion circuit - Google Patents

Description

  The present invention relates to a level conversion circuit including a current limit circuit that can perform level conversion to different voltages for both high level and low level, and has a constant current during steady state and an increase in current during level transition.

  FIG. 7 shows a typical level conversion circuit conventionally used (see, for example, Patent Document 1). This level conversion circuit is used when the low level is common to GND and the high level voltage is level-shifted from VDDL to VDDH (VDDL <VDDH). The NMOS transistor MN21 and the PMOS transistor MP21 constitute a first stage inverter, and the NMOS transistor MN22 and the PMOS transistor MP22 constitute a second stage inverter. The NMOS transistors MN23 and MN24 and the PMOS transistors MP23 and MP24 constitute an output circuit controlled by the output of the first stage inverter and the output of the second stage inverter.

  When the signal amplitude of the input terminal IN is GND-VDDL, when the input terminal IN is at high level (= VDDL), the node N21 is at low level (= GND), the node N22 is at high level (= VDDL), and the NMOS transistor MN24 is turned off and NMOS transistor MN23 is turned on. Then, the PMOS transistor MP24 is turned on, and the voltage of the output terminal OUT becomes high level (= VDDH). At this time, the transistor MP23 is turned off because the gate voltage becomes VDDH. On the other hand, when the input terminal IN is at the low level (= GND), the operations of the transistors MN23, NM24, MP23, and MP24 are reversed, and the voltage at the output terminal OUT is at the low level (= GND). Therefore, if the input terminal IN is at a high level (= VDDL), the output terminal OUT is at a high level (VDDH), and if the input terminal IN is at a low level (= GND), the output terminal OUT is also at a low level (= GND). Thus, only the high level voltage is level-converted from VDDL to VDDH.

  FIG. 8 shows another level conversion circuit (see, for example, Patent Document 2). This is a circuit particularly used for a high voltage circuit. This level conversion circuit includes NMOS transistors MN31, MN32, and MN33, a PMOS transistor MP31, a Zener diode ZD31, and resistors R31 and R32.

  When the input terminal IN is at a high level (= VDDL), the transistor MN31 is turned on, the transistor MP31 is turned off, and the transistors MN32 and MN33 are turned off. For this reason, the drain of the transistor MN33 is pulled up by the resistor R32 connected to the power supply VDDH, and the voltage of the output terminal OUT becomes VDDH. When the input terminal IN is at a low level (= GND), the transistor MP31 is turned on and the transistor MN31 is turned off, and the current determined by the potential difference between the power supply voltage VDDL and the drain of the transistor MN32 and the resistor R31 is the drain current of the transistor MN32. Flowing. Since the transistors MN32 and MN33 have a current mirror configuration, the drain current of the transistor MN32 is mirrored to the drain current of the transistor MN33, and the drain current of the transistor MN33 is larger than the current of the resistor R32 determined by the Zener voltage Vz3 of the Zener diode ZD31. For example, a current flows through the Zener diode ZD31, and the drain voltage of the transistor MN33 is clamped by a voltage (= VDDH−Vz3) lower than the power supply voltage VDDH by the Zener voltage Vz3 of the Zener diode ZD31, and this is output to the output terminal OUT. Therefore, if the input terminal IN is the power supply voltage VDDL, the output of the level conversion circuit is VDDH, and if the input terminal IN is GND, the output of the level conversion circuit is “VDDH−Vz3”, which is different for both the high level and the low level. Level converted to voltage.

JP 7-142968 A JP-A-11-68540

  However, in the level conversion circuit of FIG. 8, when the input terminal IN is at a low level, a current flows through the NMOS transistors MN32 and MN33, leading to an increase in current consumption. Further, when the level conversion circuit output is high level, the gate of the next stage PMOS transistor (not shown) connected to the output terminal OUT is driven only by the resistor R32, and when it is low level, the drain constant current of the transistor MN33 is driven. Since the gate of the next-stage transistor is driven, the time for the voltage at the output terminal OUT to transition from low level to high level and the time for transition from high level to low level tend to be longer. In order to further reduce the current consumption, it is necessary to reduce the drain current of the transistor MN33, which causes a problem that the transition time from the high level to the low level becomes long.

  Further, in the level conversion circuit of FIG. 7, in the state transition, one of the MOS transistors is switched from on to off and the other is switched from off to on. Therefore, the transition time can be shortened, and current consumption does not flow in the steady state. There is a problem that only the voltage level on the power supply side can be converted.

  An object of the present invention is to provide a level conversion circuit that can perform level conversion to different voltages for both high and low levels, reduce current consumption during steady state, and shorten the transition time during level transition. .

In order to solve the above-described problem, a level conversion circuit according to a first aspect of the present invention includes an input terminal to which a voltage having amplitudes of a first high voltage and a first low voltage is input, and is turned on by the voltage of the input terminal. A signal input unit comprising a first NMOS transistor to be turned off and a first current limit circuit connected to the drain of the first NMOS transistor, the first current limit circuit and a second high voltage power source A first Zener diode connected between the terminals, a second resistor connected in parallel to the first Zener diode, and the second high voltage and the second low voltage applied as power supply voltages. A signal output comprising a first inverter that inputs, inverts and outputs a voltage corresponding to the voltage of the first node at the common connection point of the first current limit circuit and the first Zener diode. A first resistor having one end connected to the drain of the first NMOS transistor; the first resistor connected between a gate and a source; A second NMOS transistor connected to a first current source connected to a high-voltage power supply terminal, a source connected to the other end of the first resistor, and a drain connected to the first node. A first high-voltage NMOS transistor having a gate connected to a drain of the second NMOS transistor; the first low voltage; the first high voltage; the second low voltage; The voltage is set higher in the order of 2 high voltages.
According to a second aspect of the present invention, in the level conversion circuit according to the first aspect, when the first NMOS transistor is turned on / off by the voltage of the input terminal, the signal input unit is turned off / on. And a second current limit circuit connected to the drain of the third NMOS transistor, and the signal output unit includes the second current limit circuit and a second high-voltage power source. A second Zener diode connected to the terminal, a fourth resistor connected in parallel to the second Zener diode, and a voltage corresponding to the voltage of the first node are input to the first terminal. In addition, a voltage corresponding to the voltage of the second node at the common connection point of the second current limit circuit and the second Zener diode is input to the second terminal to perform the latch operation. And a logic level determination circuit for inputting a voltage output from a third terminal to the first inverter, and one end of the second current limit circuit is connected to the drain of the third NMOS transistor. A fourth NMOS transistor in which a third resistor is connected between the gate and the source, and a drain is connected to a second current source connected to the first high-voltage power supply terminal; A second high voltage NMOS transistor having a source connected to the other end of the third resistor, a drain connected to the second node, and a gate connected to the drain of the fourth NMOS transistor; In the logic level determination circuit, the first terminal is a voltage obtained by subtracting the voltage of the second Zener diode from the second high voltage, and the second terminal is When the high voltage is 2, the third terminal is set to the second low voltage, the first terminal is the second high voltage, and the second terminal is the second high voltage to the first high voltage. When the voltage obtained by subtracting the voltage of the Zener diode is used, the third terminal is set to the second high voltage.
According to a third aspect of the present invention, in the level conversion circuit according to the second aspect, the second resistor includes a seventh PMOS having a drain connected to the second high-voltage power supply terminal and a gate fixedly biased. And a ninth NMOS transistor diode-connected between the drain of the seventh PMOS transistor and the first node, and a common drain of the seventh PMOS transistor and the ninth NMOS transistor. An eighth PMOS transistor having a terminal connected to the first terminal of the logic level determination circuit, the fourth resistor having a drain connected to the second high-voltage power supply terminal and a gate fixedly biased; A tenth NMOS transistor diode-connected between the drain of the eighth PMOS transistor and the second node. Consists of a register, the common drain terminal of the eighth PMOS transistor first 10 NMOS transistor is connected to a second terminal of the logic level setting circuit, characterized in that.
According to a fourth aspect of the present invention, in the level conversion circuit according to the third aspect, a ninth PMOS transistor is connected in parallel to the seventh PMOS transistor, and a tenth PMOS transistor is connected to the eighth PMOS transistor. In parallel connection, when the first node becomes a voltage obtained by subtracting the voltage of the first Zener diode from the second high voltage, the ninth PMOS transistor is turned on, and the second node is A level conversion auxiliary circuit for turning on the tenth PMOS transistor when a voltage obtained by subtracting a voltage of the second Zener diode from a second high voltage is provided.
According to a fifth aspect of the present invention, in the level conversion circuit according to the first aspect, the gate is connected to the first node and the second low-voltage power supply terminal is connected to the source in the signal output unit. An eleventh NMOS transistor and a third current limit circuit connected between the drain of the eleventh NMOS transistor and the second high-voltage power supply terminal are added, and the third current limit circuit is added. A fifth resistor having one end connected to the drain of the eleventh NMOS transistor, and a third resistor having the drain connected between the gate and source and the drain connected to the second high voltage. A twelfth NMOS transistor having a current source connected thereto, and a thirteenth NM having a source connected to the other end of the fifth resistor and a gate connected to the drain of the twelfth NMOS transistor. An S transistor, an eleventh PMOS transistor having a drain and a gate connected to the drain of the thirteenth NMOS transistor and a drain connected to the second high voltage power supply terminal; the eleventh PMOS transistor and a current mirror; And a twelfth PMOS transistor connected in parallel to the first resistor.
According to a sixth aspect of the present invention, in the level conversion circuit according to any one of the first to fifth aspects, the first high voltage and the first low voltage are interchanged, and the second high voltage and the second low voltage are interchanged. Are switched to each other, the voltage is set higher in the order of the second low voltage, the second high voltage, the first low voltage, and the first high voltage after the replacement, and the NMOS transistor is The PMOS transistor is replaced with an NMOS transistor, respectively.

According to the first aspect of the present invention, it is possible to make the output terminal have different voltages for both the high level and the low level with respect to the input terminal. The first current limit circuit allows a large current to flow transiently when the input terminal transitions from the low level to the high level, so that the transition time from the low level to the high level of the output terminal can be shortened, and a constant current is maintained in the steady state. Since this is an operation, the current consumption can be reduced.
According to the second aspect of the present invention, the input voltage of the first inverter transits in a short time even when the input terminal transits from the high level to the low level by the second current limit circuit and the logic level determination circuit. Therefore, the through current of the first inverter can be suppressed as compared with the configuration of the first aspect.
According to the invention of claim 3, the element layout area on the chip can be reduced by replacing the second and fourth resistors with the seventh and eighth PMOS transistors. In addition, by inserting the diode-connected ninth and tenth NMOS transistors, it is possible to improve the gate breakdown voltage protection of the PMOS transistor of the logic level determination circuit, and the first and second high breakdown voltage NMOS transistors. It is possible to make the impedance of the drain lower than when the drains of the seventh and eighth transistors are directly connected.
According to the invention of claim 4, the transition time of the transition from the high level of the output terminal to the low level with respect to the transition of the input terminal from the high level to the low level can also be shortened.
According to the fifth aspect of the present invention, since the signal output unit uses a current limit circuit similar to the current limit circuit of the signal input unit, the transition from the high level to the low level of the input terminal and the low level to the high level It is possible to shorten the transition time of both of the transitions to, and the circuit scale can be reduced to half that of the inventions according to claims 2 to 4 that achieve the same effect.

1 is a circuit diagram illustrating a level conversion circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the level conversion circuit of 2nd Example of this invention. It is a circuit diagram which shows the level conversion circuit of the 3rd Example of this invention. It is a circuit diagram which shows the level conversion circuit of the 4th Example of this invention. It is a circuit diagram which shows the level conversion circuit of the 5th Example of this invention. It is a figure showing the voltage level of the input-output signal of this invention. It is a circuit diagram which shows the level conversion circuit of the conventional circuit. It is a circuit diagram which shows another level conversion circuit of a conventional circuit.

First Embodiment FIG. 1 shows a level conversion circuit according to a first embodiment. MN1 is an NMOS transistor whose gate is connected to the input terminal IN. Reference numeral 1 denotes a current limit circuit, which includes an NMOS transistor MN2, a depletion type NMOS transistor DMN1, a resistor R1, and a current source I1, and operates with a power supply voltage VDD3. The transistors MN1 and MN2 are low breakdown voltage elements. The signal input unit composed of the transistor MN1 and the current limit circuit 1 is referred to as a low side circuit.

  The signal output unit includes a Zener diode ZD1, a resistor R2, and an inverter INV1, and operates with the power supply voltage VDD2. The Zener voltage Vz1 of the Zener diode ZD1 is equal to or lower than the rated voltage of the transistors MN1 and MN2 of the low withstand voltage elements, and the inverter INV1 is configured with the low withstand voltage elements. Therefore, VDD2 is set below the rated voltage of the low withstand voltage element. This signal output unit is referred to as a high side circuit.

Here, the power supply voltage of the high side circuit is set at the power supply voltage VDD1 for GND,
VDD1> (VDD2 + VDD3)
And For example, the power supply voltage is set such that VDD1 = 30V, VDD2 = 5V, VDD3 = 3V. For the transistor DMN1 connected to both the low side circuit and the high side circuit, an element that can withstand the maximum voltage of the voltage VDD1 is used. In this embodiment, a high breakdown voltage element of 30 V or more is used for the transistor DMN1.

First, the state when the input signal of the input terminal IN transits from the low level VL1 (= GND) to the high level VH1 (= VDD3) will be described. Immediately after the transition, the transistor MN1 is turned on, and the maximum current Id1_max determined by the source voltage of the transistor DMN1 and the resistor R1 flows instantaneously. Id1_max = (VDD3-Vgsdmn1) / R1 where Vgsdmn1 is the gate-source voltage of the transistor DMN1. As a result, the transistor MN2 operates, and the drain current Id1 of the transistor MN1 at the subsequent steady state is
Id1 = Vgsmn2 / R1. Here, Vgsmn2 is the gate-source voltage of the transistor MN2, and is determined by the threshold voltage of the transistor MN2 and the current value of the current source I1. If the parasitic capacitance is increased by increasing the transistor size of the transistor MN2 or if a capacitor is connected between the gate and source of the transistor MN2, the transistor MN1 is turned on and the maximum current Id1_max flows, and then the steady current Id1. The time to become can be lengthened.

In the high side circuit, the current of the transistor DMN1 flows through the Zener diode ZD1 and the resistor R2, and the anode voltage (node N1) of the Zener diode ZD1 drops from VDD1 to the Zener voltage Vz1. Note that the resistance value of the resistor R2 is set so that the voltage at the node N1 becomes “VDD1-Vz1” in a state where the current Id1 flows through the drain of the transistor DMN1. When the voltage of the node N1 transitions from VDD1 to “VDD1-Vz1”, the output voltage of the inverter INV1 transitions from the low level VL2 (= VDD1-VDD2) to the high level VH2 (= VDD1). In the middle of this transition, the drain current of the transistor DMN1 becomes the maximum current Id1_max, and the charge of the parasitic capacitance at the gate input of the inverter INV1 is sharply manipulated, so that the output voltage from the low level VL2 of the inverter INV1 becomes high. The transition time to level VH2 is shortened. At a constant time, the current Iz1 flowing through the Zener diode ZD1 is
Iz1 = Id1-Vz1 / R2
Thus, the voltage of the node N1 is held at “VDD1-Vz1”, and the output voltage of the inverter INV1 becomes the high level VH2 (= VDD1). The reason why the current is clamped by the low-side circuit in the steady state is to prevent the Zener diode ZD1 from being destroyed due to the continuous high current.

Next, a case where the input signal of the input terminal IN transitions from the high level VH1 (= VDD3) to the low level VL1 (= GND) will be described. When the input signal becomes the low level VL1, the transistor MN1 is turned off and the drain current does not flow to the transistor DMN1. Then, no current flows through the Zener diode ZD1 of the high side circuit, and when the drain of the transistor DMN1 is viewed from the anode (node N1), the impedance becomes high impedance. The voltage of the node N1 gradually increases with the resistor R2 serving as a pull-up resistor, and finally reaches a high level VH2 (= VDD1). The time for this state transition is determined by the parasitic capacitance and the time constant of the resistor R2 at the anode connection portion of the Zener diode ZD1. The resistor R2 has a relatively large resistance value because the voltage at the node N1 is set to “VDD1-Vz” when the current Id1 flows, and the output voltage of the inverter INV1 is at the high level VH2 (= VDD1). The transition time from the low level VL2 (= VDD1 to VDD2) is longer than the transition time from the low level VL2 to the high level VH2. In addition, a large through current easily flows through the inverter INV1 as long as the transition time is long. FIG. 6 shows the above operation state in a simplified manner. A pulse having the maximum value of the voltage VDD3 at the input terminal IN is converted into a pulse having the maximum value of the voltage VDD1 and an amplitude of the voltage VDD2. Appears at terminal OUT.

  Thus, in the first embodiment, the voltage level of the output signal can be different from the high level and the low level with respect to the input signal. Also, when the input signal transitions from the low level to the high level, a large drain current flows transiently in the transistor DMN1, and the transition time from the low level to the high level of the output signal is shortened. Further, since the transistors DMN1 and MN2 and the resistor R1 operate at a constant current in a steady state, the current can be reduced to the minimum bias current at which the Zener diode ZD1 can maintain the constant voltage Vz1, and the current consumption can be reduced.

Second Embodiment FIG. 2 shows a level conversion circuit according to a second embodiment. In the configuration of the low side circuit, a pair of current limit circuits 1A, 2 having the same configuration is connected. In the current limit circuit 1A, unlike the current limit circuit 1 of FIG. 1, a PMOS transistor MP2 is connected as the current source I1. The current limit circuit 2 includes a resistor R3, an NMOS transistor MN4, a depletion type NMOS transistor DMN2, and a PMOS transistor MP3 as a current source I2. The transistors MP2 and MP3 are current mirror connected to the PMOS transistor MP1 that supplies the current Iref1 of the constant current source, and the current Iref1 flows through the transistors MP2 and MP3. A signal obtained by inverting the gate input signal of the transistor MN1 of the current limit circuit 1A by the inverter INV2 is input to the gate of the NMOS transistor MN3 of the current limit circuit 2.

  In the configuration of the high side circuit, as in the high side circuit of FIG. 1, a Zener diode ZD1 and a resistor R2 are connected to the drain (node N1) of the transistor DMN1 of the current limit circuit 1A, and the transistor DMN2 of the current limit circuit 2 is connected. A zener diode ZD2 and a resistor R4 are connected to the drain (node N2). Reference numeral 3 denotes a logic level determination circuit which inputs the voltages of the nodes N1 and N2 to the nodes N3 and N4 and outputs the voltage from the node N6 to the inverter INV1. The logic level determination circuit 3 includes NMOS transistors MN5 to MN8 and PMOS transistors MP4 and MP5 and performs a latch operation. Here, the configuration on the side of the Zener diode ZD1 and the resistor R2 from the transistor MN1 and the current limit circuit 1A connected to the transistor MN1 is set as the non-inverting operation side, and the configuration on the side of the Zener diode ZD2 and the resistor R4 from the current limit circuit 2 connected to the transistor MN3. Is the reverse operation side.

  A state when the input signal of the input terminal IN transits from a low level (= GND) to a high level (= VDD3) will be described. The non-inversion operation side is the same as the operation of FIG. 1, and the voltages of the nodes N1 and N3 transition from VH2 (= VDD1) to VL2 (= VDD1-VDD2). On the inverting operation side, the transistor MN3 that inputs the signal obtained by inverting the input signal with the inverter INV2 to the gate changes from on to off, the current of the transistor DMN2 stops flowing, and the voltages of the nodes N2 and N4 of the high side circuit are The pull-up of the resistor R4 makes a transition from the low level VL2 (= VDD1-VDD2) to the high level VH2 (= VDD1).

In the logic level determination circuit 3, since the transistor MN7 connected to the node N3 is turned off and the transistor MP4 is turned on, the drain voltage (node N5) of the transistor MP4 becomes VDD1, and the transistor MN6 is turned on. On the other hand, the transistor MN8 node N4 is connected is turned on, the transistor MP5 is turned off, the voltage of the node N 6 is turned to the low level VL2 (= VDD1-VDD2), the transistor MN5 is turned off. As described above, the node N6 that is finally the input of the inverter INV3 transitions from the high level VH2 (= VDD1) to the low level VL2 (= VDD1-VDD2), so that the voltage of the output terminal OUT is changed from the low level VL2 to the high level. Transition to VH2.

  Regarding the state when the input signal of the input terminal IN transits from the high level VH1 (= VDD3) to the low level VL1 (= GND), the operation on the non-inversion operation side and the inversion operation side is switched. Since the operations of the transistors MN5, MN7, MP4 and the transistors MN6, MN8, MP5 are switched, the voltage at the output terminal OUT changes from the high level VH2 (= VDD1) to the low level VL2 (= VDD1-VDD2).

In this embodiment, when the voltage of the node N2 on the inverting operation side decreases from VDD1 to “VDD1-Vz”, the maximum drain current flows through the transistor DMN2, so that the gate voltage of the transistor MP5 is changed from the high level VH2 to the low level in a short time. Transition to VL2 can also shorten the transition time of the voltage at the output terminal OUT from the high level VH2 (= VDD1) to the low level VL2 (= VDD1-VDD2). Further, when the gate input of the transistor MN3 transitions from the high level VH1 (= VDD3) to the low level VL1 (= GND), the node N2 has a low level VL2 (= VDD1-VDD2) due to the parasitic capacitance of the resistor R4 and the Zener diode ZD2. ) To the high level VH2 (= VDD1) becomes longer, but when the voltage at the node N2 exceeds the threshold voltage of the transistor MN8, the voltage at the drain (node N6) of the transistor MN8 becomes the low level VL2 (= VDD1-VDD2). ) And the output of the inverter INV3 transitions from the low level VL2 (= VDD1-VDD2) to the high level VH2 (= VDD1), so that the output of the inverter INV1 in the circuit of FIG. (= VDD1 Shorter than the time to transition to the VDD2).

As described above, in the second embodiment, the input of the inverter INV 1 is generated by the current limit circuit 2 and the logic level determination circuit 3 so that the transition time from the high level to the low level and from the low level to the high level is short. Therefore, the through current of the inverter INV 1 can be suppressed as compared with the first embodiment.

Third Embodiment FIG. 3 shows a level conversion circuit according to a third embodiment. In this embodiment, PMOS transistors MP7 and MP8 are used in place of the resistors R2 and R4 of the high-side circuit of FIG. 2, and these transistors MP7 and MP8 are connected in a current mirror manner to a transistor MP6 that passes the current Iref2 of the current source. The constant current is supplied to the transistors MP7 and MP8. In addition, diode-connected NMOS transistors MN9 and MN10 are connected to the drains of the transistors MP7 and MP8 so that the drain voltage does not exceed the rating even instantaneously. The node N3 of the logic level determination circuit 3 is connected to the common drain of the transistors MP7 and MN9, and the node N4 is connected to the common drain of the transistors MP8 and MN10.

In this embodiment, the circuit configuration of the level conversion circuit of FIG. 2 and the anode portions (nodes N1, N2) of the Zener diodes ZD1, ZD2 are different, but the voltage transition of the nodes N1, N2 due to the input signal of the input terminal IN is as shown in FIG. The voltage transition of the output terminal OUT with respect to the signal state of the input terminal IN is also the same as in FIG. If the resistors R2 and R4 are replaced with constant current PMOS transistors MP7 and MP8 as in this embodiment, the layout area on the chip is reduced. Further, diode transistors connected MN9, by inserting the MN 10, it is possible to improve the gate breakdown voltage protection logic level setting circuit 3 of the PMOS transistor MP4, MP5, the transistor drain impedance of NMOS transistor DMNl, DMN2 It becomes possible to make it lower than connecting the drains of MP7 and MP8 directly.

<Fourth Embodiment> FIG. 4 shows a level conversion circuit according to a fourth embodiment. In the present embodiment, PMOS transistors MP9 and MP10 functioning as switches are connected in parallel with the transistors MP7 and MP8 of the level conversion circuit of FIG. 3, and the operation is performed using the voltages of the nodes N5 and N6 of the level determination circuit 3 as inputs. The level conversion auxiliary circuit 4 controls the gates of the transistors MP9 and MP10. The level conversion auxiliary circuit 4 includes inverters INV3 and INV1, connected to nodes N5 and N6, a NOR circuit NOR1, an SR flip-flop 41, and NAND circuits NAND1 and NAND2.

The operation of this embodiment is as follows. On the non-inverting operation side, when the voltage at the input terminal IN changes from the low level VL1 (= GND) to the high level VH1 (= VDD3), the transistor MN1 is turned on, a current flows through the Zener diode ZD1, and the voltage at the node N1 decreases. Since the transistor MP4 is turned on and the MN7 is turned off, the voltage of the node N5 becomes the high level VH2 (= VDD1).

  On the other hand, on the inverting operation side, the output of the inverter INV2 changes from the high level VH1 (= VDD3) to the low level VL1 (= GND), so that the transistor MN3 is turned off, the voltage at the node N2 rises, and the transistor MN8 is turned on. Since the transistor MP5 is turned off, the node N6 becomes the low level VL2 (= VDD1-VDD2). At this time, the transition time of the voltage at the node N6 is determined by the time constant between the current of the transistor MP8 and the parasitic capacitance generated at the gate connection point of the transistor MN8.

  The output of the inverter INV3 connected to the node N5 becomes the low level VL2 (= VDD1-DD2), and the output of the inverter INV1 connected to the node N6 becomes the high level VH2 (= VDD1). Since the voltage transition is slower than the voltage transition of the node N5, when the output of the inverter INV3 becomes the low level VL2, the output of the inverter INV1 is still at the low level VL2, and the output Q of the SR flip-flop 41 is the low level VL2. Since the transition from (= VDD1-DD2) to the high level VH2 (= VDD1) and the output of the NOR circuit NOR1 also transitions from the low level VL2 (= VDD1-DD2) to the high level VH2 (= VDD1), the output of the NAND circuit NAND2 Is low from high level VH2 (= VDD1). The transition to the level VL2 (= VDD1-DD2), turn on the transistor MP10.

  Then, the transistor MP10 is turned on earlier than the rising transition of the gate voltage (node N4) of the transistor MN8 due to only the constant current of the transistor MP8, so that the gate voltage (node N4) of the transistor MN8 rises quickly in a short time. Can be made.

  When the voltage of the input terminal IN changes from the high level VH1 (= VDD3) to the low level VL1 (= GND), the non-inversion operation side and the inversion operation side, the drain voltage (nodes N3 and N4) transitions of the transistors MN7 and MN8 are connected. The operation of the level conversion auxiliary circuit 4 is the reverse of the above operation.

  Thereby, in the level conversion circuit of the third embodiment of FIG. 3, when the signal of the input terminal IN transits from the low level VL1 (= GND) to the high level VH1 (= VDD3), the low level VH2 ( = VDD1-VDD2) to the high level VL2 (= VDD1), the delay time of the transition can be shortened. In addition, in the level conversion circuit of the fourth embodiment of FIG. 4, the signal at the input terminal IN is at the high level. When transitioning from VH1 (= VDD3) to low level VL1 (= GND), the delay time of transition from the high level VL2 (= VDD1) to the low level VL2 (= VDD1-VDD2) of the output terminal OUT may be shortened. it can.

  Thus, in this embodiment, by adding the level conversion auxiliary circuit 4, the transition time of the transition from the high level to the low level of the output terminal OUT when the signal of the input terminal IN transitions from the high level to the low level is also obtained. Can be shortened.

Fifth Embodiment FIG. 5 shows a level conversion circuit according to a fifth embodiment. In this embodiment, the low side circuit is the same as the level conversion circuit of FIG. The high side circuit includes a Zener diode ZD1, a pull-up PMOS transistor MP7, a PMOS transistor MP6 and a constant current source Iref2 that are bias sources, an NMOS transistor MN11, and a current limit circuit 5. The current limit circuit 5 includes NMOS transistors MN12 and MN13, PMOS transistors MP11 and MP12, a resistor R5, and a constant current source I3. Then, the output of the inverter INV1 having the node N1 at the common connection point of the drain of the transistor DMN1 of the low side circuit, the drain of the transistor MP7 of the high side circuit, the drain of the transistor MP12, and the gate of the transistor MN11 as an input terminal Connected to OUT. The high-side current limit circuit 5 operates in the same manner as the low-side current limit circuit 1.

The operation of this embodiment is as follows. The operation on the low side is the same as that of the level conversion circuit of FIG. When the input signal of the input terminal IN transits from the low level VL1 (= GND) to the high level VH1 (= VDD3), the drain current of the transistor DMN1 tries to pass a current larger than the limit current (Id1) in a short time. . At this time, if the total bias current in the transistors MP7 and MP12 is set to be smaller than the drain current (Id1_max) of the transistor DMN1 at this time, the voltage of the node N5 becomes “VDD1-Vz1”, and VDD2 is less than Vz1. If so, the transistor MN11 is turned off and the bias current of the transistor MP12 becomes zero. The output of the inverter INV1 transitions from the low level VL2 (= VDD1-VDD2) to the high level VH2 (= VDD1).

  When the input signal of the input terminal IN transits from the high level VH1 (= VDD3) to the low level VL1 (= GND), the drain current of the transistor DMN1 becomes 0, and the voltage of the node N1 rises due to the bias current of the transistor MP7. When this voltage exceeds the threshold voltage of the transistor MN11, the transistor MN11 is turned on to lower the drain voltage, the transistor MN12 is turned on, and the transistor MN13 is also turned on so that a current flows through the transistor MP11 and a bias current flows through the transistor MP12. Flowing. Then, the gate voltage of the transistor MN11 is changed to the high level in a time shorter than the time required to change the gate voltage of the transistor MN11 to the high level by the bias current of the transistor MP7, and the voltage of the node N1 is changed to the low level VL2 (= From VDD1 to VDD2), the level changes to the high level VH2 (= VDD1). In the steady state, the drain current of the transistor MN11 has a value determined by the threshold voltage of the transistor MN12 and the resistor R5. The output of the inverter INV1 transitions from the high level VH2 (= VDD1) to the low level VL2 (= VDD1-VDD2).

  In the embodiment of FIG. 5, the current clamp circuit 5 having the same configuration as that of the current clamp circuit 1 on the low side is used on the high side, so that the input signal at the output terminal OUT is changed from the high level VH2 (= VDD1) to the low level VL21. The circuit scale for shortening both the time of transition to (= VDD1-VDD2) and the transition from the low level VL2 to the high level VH2 and realizing the same effect as in the second to fourth embodiments. 2 to half of the fourth embodiment.

<Other examples>
In the first to fifth embodiments described above, the first low voltage (= VL1 = GND), the first high voltage (= VH1 = VDD3), and the second low voltage (= VL2 = VDD1- VDD2) and the second high voltage (VH2 = VDD1) are set higher in this order, but the first high voltage and the first low voltage are interchanged, and the second high voltage and the second low voltage Are replaced with each other, and when the second low voltage, the second high voltage, the first low voltage, and the first high voltage are set higher in this order, the NMOS transistor is replaced with the PMOS transistor. If the transistors are replaced with NMOS transistors, the operation is the same.

1, 1A, 2, 5: Current limit circuit 3: Logic level determination circuit 4: Level conversion auxiliary circuit, 41: RS flip-flop circuit

Claims (6)

An input terminal to which a voltage having an amplitude of a first high voltage and a first low voltage is input, a first NMOS transistor that is turned on / off by the voltage of the input terminal, and a drain of the first NMOS transistor A signal input unit consisting of a first current limit circuit,
A first Zener diode connected between the first current limit circuit and a second high voltage power supply terminal; a second resistor connected in parallel to the first Zener diode; The high voltage and the second low voltage are applied as power supply voltages, and a voltage corresponding to the voltage of the first node at the common connection point of the first current limit circuit and the first Zener diode is input and inverted. And a signal output unit including a first inverter that outputs to the output terminal,
The first current limit circuit includes a first resistor having one end connected to a drain of the first NMOS transistor, and a first resistor connected between a gate and a source and the first high voltage applied to a drain. A second NMOS transistor to which a first current source connected to the power supply terminal of the first NMOS transistor is connected, a source connected to the other end of the first resistor, a drain connected to the first node, and a gate connected to the first node. A first high-voltage NMOS transistor connected to the drain of the two NMOS transistors,
The voltage is set higher in the order of the first low voltage, the first high voltage, the second low voltage, and the second high voltage.
A level conversion circuit characterized by that.
The level conversion circuit according to claim 1,
The signal input unit includes a third NMOS transistor that is turned off / on when the first NMOS transistor is turned on / off by the voltage of the input terminal, and a third NMOS transistor connected to a drain of the third NMOS transistor. 2 current limit circuits are added,
The signal output unit includes a second Zener diode connected between the second current limit circuit and a second high-voltage power supply terminal, and a fourth Zener diode connected in parallel to the second Zener diode. Resistor and a voltage corresponding to the voltage of the first node are input to the first terminal and correspond to the voltage of the second node at the common connection point of the second current limit circuit and the second Zener diode A logic level determination circuit for inputting a voltage to be input to the second terminal, performing a latch operation, and inputting a voltage output from the third terminal to the first inverter, and
The second current limit circuit includes a third resistor having one end connected to the drain of the third NMOS transistor, and the third resistor connected between a gate and a source and the first high voltage connected to the drain. A fourth NMOS transistor to which a second current source connected to the power supply terminal of the second NMOS transistor is connected, a source connected to the other end of the third resistor, a drain connected to the second node, and a gate connected to the second node. And a second high voltage NMOS transistor connected to the drain of the four NMOS transistors,
The logic level determination circuit is configured such that when the first terminal is a voltage obtained by subtracting the voltage of the second Zener diode from the second high voltage and the second terminal is the second high voltage. 3 terminal is set to the second low voltage, the first terminal is the second high voltage, and the second terminal is a voltage obtained by subtracting the voltage of the first Zener diode from the second high voltage. At this time, the third terminal is set to the second high voltage.
A level conversion circuit characterized by that.
The level conversion circuit according to claim 2, wherein
The second resistor includes a seventh PMOS transistor having a drain connected to the second high-voltage power supply terminal and a gate fixedly biased, and the drain of the seventh PMOS transistor and the first node. A ninth NMOS transistor having a diode connection therebetween, and a common drain terminal of the seventh PMOS transistor and the ninth NMOS transistor is connected to the first terminal of the logic level determination circuit;
The fourth resistor includes an eighth PMOS transistor having a drain connected to the second high-voltage power supply terminal and a gate fixedly biased, and the drain of the eighth PMOS transistor and the second node. A tenth NMOS transistor diode-connected in between, and a common drain terminal of the eighth PMOS transistor and the tenth NMOS transistor is connected to a second terminal of the logic level determining circuit,
A level conversion circuit characterized by that. The level conversion circuit according to claim 3,
A ninth PMOS transistor is connected in parallel to the seventh PMOS transistor, and a tenth PMOS transistor is connected in parallel to the eighth PMOS transistor,
When the first node becomes a voltage obtained by subtracting the voltage of the first Zener diode from the second high voltage, the ninth PMOS transistor is turned on, and the second node is set to the second high voltage. A level conversion auxiliary circuit that turns on the tenth PMOS transistor when a voltage obtained by subtracting the voltage of the second Zener diode from the voltage is provided;
A level conversion circuit characterized by that. The level conversion circuit according to claim 1,
An eleventh NMOS transistor having a gate connected to the first node and a source connected to the second low-voltage power supply terminal; a drain of the eleventh NMOS transistor; And a third current limit circuit connected to the high voltage power supply terminal of
The third current limit circuit includes a fifth resistor having one end connected to the drain of the eleventh NMOS transistor, and the fifth resistor connected between a gate and a source and the second high voltage connected to the drain. A twelfth NMOS transistor connected to the third current source connected to the first NMOS transistor; a thirteenth NMOS transistor connected to the other end of the fifth resistor; and a gate connected to the drain of the twelfth NMOS transistor; An NMOS transistor, an eleventh PMOS transistor whose drain and gate are connected to the drain of the thirteenth NMOS transistor and whose drain is connected to the second high-voltage power supply terminal, the eleventh PMOS transistor and the current mirror And a twelfth PMOS transistor connected in parallel with the first resistor.
A level conversion circuit characterized by that. The level conversion circuit according to any one of claims 1 to 5,
The first high voltage and the first low voltage are interchanged with each other, the second high voltage and the second low voltage are interchanged with each other, and the second low voltage and the second high voltage after the replacement are interchanged. The level conversion is characterized in that the voltage is set higher in the order of the voltage, the first low voltage, and the first high voltage, and the NMOS transistor is replaced with a PMOS transistor and the PMOS transistor is replaced with an NMOS transistor. circuit.

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