JP7136622B2 - level conversion circuit - Google Patents

Description

The present invention relates to a level conversion circuit that converts the voltage of an input terminal into different voltages for both high level and low level and outputs the same to an output terminal.

である。電圧は、

の関係にある。ＭＰ１１～ＭＰ１５はＰＭＯＳトランジスタ、ＭＮ１１～ＭＮ１８はＮＭＯＳトランジスタ、ＤＭＮ１、ＤＭＮ２は高耐圧ＮＭＯＳトランジスタである。また、ＺＤ１、ＺＤ２はツェナーダイオード、ＩＮＶ１１、ＩＮＶ１２はインバータ、Ｒ１１～Ｒ１４は抵抗である。１１、１２は電流制限回路、１３はラッチ回路である。 <First conventional example>
FIG. 3 shows a level conversion circuit of the first conventional example (see, for example, Patent Document 1). This level conversion circuit converts low level (GND) and high level (VDD3) voltages input to the input terminal IN into low level (VL2) and high level (VDD1) voltages to the output terminal OUT and outputs the voltages. is.

is. The voltage is

in a relationship. MP11 to MP15 are PMOS transistors, MN11 to MN18 are NMOS transistors, and DMN1 and DMN2 are high voltage NMOS transistors. ZD1 and ZD2 are Zener diodes, INV11 and INV12 are inverters, and R11 to R14 are resistors. 11 and 12 are current limiting circuits, and 13 is a latch circuit.

First, when the input signal of the input terminal IN transitions from low level (GND) to high level (VDD3), the following operations are performed. The transistor MN11 is turned on, and the maximum current determined by the source voltage of the transistor DMN1 and the resistor R11 flows through the resistor R11. However, the drain current of the transistor MN11 is limited to the constant current by turning on the transistor MN12 immediately after.

The current of transistor DMN11 flows through Zener diode ZD1 and resistor R12, and the voltage of the anode (node N11) of Zener diode ZD1 drops from VDD1 to Zener voltage Vz1. When the voltage of the node N11 transitions from VDD1 to "VDD1-Vz1", the transistor MN17 connected to the node N11 is turned off and the transistor MP14 is turned on, so the voltage of the node N13 becomes VDD1 and the transistor MN16 is turned on. On the other hand, since the transistor MN18 is turned on and the transistor MP15 is turned off, the voltage of the node N14 becomes low level (VL2) and the transistor MN15 is turned off. Since the node N14 thus transitions from high level (VDD1) to low level (VL2), the voltage of the output terminal OUT transitions from low level (VL2) to high level (VDD1) via the inverter INV11. .

When the input signal of the input terminal IN transitions from high level (VDD3) to low level (GND), the following operations are performed. At this time, the transistor MN11 is turned off and the transistor MN13 is turned on, so the current limiting circuit 11 stops operating, the current limiting circuit 12 operates, and the latch circuit 13 is inverted, so that the voltage of the output terminal OUT is It transitions from high level (VDD1) to low level (VL2).

In the level conversion circuit of FIG. 3, the maximum drain current flows through the transistor DMN1 when the voltage of the node N11 drops from VDD1 to "VDD1-Vz". to a low level (VL2), thereby shortening the transition time of the voltage of the output terminal OUT from the low level (VL2) to the high level (VDD1). In addition, when the voltage of the node N12 drops from VDD1 to "VDD1-Vz", the maximum drain current flows through the transistor DMN2, so that the gate voltage of the transistor MP15 changes from high level (VDD1) to low level (VL2) in a short time. This shortens the transition time of the voltage of the output terminal OUT from the high level (VDD1) to the low level (VL2).

However, in the level conversion circuit of FIG. 3, the current limiting circuits 11 and 12 prevent large currents from continuing to flow through the Zener diodes ZD1 and ZD2, thereby preventing destruction of the Zener diodes ZD1 and ZD2. However, the transistors MN11 and MN13 cannot pass a drain current exceeding a certain value, and there is a limit to shortening the transition time at the time of level transition.

<Second conventional example>
FIG. 4 shows a level conversion circuit of the second conventional example. This level conversion circuit is an improvement over the first conventional example to further shorten the transition time of level transition. MP21 to MP30 are PMOS transistors, MN21 to MN28 are NMOS transistors, R21 to R24 are resistors, and 21 is a latch circuit.

First, when the input signal of the input terminal IN transitions from low level (GND) to high level (VDD3), the transistor MN24 is turned on and the transistor MN26 is turned off. Since the node N21 becomes low level (VL2+VGSMP28), the transistors MP22, MP24, MP25 and MP27 are turned on, and the output terminal OUT becomes high level (VDD1). VGSMP28 is the gate-to-source voltage of transistor MP28. At this time, the transistor MP24 is turned on and the transistor MN22 is turned off, so that the node N22 becomes high level (VDD1), so the transistor MN21 is turned on and the transistors MP21 and MP23 are turned off. Also, the transistor MP26 is turned off.

When the input signal of the input terminal IN transitions from high level (VDD3) to low level (GND), the transistor MN24 is turned off and the transistor MN26 is turned on, so that the node N21 becomes high level (VDD1) and the node N22 becomes low level. Since it becomes (VL2+VGSMP29), the operation is reversed to the above, and the output terminal OUT becomes low level (VL2). VGSMP29 is the gate-to-source voltage of transistor MP29.

Since the level conversion circuit of FIG. 4 does not use a Zener diode, it is not necessary to limit the current to protect it. can do. Moreover, since the low level of the node N21 is clamped to the voltage "VL2+VGSMP28" and the low level of the node N22 is clamped to the voltage "VL2+VGSMP29", it is possible to prevent the transistors connected to the nodes N21 and N22 from being destroyed. .

Japanese Patent No. 5881432

にする必要があり、低電圧化が困難であった。なお、ＶＧＳＭＰ２２はトランジスタＭＰ２２のゲート・ソース間電圧、ＶＤＳＭＰ２１はトランジスタＭＰ２１のドレイン・ソース間電圧である。 However, the level conversion circuit described with reference to FIG. 4 converts the voltage VDD2 into

It was difficult to reduce the voltage. VGSMP22 is the voltage between the gate and source of the transistor MP22, and VDSMP21 is the voltage between the drain and source of the transistor MP21.

Also, the voltage of the node N21 is "VL2+VGSMP28" and the voltage of the node N22 is "VL2+VGSMP29", so if the voltage VL2, that is, VDD2 fluctuates, the voltages of the nodes N21 and N22 may also fluctuate, causing a malfunction.

On the other hand, the output stage of the switching power supply circuit uses an NMOS transistor MN31 on the high side and an NMOS transistor MN32 on the low side as a switching transformer, as shown in FIG. , the low-side transistor MN32 is driven by the low-side drive circuit 32. FIG. L31 is a reactor, and C31 is a smoothing capacitor. VH is a high side drive signal, VL is a low side drive signal, VIN is an input voltage, and VOUT is an output voltage. Thus, NMOS transistors are used not only on the low side of the output stage but also on the high side from the viewpoint of low on-resistance and low cost.

In this case, when turning on the high-side transistor MN31, it is necessary to make the gate voltage of the transistor MN31 higher than the drain voltage (input voltage VIN) in order to turn it on completely. A bootstrap circuit is provided by a capacitor C32 for storing the input voltage VIN.

のように、ハイサイド駆動回路３１の電源電圧ＶＤＤＨを内部電圧ＶＤＤ１よりも高くすることでき、トランジスタＭＮ３１を完全にオン状態に制御することができる。ＶＦＤ３１はダイオードＤ３１の順方向電圧である。 Assuming that the power supply voltage of the high-side drive circuit 31 is VDDH, this bootstrap circuit

, the power supply voltage VDDH of the high-side drive circuit 31 can be made higher than the internal voltage VDD1, and the transistor MN31 can be controlled to be completely on. VFD31 is the forward voltage of diode D31.

However, when the high-side drive circuit 31 is configured with the level conversion circuit described with reference to FIG. 4, VL2, which is also the voltage at the common connection point of the transistors MN31 and MN32, fluctuates greatly in synchronization with the switching operation. 4, the operating voltage VDD2 becomes insufficient, the voltages of the nodes N21 and N22 drop, and the level conversion operation may malfunction.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a level conversion circuit capable of reducing the operating voltage and preventing malfunction in the latch operation.

In order to achieve the above object, the invention according to claim 1 has an output terminal for outputting a voltage having an amplitude of a first high voltage and a first low voltage, and an amplitude of a second high voltage and a second low voltage. an input terminal to which a voltage is applied, a source connected to a line of said second low voltage, a drain connected to a first node, said input terminal being connected to said second low voltage when said output terminal is at said first low voltage; an NMOS fifth transistor that is turned on when transitioning from a voltage to the second high voltage and turned off after the input terminal transitions to the second high voltage; a source connected to the line of the second low voltage; is connected to a second node, and is turned on when the input terminal transitions from the second high voltage to the second low voltage when the output terminal is at the first high voltage, and the input terminal is at the second low voltage. and a PMOS fifth transistor having a source connected to the first high voltage line, a drain connected to the third node, and a gate connected to the second node. a transistor, a PMOS sixth transistor having a source connected to said first high voltage line, a drain connected to a fourth node, and a gate connected to said first node; and said first high voltage line. A first inverter having the first low voltage line as a power source and the fourth node as the input side and the third node as the output side, and the first high voltage line and the first low voltage line as power sources. A latch circuit including a second inverter connected in inverse parallel with the first inverter so that the third node is the input side and the fourth node is the output side, and the voltage of the fourth node is output to the output terminal. a series circuit of a first NMOS transistor and a first resistor, which are connected between the second node and the first low voltage line and turn on when the output terminal is at the first low voltage; a series circuit of a second NMOS transistor and a second resistor, which are connected between the 1 node and the line of the first low voltage and which are turned on when the output terminal is at the first high voltage; a first PMOS transistor having a source connected to a line and having a gate and drain connected to said first node; a source connected to said first high voltage line, a gate connected to said first node and a drain; connected to the second node; and a fourth PMOS transistor having a source connected to the first high voltage line and a gate and a drain connected to the second node. and a PMOS third transistor having a source connected to the first high voltage line, a gate connected to the second node, and a drain connected to the first node; is composed of a PMOS eighth transistor and an NMOS fourth transistor, and the second inverter is composed of a PMOS seventh transistor and an NMOS third transistor.
The invention according to claim 2 is the level conversion circuit according to claim 1 , wherein the fifth NMOS transistor is turned off when the output terminal is at the first low voltage and the input terminal is at the second low voltage. is turned on when the output terminal is at the first low voltage and the input terminal is at the second high voltage, and turned off when the output terminal is at the first high voltage and the input terminal is at the second low voltage. and is turned off when the output terminal is at the first high voltage and the input terminal is at the second high voltage, and the NMOS sixth transistor has the output terminal at the first low voltage and the input terminal is at the second high voltage. off when the output terminal is at the first low voltage and the input terminal is at the second high voltage; and when the output terminal is at the first high voltage and the input terminal is at the first high voltage. It is turned on when the second low voltage, and turned off when the output terminal is at the first high voltage and the input terminal is at the second high voltage.

According to the first aspect of the invention, the first high voltage line and the first low voltage line are used as power sources, and the latch circuit in which the first inverter and the second inverter are connected in reverse parallel is used. and the first low voltage can be reduced to the sum of the gate-source voltages of the PMOS transistors and the gate-source voltages of the NMOS transistors of the inverters, thereby realizing a low voltage. Also, even if the first low voltage fluctuates somewhat, the voltages of the third and fourth nodes do not fluctuate, so NMOS transistors are used for the high-side and low-side transistors of the output stage, and a bootstrap circuit is provided. Even if it is applied to a high-side drive circuit of a switching power supply circuit, it is possible to prevent malfunctions from occurring.

According to the first aspect of the invention, the first NMOS transistor prevents the second node from floating, and the second NMOS transistor prevents the first node from floating, thereby reducing noise. You can avoid the impact.

According to the first aspect of the invention, the first node can be clamped to a voltage lower than the first high voltage by the voltage between the gate and source of the first PMOS transistor, and the second node can be clamped to a voltage lower than the first high voltage. The voltage between the gate and source of the fourth PMOS transistor can be clamped to a lower voltage, and the first to sixth PMOS transistors can be prevented from being destroyed at a high voltage.

Furthermore, according to the second aspect of the invention, the NMOS fifth and sixth transistors can be turned on only when the transition operation is required.

1 is a circuit diagram of a level conversion circuit according to an embodiment of the present invention; FIG. 2 is an operation waveform diagram of the level conversion circuit of FIG. 1; FIG. 1 is a circuit diagram of a level conversion circuit of a first conventional example; FIG. FIG. 10 is a circuit diagram of a level conversion circuit of a second conventional example; 4 is a circuit diagram of an output section of the switching power supply circuit; FIG.

FIG. 1 shows an embodiment of the level conversion circuit of the present invention. This level conversion circuit converts low level (GND) and high level (VDD3) voltages input to the input terminal IN into low level (VL2) and high level (VDD1) voltages and outputs them to the output terminal OUT. be. VL2, VDD1, and VDD2 have the relationship shown by the above formula (1), and the voltages VDD1, VDD3, and GND have the relationship shown by the above formula (2). For example, VDD1=30V, VDD2=5V, VDD3=3V, GND=0V. In this embodiment, VDD1 is the first high voltage, VL2 is the first low voltage, VDD3 is the second high voltage, and GND is the second low voltage.

In FIG. 1, MP1 to MP9 are PMOS transistors, MN1 to MN8 are NMOS transistors, AND1 and AND2 are AND gates, INV1 to INV7 are inverters, R1 to R7 are resistors, and 1 is a latch circuit. Hereinafter, the upper circuit to which the voltages VDD1 and VL2 are applied in FIG.

In the high-side circuit 2, transistors MP1, MP2, and MP6 form a current mirror circuit, which is controlled by the voltage of node N1 and on/off of transistor MN2. Transistors MP3, MP4 and MP5 also form a current mirror circuit and are controlled by the voltage of node N2 and the on/off of transistor MN1. A resistor R1 is connected to the drain of the transistor MN1 to limit the gate current of the transistor MP3 when turned on. A resistor R2 is connected to the drain of the transistor MN2 to limit the gate current of the transistor MP2 when turned on.

The latch circuit 1 is configured by connecting an inverter INV1 made up of transistors MP8 and MN4 and an inverter INV2 made up of transistors MP7 and MN3 in antiparallel. Resistors R3 and R4 are for bias. The node N3, which is the common gate (input side) of the transistors MP7 and MN3, is controlled by the transistor MP5, and the node N4, which is the common gate (input side) of the transistors MP8 and MN4, is controlled by the transistor MP6.

Inverter INV3 inverts the voltage at node N4 and controls transistor MN1. The inverter INV4 inverts the output voltage of the inverter INV3 and outputs it to the output terminal OUT, and controls the transistors MN2 and MP9. The transistor MP9 controls the transistor MN8 of the low side circuit 3.

In the low-side circuit 3, the AND gate AND1 determines on/off of the transistor MN5 according to the voltage of the input terminal IN and the output voltage of the inverter INV6 to control the voltage of the node N1. The AND gate AND2 determines on/off of the transistor MN6 according to the voltage obtained by inverting the voltage of the input terminal IN by the inverter INV5 and the output voltage of the inverter INV7, thereby controlling the voltage of the node N2. The inverter INV6 sets the output voltage to a low level (GND) when the output terminal OUT is at a high level (VDD1), and sets the output voltage to a high level (VDD3) when the output terminal OUT is at a low level (VL2). The inverter INV7 inverts the output voltage of the inverter INV6.

The operation will be described below with reference to the waveform diagram of FIG. First, when the voltage of the input terminal IN is low level (GND) and stable, the output terminal OUT is also low level (VL2) and stable. Therefore, since the transistor MP9 is turned on, the transistor MN8 is turned on via the transistor MN7, the output of the inverter INV6 is at high level (VDD3), and the output of the inverter INV7 is at low level (GND). Therefore, the output of the AND gate AND1 becomes low level (GND), and the transistor MN5 is turned off. The output of the AND gate AND2 also becomes low level (GND), turning off the transistor MN6.

Also, the transistor MN1 is turned on and the transistor MN2 is turned off. Therefore, the transistors MP3, MP4 and MP5 are turned on and the transistors MP1, MP2 and MP6 are turned off. As described above, the node N1 is at a high level (VDD1) by turning on the transistor MP3. Also, the node N2 is clamped to the voltage of "VDD1-VGSMP4" by turning on the transistor MP4. VGSMP4 is the gate-to-source voltage of transistor MP4.

Since the transistor MP5 is turned on and the transistor MP6 is turned off, the node N3 becomes high level (VDD1), the transistor MP7 is turned off, the transistor MN3 is turned on, the transistor MP8 is turned on, and the transistor MN4 is turned off. ing. The state in which the node N3 is at the high level (VDD1) and the node N4 is at the low level (VL2) is held by the latch circuit 1 as described above.

Next, when the voltage of the input terminal IN transitions from low level (GND) to high level (VDD3), the output of the AND gate AND1 changes to high level (VDD3) because the output of the inverter INV6 is still high level (VDD1). changes and the transistor MN5 is turned on. Therefore, the node N1 drops from the high level (VDD1), the transistor MP1 turns on, and the voltage of the node N1 drops to "VDD1-VGSMP1". VGSMP1 is the gate-to-source voltage of transistor MP1. At this time, the transistor MP3 is turned on, but the drain current of the transistor MP4 flowing through the turned-on transistor MN1 is limited by the resistor R1. Therefore, the gate-source voltages of the transistors MP3 and MP4 are also limited, and the on-resistance of the transistor MP3 is larger than the on-resistance of the transistor MP1. The voltage will be "VDD1-VGSMP1" as described above.

Also, since the output of the AND gate AND2 does not change from the low level (GND), the transistor MN6 remains off. Therefore, when the transistor MP2 is turned on, the voltage of the node N2 rises from "VDD1-VGSMP4" to the high level (VDD1), and the transistor MP5 is turned off.

As the voltage of the node N1 drops to "VDD1-VGSMP1", the transistor MP6 turns on and raises the voltage of the node N4 to a high level (VDD1). Therefore, the latch circuit 1 is inverted and the node N3 drops to low level (VL2). At this time, the output of the inverter INV3 drops to low level (VL2) and the output of the inverter INV4 rises to high level (VDD1), turning off the transistor MN1 and turning on the transistor MN2. Also, the output terminal OUT changes to high level (VDD1).

Also, since the transistor MN8 is turned off, the output of the inverter INV6 changes to low level (GND), the output of the AND gate AND1 changes to low level (GND), and the transistor MN5 is turned off again.

As a result, the state where the node N3 is at low level (VL2) and the node N4 is at high level (VDD1) is held by the latch circuit 1, and the output terminal OUT is held at high level (VDD1).

Next, when the voltage of the input terminal IN transitions from high level (VDD3) to low level (GND) , the output of the inverter INV5 becomes high level (VDD3), and the output of the inverter INV7 is still high level (VDD1). , and the output of the AND gate AND2 changes to high level (VDD3), turning on the transistor MN6. Therefore, the node N2 drops from the high level (VDD1), the transistor MP4 turns on, and the voltage of the node N2 drops to "VDD1-VGSMP4". VGSMP4 is the gate-to-source voltage of transistor MP4. At this time, the transistor MP2 is turned on, but the drain current of the transistor MP1 flowing through the turned-on transistor MN2 is limited by the resistor R2. Therefore, the gate-source voltages of the transistors MP1 and MP2 are also limited, and the on-resistance of the transistor MP2 is larger than the on-resistance of the transistor MP4. The voltage will be "VDD1-VGSMP4" as described above.

Also, since the output of the AND gate AND1 does not change from the low level (GND), the transistor MN5 remains off. Therefore, when the transistor MP3 is turned on, the voltage of the node N1 rises from "VDD1-VGSMP1" to the high level (VDD1), and the transistor MP6 is turned off.

As the voltage of the node N2 drops to "VDD1-VGSMP4", the transistor MP5 turns on to raise the voltage of the node N3 to high level (VDD1). Therefore, the latch circuit 1 is restored and the node N4 drops to low level (VL2). At this time, the output of the inverter INV3 rises to a high level (VDD1) and the output of the inverter INV4 falls to a low level (VL2), turning on the transistor MN1 and turning off the transistor MN2. Also, the output terminal OUT changes to low level (VL2).

Also, since the transistor MN8 is turned on, the output of the inverter INV6 changes to high level (VDD3), and the output of the inverter INV7 drops to low level (GND), so the output of the AND gate AND2 changes to low level (GND). , transistor MN6 is turned off again.

As a result, the latch circuit 1 holds the state where the node N3 is at high level (VDD1) and the node N4 is at low level (VL2), and the output terminal OUT is held at low level (VL2).

となり、式（３）に比べて、トランジスタのドレイン・ソース間電圧であるＶＤＳＭＰ２１の電圧分だけ小さくなり、低電圧の動作が可能となる。 As described above, in the level conversion circuit of this embodiment, the required voltage VDD2 in the high-side circuit 2 is set to VGSMP8 as the voltage between the gate and source of the transistor MP8 in the latch circuit 1, and If the voltage is VGSMN4,

As compared with the expression (3), it becomes smaller by the voltage of VDSMP21, which is the voltage between the drain and the source of the transistor, and low-voltage operation becomes possible.

Even if the voltage VDD2 fluctuates and the voltage VL2 fluctuates to some extent, the voltages of the nodes N3 and N4 do not fluctuate. Even if the level conversion circuit of this embodiment is applied to , the occurrence of malfunction can be prevented.

Also, by using the series circuit of the transistor MN1 and the resistor R1, the voltage of the node N1 when turning on the transistor MP6 can be clamped to "VDD1-VSGMP1". Also, by using the series circuit of the transistor MN2 and the resistor R2, the voltage of the node N2 when turning on the transistor MP5 can be clamped to "VDD1-VSGMP4". For these reasons, it is possible to prevent an excessive voltage from being applied to the transistors MP1 to MP6.

Further, the transistor MN1 can prevent the node N1 from floating after the transistor MN5 turns off, and the transistor MN2 can prevent the node N2 from floating after the transistor MN6 turns off. It is possible to prevent the influence of disturbance.

1: latch circuit, 2: high side circuit, 3: low side circuit

Claims (2)

an output terminal for outputting a voltage having amplitudes of the first high voltage and the first low voltage;
an input terminal receiving a voltage having amplitudes of a second high voltage and a second low voltage;
a source connected to a line of said second low voltage, a drain connected to a first node, and said input terminal going from said second low voltage to said second high voltage when said output terminal is at said first low voltage. an NMOS fifth transistor that turns on when transitioning and turns off after the input terminal transitions to the second high voltage;
a source connected to a line of said second low voltage, a drain connected to a second node, and said input terminal going from said second high voltage to said second low voltage when said output terminal is at said first high voltage; a sixth NMOS transistor that turns on when transitioning and turns off after the input terminal transitions to the second low voltage;
a PMOS fifth transistor having a source connected to the first high voltage line, a drain connected to a third node, and a gate connected to the second node;
a PMOS sixth transistor having a source connected to the first high voltage line, a drain connected to a fourth node, and a gate connected to the first node;
a first inverter having the first high voltage line and the first low voltage line as power sources, the fourth node being the input side and the third node being the output side; the first high voltage line and the first inverter; 1 low-voltage line as a power supply, a second inverter connected in anti-parallel with the first inverter so that the third node is the input side and the fourth node is the output side, and the voltage of the fourth node is a latch circuit that outputs to the output terminal;
a series circuit of an NMOS first transistor and a first resistor, which are connected between the second node and the first low voltage line and turn on when the output terminal is at the first low voltage;
a series circuit of a second NMOS transistor and a second resistor, which are connected between the first node and the first low voltage line and turn on when the output terminal is at the first high voltage;
a PMOS first transistor having a source connected to the first high voltage line and having a gate and a drain connected to the first node;
a second PMOS transistor having a source connected to the first high voltage line, a gate connected to the first node, and a drain connected to the second node;
a PMOS fourth transistor having a source connected to the first high voltage line and having a gate and a drain connected to the second node;
a PMOS third transistor having a source connected to the first high voltage line, a gate connected to the second node, and a drain connected to the first node;
with
1. A level conversion circuit, wherein said first inverter comprises an eighth PMOS transistor and a fourth NMOS transistor, and said second inverter comprises a seventh PMOS transistor and a third NMOS transistor. 2. The level conversion circuit of claim 1, wherein
The fifth NMOS transistor is turned off when the output terminal is at the first low voltage and the input terminal is at the second low voltage, and the output terminal is at the first low voltage and the input terminal is at the second low voltage. 2 is on when the output terminal is at the first high voltage and the input terminal is at the second low voltage; and when the output terminal is at the first high voltage and the input terminal is at the second low voltage. 2 Turn off when high voltage,
The sixth NMOS transistor is turned off when the output terminal is at the first low voltage and the input terminal is at the second low voltage, and the output terminal is at the first low voltage and the input terminal is at the second low voltage. 2 is turned off when the output terminal is at the first high voltage and the input terminal is at the second low voltage; and when the output terminal is at the first high voltage and the input terminal is at the second low voltage. 2 turn off when high voltage,
A level conversion circuit characterized by:

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