JP5149704B2 - Switching drive circuit - Google Patents

Description

  The present invention relates to a switching drive circuit having a short-circuit protection function.

  Conventionally, a configuration shown in FIG. 7 is known as a switching drive circuit. The switching drive circuit shown in the figure includes a control logic unit 100A, a level shift unit 200A, a pre-driver unit 300A, and a power transistor unit 400. The level shift unit 200A includes a high side level shift circuit 211 and a low side level shift circuit 212. The pre-driver unit 300A includes a high-side pre-driver 321 and a low-side pre-driver 322. The power transistor unit 400 includes a high side NMOS power transistor 401 and a low side NMOS power transistor 402.

  The power source of the inverter 111 of the control logic unit 100A is the VSS reference logic level voltage VDD. The power source of the high-side pre-driver 321 of the pre-driver unit 300A is a voltage VGH based on VOUT (the voltage at the OUT terminal). The power source of the low-side pre-driver 322 is a VSS reference voltage VGL. The power source of the power transistor unit 400 is the VSS reference voltage VDDO. For example, VDD is 5V based on VSS, VGH is 10V based on VOUT, VGL is 10V based on VSS, VDDO is 12V based on VSS, and VOUT is VSS or VDD.

  FIG. 8 shows an example of operation waveforms of the switching drive circuit of FIG. The signal voltage (high level is VDD, low level is VSS) input from the IN terminal is level-shifted by the high-side level shift circuit 211, and the driving force is increased by the high-side predriver 321 (the output impedance is reduced). Applied to the gate of the high-side NMOS power transistor 401. On the other hand, the signal voltage input from the IN terminal is inverted by the inverter 111, level-shifted by the low-side level shift circuit 212, the driving power is increased by the low-side pre-driver 322 (the output impedance is reduced), and the low-side NMOS Applied to the gate of the power transistor 402. When the high side NMOS power transistor 401 is driven, the output impedance of the high side pre-driver 321 is set sufficiently low. When the low side NMOS power transistor 402 is driven, the output impedance of the low side pre-driver 322 is set sufficiently low.

  Next, a switching drive circuit including the short circuit detection circuit 500A is shown in FIG. The control logic unit 100B of the switching drive circuit shown in the figure includes an inverter 121, an AND circuit 122, and a NOR circuit 123. The level shift unit 200A, the pre-driver unit 300A, and the power transistor unit 400 are the same as those in FIG. The short-circuit detection circuit 500A includes a high-side switch 501 that is turned on synchronously when the high-side NMOS power transistor 401 is turned on, a low-side switch 502 that is turned on synchronously when the low-side NMOS power transistor 402 is turned on, and a high-side reference voltage source 503. , Low side reference voltage source 504, high side comparator 505, low side comparator 506, high side level shift circuit 507, low side level shift circuit 508, OR circuit 509, D flip-flop 510, pull-up resistor R3, pull-down resistor R4. .

  Regarding the power supply of the short-circuit detection circuit 500A, the power supply of the high-side comparator 505 and the low-side comparator 506 is the VSS reference voltage VDDO, the high-side level shift circuit 507, the low-side level shift circuit 508, the OR circuit 509, and the D flip-flop 510. This is the VSS reference voltage VDD.

  Here, when a short circuit occurs between the OUT terminal and VSS, and a short circuit current flows through the high-side NMOS power transistor 401 that is turned on at this time, a short circuit voltage is generated between the VDDO-OUT terminals. Thus, when the voltage at the OUT terminal falls below the voltage VHREF of the high-side reference voltage source 503, the high-side comparator 505 has the inverting input terminal lower than the voltage at the non-inverting input terminal, and the output becomes VDDO. At this time, the low-side switch 502 is in an off state, the non-inverting input terminal of the low-side comparator 506 is kept at VSS by the pull-down resistor R4, and its output is VSS. Therefore, a voltage obtained by converting VDDO to VDD by the high side level shift circuit 507 appears at the node HDCT. This VDD passes through the OR circuit 509 and reaches the CLK terminal of the D flip-flop 510. When the voltage at the CLK terminal transitions from VSS to VDD, VDD applied to the data terminal of the D flip-flop 510 is output to the OCP terminal. When the OCP terminal becomes VDD, the output of the AND circuit 122 of the control logic unit 100B becomes VSS, the node HG of the high side pre-driver 321 changes to VOUT, and the high side NMOS power transistor 401 is turned off. When the high-side NMOS power transistor 401 is turned off, the OUT terminal is in a floating state and the short-circuit current is stopped. An example of the operation waveform at this time is shown in FIG.

  Conversely, when a short circuit occurs between VDDO and the OUT terminal and a short circuit current flows through the low-side NMOS power transistor 402 that is turned on at this time, a short circuit voltage is generated between the OUT terminal and VSS. As a result, when the voltage at the OUT terminal exceeds the voltage VLREF of the low-side reference voltage source 504, the output of the low-side comparator 506 becomes VDDO. At this time, the high-side switch 501 is in an OFF state, the inverting input terminal of the high-side comparator 505 is kept at VDDO by the pull-up resistor R3, and its output is VSS. Therefore, VDDO is converted to VDD by the low side level shift circuit 508 and appears at the node LDCT. This VDD passes through the OR circuit 509 and reaches the CLK terminal of the D flip-flop 510. When the voltage at the CLK terminal transitions from VSS to VDD, VDD applied to the data terminal of the D flip-flop 510 is output to the OCP terminal. When the OCP terminal becomes VDD, the output of the NOR circuit 123 of the control logic unit 100B becomes VSS, the node LG of the low side pre-driver 322 changes to VSS, and the low side NMOS power transistor 402 is turned off. When the low-side NMOS power transistor 402 is turned off, the OUT terminal is in a floating state and the short-circuit current is stopped. An example of operation waveforms at this time is shown in FIG.

  However, the operation of the short-circuit detection circuit 500A described above is in an ideal state, and when applied to an actual circuit, the following two problems occur. That is, the short-circuit erroneous detection operation due to the voltage ringing of the OUT terminal and the destruction of the power transistors 401 and 402 caused by the overshoot when the high-side NMOS power transistor 401 and the low-side NMOS power transistor 402 are turned off.

  First, short circuit erroneous detection due to ringing of the voltage VOUT will be described with reference to operation waveform diagrams shown in FIGS. FIG. 12 shows a waveform example actually seen at the IN terminal and OUT terminal in the switching drive circuit of FIG. As shown in the figure, the voltage waveform at the OUT terminal causes ringing at the time of switching due to the influence of the inductance component parasitic on the VDDO terminal, the VSS terminal and the OUT terminal, the capacitance component of the power transistor, the on-resistance, and the like.

  Therefore, as shown in FIG. 13, when the voltage at the OUT terminal transitions from VSS to VDDO, the voltage may drop below the voltage VHREF of the high-side reference voltage source 503 during ringing. When the voltage at the OUT terminal falls below VHREF, the voltage at the node HDCT becomes VDD, and a short circuit is erroneously detected. Although not shown, conversely, when the voltage at the OUT terminal transitions from VDDO to VSS, ringing may occur and the voltage may rise above the voltage VLREF of the low-side reference voltage source 504. When the voltage at the OUT terminal rises above VLREF, the LDCT voltage becomes VDD, and a short circuit is erroneously detected.

  As a means for solving the malfunction caused by the ringing, a blanking circuit is introduced. The blanking circuit is a circuit that does not pass a signal having a pulse width less than a certain period called a blanking period. The introduction of this blanking circuit will be described with reference to FIGS.

  FIG. 14 shows an implementation example of a switching drive circuit having a short circuit detection circuit 500B to which a blanking circuit is added. A high side blanking circuit 511 is inserted between the high side comparator 507 and the OR circuit 509, and a low side blanking circuit 512 is inserted between the low side comparator 508 and the OR circuit 509.

  Next, the operation of the blanking circuit 511 will be described with reference to FIG. 15 when OUT-VSS is short-circuited. As shown in the figure, when the voltage at the OUT terminal falls below the voltage VHREF of the high-side reference voltage source 503, the voltage at the node HDCT becomes VDD. However, the OCP terminal does not immediately become VDD even when the voltage of the node HDCT becomes VDD, and the output node HBLKO of the high side blanking circuit 511 becomes VDD after the HDCT voltage is maintained at VDD for a certain time. As a result, the OCP terminal becomes VDD. The same applies to the short circuit between VDDO and OUT.

  Next, the operation of the blanking circuit will be described with reference to FIG. As shown in the figure, ringing occurs immediately after the voltage at the OUT terminal changes from VSS to VDDO or from VDDO to VSS. Due to this ringing, immediately after the voltage at the OUT terminal transitions from VSS to VDDO, the voltage at the node HDCT becomes VDD when the voltage drops below the voltage VHREF of the high-side reference voltage source 503. Further, immediately after the voltage at the OUT terminal transitions from VDDO to VSS, the voltage at the node LDCT becomes VDD when the voltage rises above the voltage VLREF of the low-side reference voltage source 503.

  However, since the pulse width of the voltages of the nodes HDCT and LDCT is shorter than the blanking period, the voltage of the output node HBLKO of the high side blanking circuit 511 and the voltage of the output node LBLKO of the low side blanking circuit 512 are maintained at VSS. Therefore, the OCP terminal does not become VDD due to ringing during normal operation, and it is possible to prevent a short circuit detection error in the short circuit detection circuit 500B. The prevention of short circuit false detection by such ringing is described in Patent Document 1.

  Next, destruction due to overshoot when the power transistors 401 and 402 are turned off will be described with reference to FIGS. 17 and 18. As shown in FIG. 17, inductance components L1, L2, and L3 are parasitically present at the power supply terminals VDDO and VSS and the output terminal OUT of the switching drive circuit. The inductance components L1, L2, and L3, the on-resistance of the high-side NMOS power transistor 401 and the low-side NMOS power transistor 402, the parasitic capacitance, and the like are factors, and after the short circuit is detected, the high-side NMOS power transistor 401 and the low-side NMOS power transistor 402 Immediately after being turned off, a large overshoot occurs in the voltage waveforms at the VDDO, VSS and OUT terminals. Due to this overshoot, the high-side NMOS power transistor 401 and the low-side NMOS power transistor 402 may be destroyed because the drain-source voltage exceeds the withstand voltage. FIG. 18 is an example of operation waveforms when the high-side NMOS power transistor 401 is destroyed when the OUT terminal and VSS are short-circuited.

  In order to solve the above problem, it is necessary to reduce the overshoot of the voltage at the OUT terminal when the high-side NMOS power transistor 401 and the low-side NMOS power transistor 402 are off.

  As a general method for reducing overshoot due to switching of the power transistor, as shown in FIG. 19, series resistors R5 and R6 are connected to the gates of the power transistors 401 and 402, and power is supplied through the resistors R5 and R6. Some drive the transistors 401 and 402.

  However, as the resistance values of the resistors R5 and R6 increase, the overshoot due to switching decreases, but the rise and fall times of the voltage waveform at the OUT terminal become longer. When the power efficiency of the switching drive circuit and the switching drive circuit are used for applications such as PWM and PDM modulation, the rise time and fall time need to be as short as possible from the viewpoint of modulation accuracy. Therefore, the gates of the high-side NMOS power transistor 401 and the low-side NMOS power transistor 402 are preferably driven with as low impedance as possible.

  Therefore, as a more effective means for solving the above problem, the gates of the high-side NMOS power transistor 401 and the low-side NMOS power transistor 402 are driven by a low-impedance predriver during normal operation, and a resistance component is detected when a short circuit is detected. There is a method of turning off the high-side NMOS power transistor 401 and the low-side NMOS power transistor 402 from another path via the line.

  There is a switching drive circuit shown in FIG. 20 as a circuit in which the first countermeasure is taken to realize this. This circuit includes a control logic unit 100, a level shift unit 200, a high-side pre-driver 300H, a low-side pre-driver 300L, a power transistor unit 400, a high-side pull-down resistor R1, and a low-side pull-down resistor R2. Note that the short circuit detection circuit 500B is omitted. The control logic unit 100 includes inverters 101 and 102, OR circuits 103 and 104, and AND circuits 105 and 106. The high side pre-driver 300H includes inverters 301 to 304, a high side PMOS transistor 305, and a high side NMOS transistor 306. The low side pre-driver 300L includes inverters 311 to 314, a low side PMOS transistor 315, and a low side NMOS transistor 316.

  In the switching drive circuit of FIG. 20, individual level shift circuits 201 and 202 for signal transmission from the control logic 100 are added to separately control the high-side PMOS transistor 305 and the high-side NMOS transistor 306. Further, in order to control the low-side PMOS transistor 315 and the low-side NMOS transistor 316 separately, individual level shift circuits 203 and 204 for signal transmission from the control logic 100 are added.

  The operation of this circuit will be described below. During normal operation, since the OCP terminal becomes VSS, the high-side PMOS transistor 305, the high-side NMOS transistor 306, the low-side PMOS transistor 315, and the low-side NMOS transistor having sufficiently lower impedance than the high-side pull-down resistor R1 and the low-side pull-down resistor R2. By 316, the high-side NMOS power transistor 401 and the low-side NMOS power transistor 402 are driven according to the signal input to the IN terminal.

  When the short circuit is detected, the OCP terminal becomes VDD, so that the MOS transistors 305, 306, 315, and 316 are all turned off. For this reason, the output impedances of the high-side predriver 300H and the low-side predriver 300L become high impedance, and the high-side NMOS power transistor 401 and the low-side NMOS power transistor 402 are gradually turned off by the high-side pull-down resistor R1 and the low-side pull-down resistor R2. become. For this reason, the overshoot immediately after the high-side NMOS power transistor 401 and the low-side NMOS power transistor 402 transition to the off state is greatly reduced.

  FIG. 21 shows operation waveforms when the switching drive circuit of FIG. 20 is short-circuited between the OUT terminal and VSS. As shown in the figure, when the OCP terminal becomes VDD, the gate node HHG of the high side PMOS transistor 305 is VGH, the gate node HLG of the high side NMOS transistor 306 is VOUT, the gate node LHG of the low side PMOS transistor 315 is VGL, and the low side. The gate node LLG of the NMOS transistor 316 becomes VSS. Then, the MOS transistors 305, 306, 315, and 316 are all turned off. As a result, the voltage of the gate node HG of the high-side NMOS power transistor 401 slowly becomes VOUT via the pull-down resistor R1. Therefore, the overshoot of the VDDO terminal and the OUT terminal can be greatly reduced.

  FIG. 22 shows a switching drive circuit with a second countermeasure. FIG. 22 shows a level shift in which the high-side pull-down resistor R1 in FIG. 20 is replaced with a series circuit of a high-side pull-down resistor R7 and a high-side pull-down NMOS transistor 701, and the voltage appearing at the OCP terminal is arranged in the level shift unit 200B. The level is shifted by the circuit 205 so as to be applied to the gate of the NMOS transistor 701, and the low-side pull-down resistor R2 is replaced with a series circuit of the low-side pull-down resistor R8 and the low-side pull-down NMOS transistor 702, and the voltage appearing at the OCP terminal Is applied to the gate of the NMOS transistor 702.

  During normal operation, since the OCP terminal is VSS, the high-side pull-down NMOS transistor 701 and the low-side pull-down NMOS transistor 702 are in an off state, and the MOS transistors 305 and 305 of the high-side pre-driver 300H according to the signal input to the IN terminal. High-side NMOS power transistor 401 and low-side NMOS power transistor 402 are driven by MOS transistors 315 and 316 of 306 and low-side pre-driver 300L.

When the short circuit is detected, the OCP terminal becomes VDD, and the MOS transistors 305 and 306 of the high-side predriver 300H and the MOS transistors 315 and 316 of the low-side predriver 300L are turned off. Further, the high side pull-down NMOS transistor 701 and the low side pull-down NMOS transistor 702 are turned on. When the MOS transistors 305, 306, 315, and 316 are turned off, the output impedances of the high-side predriver 300H and the low-side predriver 300L become high impedance, and the high-side pull-down resistor R7, the high-side pull-down NMOS transistor 701, and the low-side pull-down resistor R8 The low-side pull-down NMOS transistor 702 gradually turns off the high-side NMOS power transistor 401 and the low-side NMOS power transistor 402. Therefore, the overshoot immediately after the high-side NMOS power transistor 401 and the low-side NMOS power transistor 402 transition to the off state is greatly reduced. The operation waveform when the OUT terminal-VSS is short-circuited is the same as the operation waveform (FIG. 21) of the switching drive circuit shown in FIG. As described above, Patent Documents 2 and 3 describe that the power transistor is gradually turned off when a short circuit is detected.
JP 2002-171140 A (FIG. 13) Japanese Patent Laid-Open No. 03-183209 (FIG. 1) Japanese Patent Laid-Open No. 10-276075 (FIG. 1)

  However, in the switching drive circuits of FIGS. 20 and 22, when the OUT terminal is short-circuited to the VSS terminal, if the input signal at the IN terminal changes from VDD to VSS during the blanking period, the high-side pull-down resistor R1 (in FIG. 22). The high-side NMOS power transistor 401 is turned off by the outputs of the low-side high-side PMOS transistor 305 and the high-side NMOS transistor 306 instead of the high-side pull-down resistor R7 and the high-side pull-down NMOS transistor 701 in series). A large overshoot occurs at the terminal and the VDDO terminal. As a result, the high side NMOS power transistor 401 may be destroyed.

  Further, when the OUT terminal is short-circuited with the VDDO terminal and the input signal of the IN terminal changes from VSS to VDD during the blanking period, the low-side pull-down resistor R2 (in FIG. 22, the low-side pull-down resistor R8 and the low-side pull-down NMOS transistor 702 are connected in series). The low-side NMOS power transistor 402 is turned off by the output of the low-impedance low-side PMOS transistor 315 and the low-side NMOS transistor 316 instead of the circuit), and a large overshoot occurs at the OUT terminal and the VSS terminal. As a result, the low side NMOS power transistor 402 may be destroyed.

  An object of the present invention is to provide a switching drive circuit in which a power transistor is not destroyed even if an input signal changes during a blanking period generated by short circuit detection.

In order to achieve the above object, according to the first aspect of the present invention, there is provided a high-side power transistor and a low-side power transistor having one end commonly connected to an output terminal, and turning on the high-side power transistor according to the high / low of an input signal. A high-side pre-driver to be turned on / off, a low-side pre-driver to turn off / on the low-side power transistor according to high / low of the input signal, and a short circuit when detecting a short circuit of the high-side power transistor or the low-side power transistor A short detection circuit that outputs a first short detection signal and outputs a short detection second detection signal when the short detection first detection signal is maintained during a preset blanking period, and the short detection circuit outputs the first detection signal. When the detection signal is output, the input signal is turned on / off. A control logic unit that controls the outputs of the high-side pre-driver and the low-side pre-driver to high impedance, and the high-side power when the output of the high-side pre-driver becomes high impedance when the high-side power transistor is on. First power transistor off means for gradually turning off the transistor, and second power transistor for gradually turning off the low side power transistor when the output of the low side predriver becomes high impedance when the low side power transistor is on And an input signal holding unit that switches the input signal from a passing state to a holding state when the short-circuit detection circuit outputs the first short-circuit detection signal.
According to a second aspect of the present invention, in the switching drive circuit according to the first aspect, the input signal holding unit is a D latch connected between an input terminal of the input signal and the control logic unit. Features.
According to a third aspect of the present invention, in the switching drive circuit according to the first aspect, the input signal holding unit includes an input terminal of the input signal, an input side of the high-side predriver, and an input side of the low-side predriver. It is characterized by comprising D latches individually connected between the two.
According to a fourth aspect of the present invention, in the switching drive circuit according to any one of the first to third aspects, the high-side pre-driver is turned on / off according to the high / low of the input signal. A PMOS transistor and a first NMOS transistor that is turned off / on in response to high / low of the input signal, and wherein the low-side pre-driver is turned off / on in response to high / low of the input signal. A PMOS transistor and a second NMOS transistor that is turned on / off in response to the high / low of the input signal, wherein the high-side power transistor has a gate connected to the first PMOS transistor and the first NMOS transistor. It consists of a high-side NMOS power transistor commonly connected to the drain, and the low-side power transistor The transistor comprises a low-side NMOS power transistor having a gate commonly connected to the drains of the second PMOS transistor and the second NMOS transistor, and the first power transistor off means includes a gate of the high-side NMOS power transistor. The second power transistor off means comprises a second resistor connected between the gate and the source of the low-side NMOS power transistor.
According to a fifth aspect of the present invention, in the switching drive circuit according to the fourth aspect, the first resistor is turned on when the third resistor and the short circuit detection circuit output the second short circuit detection signal. A series circuit with a switching element or a second switching element having an internal resistance corresponding to the third resistance is replaced, and the second resistance is replaced with a fourth resistance and the short circuit detection circuit. A series circuit with a third switching element that is turned on when a signal is output or a fourth switching element having an internal resistance corresponding to the fourth resistance is replaced.

  According to the present invention, when a short circuit occurs, the input signal holding unit that inputs the short circuit first detection signal prohibits the change of the input signal from being transmitted to the power transistor. Overshoot does not occur during the period, and the high-side power transistor and the low-side power transistor are not destroyed. In addition, when the blanking period ends, these power transistors are controlled so that the pre-driver is set to high impedance by the short-circuit second detection signal, and is gradually turned off from this time by the first and second power transistor off means. Therefore, overshoot does not occur at this point, and it is not destroyed.

<First embodiment>
FIG. 1 is a circuit diagram showing a configuration of a switching drive circuit according to a first embodiment of the present invention. This switching drive circuit includes a control logic unit 100, a level shift unit 200, a high-side pre-driver 300H, a low-side pre-driver 300L, a power transistor unit 400, a high-side pull-down resistor R1, a low-side pull-down resistor R2, a short-circuit detection circuit 500, and an input The signal holding unit 600 is configured.

  The control logic unit 100, the level shift unit 200, the high-side pre-driver 300H, the low-side pre-driver 300L, the power transistor unit 400, the high-side pull-down resistor R1, and the low-side pull-down resistor R2 are the same as the switching drive circuit described in FIG. . The high-side pull-down resistor R1 is an example of “first power transistor off means” described in the claims, and the low-side pull-down resistor R2 is an example of “second power transistor off means”.

  The short-circuit detection circuit 500 includes a high-side switch 501 that is turned on synchronously when the high-side NMOS power transistor 401 is turned on, a low-side switch 502 that is turned on synchronously when the low-side NMOS power transistor 402 is turned on, and a high-side reference voltage source. 503, low side reference voltage source 504, high side comparator 505, low side comparator 506, high side level shift circuit 507, low side level shift circuit 508, OR circuit 509, D flip-flop 510, high side blanking circuit 511, low side blanking circuit 512 , A NOR circuit 513, a pull-up resistor R3, and a pull-down resistor R4.

  That is, the short circuit detection circuit 500 has a NOR circuit in which inputs are connected to the output node HDCT of the high side level shift circuit 507 and the output node LDCT of the low side level shift circuit 508, in contrast to the configuration of the short circuit detection circuit 500B described in FIG. 513 is added. The power supply of the NOR circuit 513 is at the VSS reference logic level VDD. In the present embodiment, the short detection first detection signal appears at the nodes HDCT and LDCT, and the second detection signal appears at the nodes HBLKO and LBLKO.

  The input signal holding unit 600 includes a D latch that uses a VSS-based logic level VDD as a power source, is connected between the IN terminal and the control logic unit 100, and is controlled by the output of the NOR circuit 513.

  When the IN terminal is VDD and the OUT terminal is not short-circuited, the CLK terminal of the D latch 600 is VDD and is in a signal passing state. Therefore, the high side PMOS transistor 305 is turned on, the high side NMOS transistor 306 is turned off, the low side PMOS transistor 315 is turned off, and the low side NMOS transistor 316 is turned on. As a result, the high side NMOS power transistor 401 is turned on and the low side NMOS power transistor 402 is turned off. At this time, the high-side switch 501 of the short-circuit detection circuit 500 is in an on state and the low-side switch 502 is in an off state.

  If the OUT-VSS terminal is short-circuited in this state, a short-circuit current flows through the high-side NMOS power transistor 401, thereby generating a potential difference between the drain and source of the high-side NMOS power transistor 401. This potential difference is compared with the voltage VHREF of the high-side reference voltage source 503 by the high-side comparator 505, and when the potential difference becomes larger than the voltage VHREF, the output of the high-side comparator 505 becomes VDDO. Then, the high-side level shift circuit 507 converts VDDO to VDD and outputs it to the node HDCT. When this VDD is input to the NOR circuit 513, the output of the NOR circuit 513 becomes VSS (“short-circuit first detection signal”), and the CLK terminal of the D latch 600 becomes VSS. Then, the D latch 600 holds the signal immediately before the CLK terminal is switched from VDD to VSS and fixes the output.

  As a result, even if the signal at the IN terminal changes from VDD to VSS during the blanking period, the on / off states of the transistors 305, 306, 315, and 316 do not change, so the high-side NMOS power transistor 401 is turned off. Never happen. When the blanking period elapses, the OCP terminal becomes VDD (“short-circuit second detection signal”), the outputs of the high-side pre-driver 300H and the low-side pre-driver 300L become high impedance, and the high-side pull-down resistor R1 The side NMOS transistor 401 is gradually turned off.

  An example of operation waveforms when OUT-VSS is short-circuited is shown in FIG. Thus, overshoot does not occur during the blanking period starting from the occurrence of the short circuit and at the end of the blanking period, and the high-side power transistor 401 is not destroyed.

  Next, when the IN terminal is VSS and the OUT terminal is not in a short circuit state, the CLK terminal of the D latch 600 is in a signal passing state at VDD. Therefore, the high-side PMOS transistor 305 is turned off, the high-side NMOS transistor 306 is turned on, the low-side PMOS transistor 315 is turned on, and the low-side NMOS transistor 316 is turned off. As a result, the high side NMOS power transistor 401 is turned off and the low side NMOS power transistor 402 is turned on. At this time, the high-side switch 501 of the short-circuit detection circuit 500 is off and the low-side switch 502 is on.

  If the VDDO-OUT terminal is short-circuited in this state, a short-circuit current flows through the low-side NMOS power transistor 402, thereby generating a potential difference between the drain and source of the low-side NMOS power transistor 402. This potential difference is compared with the voltage VLREF of the low-side reference voltage source 504 by the low-side comparator 506, and when the potential difference becomes larger than the voltage VLREF, the output of the low-side comparator 506 becomes VDDO. Then, the low-side level shift circuit 508 converts VDDO to VDD and outputs it to the node LDCT (“short circuit first detection signal”). When this VDD is input to the NOR circuit 513, the output of the NOR circuit 513 becomes VSS, and the CLK terminal of the D latch 600 becomes VSS. Then, the D latch 600 holds the signal immediately before the CLK terminal is switched from VDD to VSS and fixes the output.

  As a result, even if the signal at the IN terminal changes from VSS to VDD during the blanking period, the on / off states of the transistors 305, 306, 315, and 316 do not change, so the low-side NMOS power transistor 402 is turned off. There is nothing. When the blanking period elapses, the node LBLKO becomes VDD (“short-circuited second detection signal”), and the OCP terminal becomes VDD. As a result, the outputs of the high-side pre-driver 300H and the low-side pre-driver 300L become high impedance, and the low-side NMOS transistor 402 is gradually turned off by the low-side pull-down resistor R2.

  FIG. 3 shows an example of operation waveforms when VDDO-OUT is short-circuited. Thus, overshoot does not occur during the blanking period starting from the occurrence of the short circuit and at the end of the blanking period, and the low-side power transistor 402 is not destroyed.

<Second embodiment>
FIG. 4 is a circuit diagram showing a configuration of a switching drive circuit according to a second embodiment of the present invention. This switching drive circuit is different from the switching drive circuit of the embodiment described with reference to FIG. 1 in that an input signal holding unit 600A is inserted between the control logic unit 100 and the level shift unit 200. The input signal holding unit 600A includes a D latch 601 inserted between the output side of the OR circuit 103 and the input side of the level shift circuit 201, and between the output side of the AND circuit 105 and the input side of the level shift circuit 202. The inserted D latch 602, between the output side of the OR circuit 104 and the input side of the level shift circuit 203, and between the output side of the AND circuit 106 and the input side of the level shift circuit 204. The D latch 604 is inserted.

  When the IN terminal is VDD and the OUT terminal is not short-circuited, the CLK terminals of the D latches 601 to 604 are in the signal passing state at VDD. Therefore, similarly to the switching drive circuit of FIG. 1, the high-side NMOS power transistor 401 is turned on and the low-side NMOS power transistor 402 is turned off. At this time, the high-side switch 501 of the short-circuit detection circuit 500 is in an on state and the low-side switch 502 is in an off state.

  If the OUT-VSS terminal is short-circuited in this state, a short-circuit current flows through the high-side NMOS power transistor 401, thereby generating a potential difference between the drain and source of the high-side NMOS power transistor 401. This potential difference is compared with the voltage VHREF of the high-side reference voltage source 503 by the high-side comparator 505. If the potential difference becomes larger than the voltage VHREF, the output of the high-side comparator 505 becomes VDDO, and the high-side level shift is performed. The circuit 507 converts VDDO to VDD and outputs it to the node HDCT (“short-circuit first detection signal”). Then, the output of the NOR circuit 513 becomes VSS, the CLK terminals of the D latches 601 to 604 become VSS, and the D latches 601 to 604 hold the signal immediately before the CLK terminal is switched from VDD to VSS and fix the output.

  As a result, even if the signal at the IN terminal changes from VDD to VSS during the blanking period, the on / off states of the transistors 305, 306, 315, and 316 do not change, and the high-side NMOS power transistor 401 is turned off. Never happen. When the blanking period elapses, HBLKO becomes VDD (“short circuit second detection signal”), and the OCP terminal becomes VDD. As a result, the outputs of the high-side pre-driver 300H and the low-side pre-driver 300L become high impedance, and the high-side NMOS transistor 401 is gradually turned off by the high-side pull-down resistor R1. An example of operation waveforms when OUT-VSS is short-circuited is shown in FIG.

  Next, when the IN terminal is VSS and the OUT terminal is not in a short circuit state, the CLK terminals of the D latches 601 to 604 are in a signal passing state at VDD. Therefore, similarly to the switching drive circuit of FIG. 1, the high-side NMOS power transistor 401 is turned off and the low-side NMOS power transistor 402 is turned on. At this time, the high-side switch 501 of the short-circuit detection circuit 500 is in an off state and the low-side switch 502 is in an on state.

  If the VDDO-OUT terminal is short-circuited in this state, a short-circuit current flows through the low-side NMOS power transistor 402, thereby generating a potential difference between the drain and source of the low-side NMOS power transistor 402. This potential difference is compared with the voltage VLREF of the low-side reference voltage source 504 by the low-side comparator 506. When the potential difference becomes larger than the voltage VLREF, the output of the low-side comparator 506 becomes VDDO, and the low-side level shift circuit 508 outputs VDDO. Is converted to VDD and output to the node LDCT (“short-circuit first detection signal”). Then, the output of the NOR circuit 513 becomes VSS, the CLK terminals of the D latches 601 to 604 become VSS, and the D latches 601 to 604 hold the signal immediately before the CLK terminal is switched from VDD to VSS and fix the output.

  As a result, even if the signal at the IN terminal changes from VSS to VDD during the blanking period, the on / off states of the transistors 305, 306, 315, and 316 do not change, and the low-side NMOS power transistor 402 is turned off. There is nothing. When the blanking period elapses, the node LBLKO becomes VDD (“short-circuited second detection signal”), and the OCP terminal becomes VDD. As a result, the outputs of the high-side pre-driver 300H and the low-side pre-driver 300L become high impedance, and the low-side NMOS transistor 402 is gradually turned off by the low-side pull-down resistor R2. FIG. 6 shows an example of operation waveforms when VDDO-OUT is short-circuited.

<Other examples>
1 and 4, the high-side pull-down resistor R1 is replaced with a series circuit of the high-side pull-down resistor R7 and the high-side pull-down NMOS transistor 701 (switching element) of the switching drive circuit described in FIG. The low-side pull-down resistor R2 can be replaced with the series circuit of the low-side pull-down resistor R8 and the low-side pull-down NMOS transistor 702 (switching element) of the switching drive circuit described in FIG. The high-side pull-down NMOS transistor 701 and the low-side pull-down NMOS transistor 702 are turned on when the OCP terminal becomes VDD. Further, if the on-resistances of the high-side pull-down NMOS transistor 701 and the low-side pull-down NMOS transistor 702 are set to the same resistance values as the high-side pull-down resistor R1 and the low-side pull-down resistor R2, the high-side pull-down resistor R7 and the low-side pull-down resistor R8 are omitted. You can also Furthermore, the high-side NMOS power transistor 401 is not limited to an NMOS transistor, and can be replaced with a PMOS transistor.

1 is a circuit diagram showing a configuration of a switching drive circuit according to a first exemplary embodiment of the present invention. FIG. 2 is an operation waveform diagram of the switching drive circuit of FIG. 1. FIG. 2 is an operation waveform diagram of the switching drive circuit of FIG. 1. It is a circuit diagram which shows the structure of the switching drive circuit of the 2nd Example of this invention. FIG. 5 is an operation waveform diagram of the switching drive circuit of FIG. 4. FIG. 5 is an operation waveform diagram of the switching drive circuit of FIG. 4. It is a circuit diagram which shows the basic composition of the conventional switching drive circuit. FIG. 8 is an operation waveform diagram of the switching drive circuit of FIG. 7. It is a circuit diagram which shows the basic composition of the conventional switching drive circuit provided with the short circuit detection circuit. FIG. 10 is an operation waveform diagram of the switching drive circuit of FIG. 9. FIG. 10 is an operation waveform diagram of the switching drive circuit of FIG. 9. FIG. 10 is an operation waveform diagram for explaining the influence of ringing in the switching drive circuit of FIG. 9. FIG. 10 is an operation waveform diagram for explaining a malfunction due to ringing of the switching drive circuit of FIG. 9. It is a circuit diagram of the conventional switching drive circuit which took the countermeasure against ringing. FIG. 15 is an operation waveform diagram of the switching drive circuit of FIG. 14. FIG. 15 is an operation waveform diagram of the switching drive circuit of FIG. 14. It is a circuit diagram of the conventional switching drive circuit which has a parasitic inductance component. FIG. 18 is an operation waveform diagram of the switching drive circuit of FIG. 17. It is a circuit diagram of the conventional switching drive circuit which gave the 1st countermeasure of the power transistor destruction when a power transistor is made into an OFF state by a short circuit detection circuit. It is a circuit diagram of the conventional switching drive circuit which gave the 2nd countermeasure of the power transistor destruction when a power transistor is made into an OFF state by a short circuit detection circuit. FIG. 21 is an operation waveform diagram of the switching drive circuit of FIG. 20. FIG. 10 is a circuit diagram of another conventional switching drive circuit in which a second countermeasure against power transistor destruction due to the power transistor being turned off by the short circuit detection circuit is taken. It is an operation | movement waveform diagram of the switching drive circuit for description of a power transistor destruction by the input signal changing during a blanking period.

Explanation of symbols

100, 100A, 100B: control logic unit, 101, 102: inverter, 103, 104: OR circuit, 105, 106: AND circuit, 111: inverter, 121: inverter, 122: AND circuit, 123: NOR circuit 200, 200A , 200B: level shift unit, 201-205, 211, 212: level shift circuit 300, 300A: pre-driver unit, 300H, 321: high-side pre-driver, 300L, 322: low-side pre-driver, 301-304, 311-314 : Inverter, 305, 315: PMOS transistor, 306, 316: NMOS transistor 400: power transistor section, 401: high side NMOS power transistor, 402: low side NMOS power transistor 50 0: Short circuit detection circuit, 501: High side switch, 502: Low side switch, 503: High side reference voltage source, 504: Low side reference voltage source, 505: High side comparator, 506: Low side comparator, 507: High side level shift circuit 508: Low side level shift circuit, 509: OR circuit, 510: D flip-flop, 511: High side blanking circuit, 512: Low side blanking circuit, 513: NOR circuit 600: Input signal holding unit (D latch), 600A: Input signal holding unit, 601 to 604: D latch 701: High side pull-down NMOS transistor, 702: Low side pull-down NMOS transistor

Claims (5)

A high-side power transistor and a low-side power transistor, one end of which is commonly connected to the output terminal;
A high-side pre-driver that turns on / off the high-side power transistor in response to high / low of an input signal;
A low-side pre-driver that turns off / on the low-side power transistor according to high / low of the input signal;
When a short circuit of the high side power transistor or the low side power transistor is detected, a short circuit first detection signal is output, and when the short circuit first detection signal is maintained during a preset blanking period, a short circuit second detection signal is output. A short-circuit detection circuit that outputs
When the short-circuit detection circuit outputs the second short-circuit detection signal, a control logic unit that controls the outputs of the high-side predriver and the low-side predriver to high impedance regardless of whether the input signal is on or off;
When the output of the high-side pre-driver becomes high impedance when the high-side power transistor is on, first power transistor off means for gradually turning off the high-side power transistor, and the low-side power transistor is turned on Second power transistor off means for gradually turning off the low side power transistor when the output of the low side pre-driver becomes high impedance when
When the short circuit detection circuit outputs the first short detection signal, an input signal holding unit that switches the input signal from a passing state to a holding state;
A switching drive circuit comprising: The switching drive circuit according to claim 1,
The switching drive circuit, wherein the input signal holding unit is a D latch connected between an input terminal of the input signal and the control logic unit. The switching drive circuit according to claim 1,
The switching drive, wherein the input signal holding unit is a D latch individually connected between an input terminal of the input signal and an input side of the high-side pre-driver and an input side of the low-side pre-driver. circuit. The switching drive circuit according to any one of claims 1 to 3,
The high-side pre-driver includes a first PMOS transistor that is turned on / off in response to high / low of the input signal, and a first NMOS transistor that is turned off / on in response to high / low of the input signal. ,
The low-side pre-driver includes a second PMOS transistor that is turned on / off in response to high / low of the input signal, and a second NMOS transistor that is turned on / off in response to high / low of the input signal,
The high-side power transistor comprises a high-side NMOS power transistor having a gate commonly connected to the drains of the first PMOS transistor and the first NMOS transistor;
The low-side power transistor comprises a low-side NMOS power transistor whose gate is commonly connected to the drains of the second PMOS transistor and the second NMOS transistor;
The first power transistor off means comprises a first resistor connected between the gate and source of the high side NMOS power transistor;
The second power transistor off means comprises a second resistor connected between the gate and source of the low side NMOS power transistor;
A switching drive circuit characterized by that. The switching drive circuit according to claim 4,
The first resistor is a series circuit of a third resistor and a first switching element that is turned on when the short-circuit detection circuit outputs the short-circuit second detection signal, or an internal resistance corresponding to the third resistor. Replacing the second switching element with
The second resistor is a series circuit of a fourth resistor and a third switching element that is turned on when the short-circuit detection circuit outputs the short-circuit second detection signal, or an internal resistor corresponding to the fourth resistor. Replaced with a fourth switching element having
A switching drive circuit characterized by that.

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