CN114070297A - Level flip circuit with micro power consumption and method for reducing transient current in circuit - Google Patents
Level flip circuit with micro power consumption and method for reducing transient current in circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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Abstract
The invention discloses a micro-power-consumption level flip circuit and a method for reducing transient current in the circuit, wherein the level flip circuit comprises: the bias voltage generating module is connected with the power supply end and used for providing bias voltage according to input voltage; the output module is connected with the bias voltage generation module, receives the bias voltage and is used for generating output voltage and feedback voltage according to the bias voltage; and the current source module is connected between a power supply end and the output module or between the output module and a grounding end and is used for providing protection current to limit short-circuit current when the output module is short-circuited, wherein the level state of the output voltage is overturned when the voltage value of the input voltage changes and changes to exceed a threshold value. The invention can reduce the short-circuit current in the circuit when the voltage of the circuit is reversed, thereby realizing the micro-power operation of the circuit.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a micro-power-consumption level flip circuit and a method for reducing transient current in the circuit.
Background
Digital gates are typically included in analog circuits to implement some of the basic logic functions. For the micro-power circuit, the inherent short-circuit current of the digital gate circuit is very large when the digital gate circuit is turned over, so that the power consumption seen by a power supply end or a power supply end is very large when the digital gate circuit is switched in a working mode, namely the gate circuit is turned over, and the whole system is probably not supported.
For example, a quiescent current of a chip or a circuit is set to be 1 microampere, and during system design, a power supply provided for the chip may have a current capability of only a few microamperes, but when the chip is turned over, the power consumption of tens of microamperes or even hundreds of microamperes is consumed, so that the power supply is pulled down, and the whole chip and the system cannot normally work.
The problem is not considered in most chip design schemes, and the influence of large overturning power consumption on a system is ignored. Conventional methods for reducing power consumption of digital circuits, such as reducing voltage, reducing gate size, using smaller scale processes, etc., are not desirable for an analog based chip design.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problems, the invention provides a micro-power-consumption level flip circuit and a method for reducing transient current in the circuit, which can reduce short-circuit current in the circuit when the voltage of the circuit is flipped, and realize micro-power-consumption operation of the circuit.
The invention provides a level flip circuit with micro power consumption, which comprises: the bias voltage generating module is connected with the power supply end and used for providing bias voltage according to input voltage; the output module is connected with the bias voltage generation module, receives the bias voltage and is used for generating output voltage and feedback voltage according to the bias voltage; and the current source module is connected between a power supply end and the output module or between the output module and a grounding end and is used for providing protection current to limit short-circuit current when the output module is short-circuited, wherein the level state of the output voltage is overturned when the voltage value of the input voltage changes and changes to exceed a threshold value.
Preferably, the protection current provided by the current source module is smaller than the quiescent current of the level flip circuit with micro power consumption.
Preferably, the bias voltage generating module includes: the drain electrode of the first transistor is connected with the power supply end, and the source electrode of the first transistor is connected with the grid electrode of the first transistor through a first resistor; and a gate of the second transistor receives the input voltage, a drain of the second transistor is connected with a source of the first transistor through the first resistor, a source of the second transistor is connected with a ground terminal, wherein the bias voltage generation module provides the bias voltage at a connection position of the second transistor and the first resistor, the first transistor is a depletion type NMOS transistor, and the second transistor is an enhancement type NMOS transistor.
Preferably, the bias voltage generating module further includes: a third transistor, a drain of which is connected to the source of the second transistor, a source of which is connected to a ground terminal, and a gate of which receives the input voltage; and a drain of the fourth transistor is connected with the source of the second transistor, a source of the fourth transistor is connected with a ground terminal, and a gate of the fourth transistor receives the feedback voltage, wherein the third transistor and the fourth transistor are both enhancement type NMOS transistors.
Preferably, the output module includes: a fifth transistor and a sixth transistor connected in series between a power supply terminal and the current source module or between the current source module and a ground terminal, and gates of the fifth transistor and the sixth transistor both receiving the bias voltage; a seventh transistor and an eighth transistor, which are connected in series between a power supply terminal and the current source module or between the current source module and a ground terminal, wherein gates of the seventh transistor and the eighth transistor are connected to a connection node of the fifth transistor and the sixth transistor, wherein the output module provides the feedback voltage at the connection node of the fifth transistor and the sixth transistor, and generates an output voltage at the connection node of the seventh transistor and the eighth transistor, the fifth transistor and the seventh transistor are both enhancement type PMOS transistors, and the sixth transistor and the eighth transistor are both enhancement type NMOS transistors.
Preferably, the current source module includes: a first current source connected between a power supply terminal and the fifth transistor or between the sixth transistor and a ground terminal; and the second current source is connected between a power supply end and the seventh transistor or between the eighth transistor and a ground end.
Preferably, the current source module includes: and the input end of the third current source is connected with the power supply end, the output end of the third current source is respectively connected with the source electrode of the fifth transistor and the source electrode of the seventh transistor, or the input end of the third current source is respectively connected with the source electrode of the sixth transistor and the source electrode of the eighth transistor, and the output end of the third current source is connected with the grounding end.
Preferably, the first current source includes: a ninth transistor and a second resistor connected in series between a power supply terminal and the fifth transistor or between the sixth transistor and a ground terminal, wherein a source of the ninth transistor is connected to a gate of the ninth transistor through the second resistor;
the second current source includes: and a tenth transistor and a third resistor connected in series between the power supply terminal and the seventh transistor or between the eighth transistor and the ground terminal, wherein a source of the tenth transistor is connected to a gate of the tenth transistor through the third resistor, and the ninth transistor and the tenth transistor are both depletion type NMOS transistors.
Preferably, the third current source includes: an eleventh transistor having a drain connected to the power supply terminal, a source connected to a gate of the eleventh transistor through a fourth resistor, and the gates of the eleventh and seventh transistors being connected to the source of the fifth and seventh transistors, respectively, or
The drain of the eleventh transistor is connected to the source of the sixth transistor and the source of the eighth transistor, respectively, the source of the eleventh transistor is connected to a ground terminal through a fourth resistor, and the gate of the eleventh transistor is connected to the ground terminal, wherein the eleventh transistor is a depletion type NMOS transistor.
According to the method for reducing the transient current in the micro power consumption circuit provided by the invention, the method for reducing the transient current in the micro power consumption circuit can be applied to the level flip circuit with micro power consumption, and the method comprises the following steps: a current source is connected in series in a branch capable of generating transient current when the micro power consumption circuit switches working modes or overturns levels, the current source provides protection current for the branch, and the transient current is larger than the static current of the micro power consumption circuit; and based on the protection current, adjusting the input voltage of the micro power consumption circuit to switch the working mode or turn over the level of the circuit, wherein the protection current is smaller than the transient current of the quiescent current of the micro power consumption circuit.
Preferably, a current source is connected in series in a branch capable of generating a transient current when the micro power consumption circuit performs a working mode switching or a level inversion, and the current source provides a protection current for the branch includes: the number of the branches is multiple, the number of the current sources connected in series in the branches is multiple, and each current source in the multiple current sources respectively and correspondingly provides protection current for one branch in the multiple branches; or the number of the branches is multiple, the number of the current sources connected in series in the branches is one, and one current source simultaneously provides protection current for each branch in the multiple branches.
Preferably, the current source includes: the transistor and the resistor are connected in series, the grid electrode of the transistor is connected with the source electrode of the transistor through the resistor, and the transistor is a depletion type NMOS transistor.
The invention has the beneficial effects that: the invention discloses a micro-power-consumption level flip circuit and a method for reducing transient current in the circuit, wherein a current source module is arranged at a part for realizing working mode switching or level flip in the circuit (namely a branch circuit generating transient large current during the working mode switching or level flip), and the short-circuit current generated during the level flip is limited through constant current output of the current source module, so that the influence of the short-circuit current on a circuit and a system power supply is reduced, and the micro-power consumption and the normal work of the circuit and the system are realized.
The depletion type NMOS transistor and the resistor are connected in series to serve as a current source, so that small current can be easily generated to serve as protection current, and the structure is simple.
In the bias voltage generation module, only one transistor (namely, a second transistor) is adopted as a switching tube for realizing voltage reversal control, and the structure is simple. And a plurality of transistors (namely, a second transistor, a third transistor, a fourth transistor and a fourth transistor) are adopted in the bias voltage generation module as switching tubes for realizing voltage inversion control, so that the threshold value of the voltage value of the input voltage in the circuit can be changed, and the application range of the level inversion circuit with micro power consumption is enlarged.
The number and the connection position of the current sources in the current source module are various, and the current source module is suitable for different application scenes.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a circuit structure of a level flip circuit with micro power consumption;
fig. 2 is a block diagram illustrating a structure of a level flip circuit for micro power consumption according to an embodiment of the present invention;
fig. 3a is a schematic circuit diagram of a level flip circuit with micro power consumption according to a first embodiment of the present invention;
fig. 3b is a schematic circuit diagram of a level flip circuit with micro power consumption according to a second embodiment of the present invention;
fig. 4 is a schematic circuit diagram illustrating a level flip circuit with micro power consumption according to a third embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a specific implementation manner of a current source in a level flip circuit with micro power consumption according to a second embodiment of the present invention;
fig. 6 is a schematic diagram illustrating a specific implementation manner of a current source in a level flip circuit with micro power consumption according to a third embodiment of the present invention;
fig. 7a is a schematic circuit diagram illustrating a level flip circuit with micro power consumption according to a fourth embodiment of the present invention;
fig. 7b is a schematic circuit diagram illustrating a level flip circuit with micro power consumption according to a fifth embodiment of the present invention;
fig. 8a is a schematic diagram illustrating a specific implementation manner of a current source in a level flip circuit with micro power consumption according to a fourth embodiment of the present invention;
fig. 8b is a schematic diagram illustrating a specific implementation manner of a current source in a level flip circuit with micro power consumption according to a fifth embodiment of the present invention;
fig. 9 is a flowchart illustrating a method for reducing transient current in a micropower circuit according to an embodiment of the present invention.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 shows a schematic circuit diagram of a level flip circuit with micro power consumption.
As shown in fig. 1, the level flip circuit of the micro power consumption includes: a first resistor R1, and first to eighth transistors (Q1-Q8). The drain of the first transistor Q1 is connected to the power supply terminal VDD, the source of the first transistor Q1 is connected to the first terminal of the first resistor R1, the gate of the first transistor Q1 is connected to the second terminal of the first resistor R1, and the first transistor Q1 and the first resistor R1 are used to provide a bias current. The drain of the second transistor Q2 is connected to the second terminal of the first resistor R1, the gate of the second transistor Q2 receives the input voltage Vin, and the first transistor Q1, the first resistor R1 and the second transistor Q2 are configured to provide a bias voltage at a connection node of the second transistor Q2 and the first resistor R1 according to the input voltage Vin, i.e., the drain of the second transistor Q2. The fifth transistor Q5 and the sixth transistor Q6 are sequentially connected in series between the power supply terminal VDD and the ground terminal GND, and the gates of the fifth transistor Q5 and the sixth transistor Q6 both receive a bias voltage, and a feedback voltage is provided at a connection node of the fifth transistor Q5 and the sixth transistor Q6 (i.e., the drain of the fifth transistor Q5 or the drain of the sixth transistor Q6). The seventh transistor Q7 and the eighth transistor Q8 are sequentially connected in series between the power supply terminal VDD and the ground terminal GND, the gates of the seventh transistor Q7 and the eighth transistor Q8 are both connected to the connection node of the fifth transistor Q5 and the sixth transistor Q6, and the connection node of the seventh transistor Q7 and the eighth transistor Q8 is used for providing the output voltage Vout. The fifth transistor Q5 and the seventh transistor Q7 are PMOS transistors, the sixth transistor Q6 and the eighth transistor Q8 are NMOS transistors, and the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8 are configured to realize the inversion of the level state of the output voltage Vout based on the change of the voltage value of the input voltage Vin, and further realize the transition of the change of the analog voltage to the inversion of the digital logic level state.
The third transistor Q3 and the fourth transistor Q4 are connected in parallel between the source of the second transistor Q2 and ground. Specifically, the drain of the third transistor Q3 is connected to the source of the second transistor Q2, the source of the third transistor Q3 is grounded, and the gate of the third transistor Q3 receives the input voltage Vin. The drain of the fourth transistor Q4 is connected to the source of the second transistor Q2, the source of the fourth transistor Q4 is connected to ground, and the gate of the fourth transistor Q4 receives the feedback voltage. The third transistor Q3 and the fourth transistor Q4 have different turn-on threshold voltages and different output impedances, so as to change the threshold value of the input voltage Vin, and increase the application range of the level flip circuit with micro power consumption.
Further, in the operation process of the level flip circuit with micro power consumption, for example, the sixth transistor Q5 and the seventh transistor Q6, or the third transistor Q7 and the fourth transistor Q8 are turned on at the same time in a certain short time, at this time, the current (i.e., short-circuit current) flowing through the sixth transistor Q5 and the seventh transistor Q6, or the third transistor Q7 and the fourth transistor Q8 is very large, so that power consumption of tens of microampere current or even hundreds of microampere current is caused, and the power supply of the circuit is pulled down, so that the whole chip and the system cannot operate normally.
Based on this, the embodiment of the present invention proposes the following modifications.
Fig. 2 is a block diagram illustrating a structure of a level flip circuit with micro power consumption according to an embodiment of the present invention, fig. 3a is a schematic diagram illustrating a circuit structure of the level flip circuit with micro power consumption according to a first embodiment of the present invention, fig. 3b is a schematic diagram illustrating a circuit structure of the level flip circuit with micro power consumption according to a second embodiment of the present invention, fig. 4 is a schematic diagram illustrating a circuit structure of the level flip circuit with micro power consumption according to a third embodiment of the present invention, fig. 7a is a schematic diagram illustrating a circuit structure of the level flip circuit with micro power consumption according to a fourth embodiment of the present invention, and fig. 7b is a schematic diagram illustrating a circuit structure of the level flip circuit with micro power consumption according to a fifth embodiment of the present invention.
As shown in fig. 2, in this embodiment, the level flip circuit with micro power consumption includes: the bias voltage generating module 100, the output module 200 and the current source module 300. On the basis of the circuit structure shown in fig. 1, the current source module 300 is added in the circuit, and the protection current provided by the current source module 300 is used for restraining or reducing the large short-circuit current when the voltage of the circuit is reversed, so that the micro-power consumption operation of the circuit is realized.
Specifically, the bias voltage generating module 100 is connected to the power supply terminal for providing a bias voltage according to the input voltage Vin. Here, the bias voltage is opposite to the level state (high level state or low level state) of the input voltage Vin.
The output module 200 is connected to the bias voltage generating module 100, and receives the bias voltage, and is used for generating an output voltage Vout and a feedback voltage according to the bias voltage.
In this embodiment, the output module 200 mainly realizes that the level state of the output voltage Vout is inverted when the voltage value of the input voltage Vin changes and changes to exceed a threshold (including changing to be less than the threshold and changing to be greater than the threshold).
Further, the output module 200 generates a feedback voltage while realizing stable output of the inverted voltage of the input voltage Vin. In this embodiment, the adjustment of the switching threshold of the input voltage Vin can be realized based on the feedback voltage.
The current source module 300 is connected to the output module 200 and is used for providing a protection current to limit a short-circuit current when the output module 200 is short-circuited.
As shown in fig. 3a, in the first embodiment of the present invention, the current source module 300 is connected between the power supply terminal and the output module 200. As shown in fig. 4, in the third embodiment of the present invention, the current source module 300 is connected between the output module 200 and the ground terminal.
In the embodiment of the present invention, the protection current provided by the current source module 300 is smaller than the quiescent current of the circuit. Therefore, when the output module 200 of the circuit is in a short-circuit state due to the level inversion, the current in the corresponding branch of the circuit will not exceed the protection current due to the current source module 300, so as to limit the short-circuit current and achieve the real micro-power consumption of the whole circuit.
It is understood that the level flip circuit with micro power consumption provided by the present invention can be applied to any circuit that has excessive current (e.g. larger than the self-quiescent current of the chip or circuit) during actual operation, but is not supported by the power supply provided by the chip. The application range of the level flip circuit with micro power consumption in the embodiment can be enlarged, and the application scene is enlarged.
Specifically, in the first embodiment of the present invention, as shown in fig. 3a, the bias voltage generating module 100 includes: a first transistor Q1, a first resistor R1, and a second transistor Q2. The drain of the first transistor Q1 is connected to the power supply terminal VDD, the source of the first transistor Q1 is connected to the first terminal of the first resistor R1, the gate of the first transistor Q1 is connected to the second terminal of the first resistor R1, and the first transistor Q1 and the first resistor R1 are used to provide a bias current. The drain of the second transistor Q2 is connected to the second end of the first resistor R1, the gate of the second transistor Q2 receives the input voltage Vin, and the source of the second transistor Q2 is connected to the ground GND. The first transistor Q1, the first resistor R1 and the second transistor Q2 are configured to provide a bias voltage at a connection node of the second transistor Q2 and the first resistor R1, i.e., at the drain of the second transistor Q2, according to the input voltage Vin.
The first transistor Q1 is a depletion NMOS transistor, and the second transistor Q2 is an enhancement NMOS transistor. The depletion type NMOS transistor series resistor mode can easily generate small current, and the current is used as a current source to provide protection current, so that the structure is simple.
Further, in this embodiment, the depletion-type first transistor Q1 and the first resistor R1 are connected in series to provide a small bias current, which can also be used as a protection current for the branch when the second transistor Q2 switches on and off, thereby limiting the short-circuit current.
Furthermore, in the circuit structure disclosed by the invention, a connection structure such as a depletion type first transistor Q1 and a first resistor R1 is arranged in any branch circuit with voltage reversal, so that the transient large current in all micro-power consumption circuits is reduced, and the real micro-power consumption of the whole circuit is realized. Meanwhile, in any circuit with voltage reversal, the same or similar structure can be arranged in a circuit branch for voltage reversal to inhibit short-circuit current, so that the power consumption of the circuit is reduced.
As shown in fig. 3b, in the second embodiment of the present invention, the bias voltage generating module 100 further includes: a third transistor Q3 and a fourth transistor Q4. The third transistor Q3 and the fourth transistor Q4 are connected in parallel between the source of the second transistor Q2 and ground. Specifically, the drain of the third transistor Q3 is connected to the source of the second transistor Q2, the source of the third transistor Q3 is grounded, and the gate of the third transistor Q3 receives the input voltage Vin. The drain of the fourth transistor Q4 is connected to the source of the second transistor Q2, the source of the fourth transistor Q4 is connected to ground, and the gate of the fourth transistor Q4 receives the feedback voltage. However, although the third transistor Q3 and the fourth transistor Q4 are enhancement-type NMOS transistors, the third transistor Q3 and the fourth transistor Q4 have different on-threshold voltages (specifically, the on-threshold of the third transistor Q3 is greater than the on-threshold of the fourth transistor Q4) and different output impedances (specifically, the output impedance of the third transistor Q3 is greater than the output impedance of the fourth transistor Q4), so that the connection structure between the source of the second transistor Q2 and the ground terminal in the bias voltage generation module 100 based on the third transistor Q3 and the fourth transistor Q4 can change the threshold value of the change of the voltage value of the input voltage Vin and increase the application range of the level flip-flop circuit of the micro power consumption.
The output module 200 includes: a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8. The fifth transistor Q5 and the sixth transistor Q6 are sequentially connected in series between the power supply terminal VDD and the ground terminal GND, the gates of the fifth transistor Q5 and the sixth transistor Q6 receive a bias voltage, and a feedback voltage is generated at a connection node of the fifth transistor Q5 and the sixth transistor Q6 (i.e., the drain of the fifth transistor Q5 or the drain of the sixth transistor Q6). The seventh transistor Q7 and the eighth transistor Q8 are sequentially connected in series between the power supply terminal VDD and the ground terminal GND, and the gates of the seventh transistor Q7 and the eighth transistor Q8 are both connected to the connection node of the fifth transistor Q5 and the sixth transistor Q6, and the connection node of the seventh transistor Q7 and the eighth transistor Q8 is used to generate the output voltage Vout.
Further, the fifth transistor Q5 and the seventh transistor Q7 are enhancement type PMOS transistors, and the sixth transistor Q6 and the eighth transistor Q8 are enhancement type NMOS transistors. The fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7 and the eighth transistor Q8 are used for realizing the inversion of the level state of the output voltage Vout based on the change of the voltage value of the input voltage Vin, thereby realizing the transition from the change of the analog voltage to the inversion of the digital logic level state.
The current source module 300 includes a first current source I1 and a second current source I2. In the first and second embodiments of the present invention, as shown in fig. 3a and 3b, the first current source I1 is connected between the power supply terminal VDD and the fifth transistor Q5. The second current source I2 is connected between the supply terminal VDD and the seventh transistor Q7. Referring to fig. 5, fig. 5 is a schematic diagram illustrating a specific implementation manner of a current source in a level flip circuit with micro power consumption according to a second embodiment of the present invention, and repeated portions in fig. 5 and fig. 3b are not repeated here.
As shown in fig. 5, the first current source I1 includes a ninth transistor Q9 and a second resistor R2. The ninth transistor Q9 and the second resistor R2 are connected in series between the power supply terminal VDD and the fifth transistor Q5, and the source of the ninth transistor Q9 is connected to the gate of the ninth transistor Q9 through the second resistor R2. The second current source I2 includes a tenth transistor Q10 and a third resistor R3. The tenth transistor Q10 and the third resistor R3 are connected in series between the power supply terminal VDD and the seventh transistor Q7, and the source of the tenth transistor Q10 is connected to the gate of the tenth transistor Q10 through the third resistor R3.
As shown in fig. 4, which is a circuit diagram of a third embodiment of the present invention, the third embodiment of the present invention is a scheme conversion performed based on the second embodiment, and repeated parts in the second embodiment are not described herein again. The difference is that the first current source I1 is connected between the sixth transistor Q6 and the ground GND. The second current source I2 is connected between the eighth transistor Q8 and the ground GND. Referring to fig. 6, fig. 6 is a schematic diagram illustrating a specific implementation manner of a current source in a level flip circuit with micro power consumption according to a third embodiment of the present invention, and repeated portions in fig. 6 and fig. 3b are not repeated here.
As shown in fig. 6, the first current source I1 includes a ninth transistor Q9 and a second resistor R2. The ninth transistor Q9 and the second resistor R2 are connected in series between the sixth transistor Q6 and the ground GND, the drain of the ninth transistor Q9 is connected to the source of the sixth transistor Q6, and the source of the ninth transistor Q9 is connected to the ground GND through the second resistor R2. The second current source I2 includes a tenth transistor Q10 and a third resistor R3. The tenth transistor Q10 and the third resistor R3 are connected in series between the eighth transistor Q8 and the ground GND, the drain of the tenth transistor Q10 is connected to the source of the seventh transistor Q8, and the source of the tenth transistor Q10 is connected to the ground GND through the third resistor R3.
As shown in fig. 7a, which is a circuit diagram of a fourth embodiment of the present invention, the fourth embodiment of the present invention is a scheme conversion performed based on the second embodiment, and repeated parts in the second embodiment are not described herein again. The difference is that the current source module 300 includes only one current source, i.e. the third current source I3. The input terminal of the third current source I3 is connected to the supply terminal VDD, and the output terminal of the third current source I3 is connected to the source of the fifth transistor Q5 and the source of the seventh transistor Q7, respectively.
As shown in fig. 7b, which is a circuit diagram of a fifth embodiment of the present invention, the fifth embodiment of the present invention is a scheme conversion performed based on the fourth embodiment, and repeated parts in the fourth embodiment are not described herein again. The difference is that the current source module 300 includes only one current source, i.e. the third current source I3. The input terminal of the third current source I3 is connected to the source of the sixth transistor Q6 and the source of the eighth transistor Q8, respectively, and the output terminal of the third current source I3 is connected to the ground GND. So can reduce the components and parts quantity of circuit, optimize circuit structure, reduce the cost.
Further, referring to fig. 8a, fig. 8a shows a schematic diagram of a specific implementation manner of a current source in a level flip circuit with micro power consumption according to a fourth embodiment of the present invention, and repeated portions in fig. 8a and fig. 3b are not repeated here. As shown in fig. 8a, the third current source I3 includes: an eleventh transistor Q11 and a fourth resistor R4. When the current source module 300 is connected between the power supply terminal VDD and the output module 200, the drain of the eleventh transistor Q11 is connected to the power supply terminal VDD, the source of the eleventh transistor Q11 is connected to the gate of the eleventh transistor Q11 through the fourth resistor R4, and the gate of the eleventh transistor Q11 is connected to the source of the fifth transistor Q5 and the source of the seventh transistor Q7, respectively.
Referring to fig. 8b, fig. 8b is a schematic diagram illustrating a specific implementation manner of a current source in a level flip circuit with micro power consumption according to a fourth embodiment of the present invention, and repeated portions in fig. 8b and fig. 8a are not repeated here. As shown in fig. 8b, the third current source I3 includes: an eleventh transistor Q11 and a fourth resistor R4. When the current source module 300 is connected between the output module 200 and the ground GND, the drain of the eleventh transistor Q11 is connected to the source of the sixth transistor Q6 and the source of the eighth transistor Q8, the source of the eleventh transistor Q11 is connected to the ground GND through the fourth resistor R4, and the gate of the eleventh transistor Q11 is connected to the ground GND.
Wherein, the ninth transistor, the tenth transistor Q10 and the eleventh transistor Q11 are all depletion type NMOS transistors. The ninth transistor Q9 and the second resistor R2 are connected to provide a protection current, the tenth transistor Q10 and the third resistor R3 are connected to provide a protection current, and the eleventh transistor Q11 and the fourth resistor R4 are connected to provide a protection current.
It is understood that whether the current source module 300 is configured as one current source or two current sources, that is, all branches of the circuit that are short-circuited to generate short-circuit current are configured as a common current source or each branch is configured as a separate current source, which may be determined according to the magnitude of the short-circuit current in the circuit and the requirement of the current source for the short-circuit current suppression capability, and the present invention is not limited thereto.
For example, taking the circuit shown in fig. 3b as an example, assuming that the initial voltage state of the input voltage Vin is less than the threshold (the switching threshold), at this time, the second transistor Q2 and the third transistor Q3 are in an off state, the bias voltage is at a high level, the fifth transistor Q5 is off, the sixth transistor Q6 is on, the feedback voltage is at a low level, the fourth transistor Q4 is off, the seventh transistor Q7 is on, the eighth transistor Q8 is off, and the output voltage Vout is at a high level.
When the voltage value of the input voltage Vin changes from less than the threshold value to greater than the threshold value, the second transistor Q2 and the third transistor Q3 are turned on, the bias voltage changes to a low level, the fifth transistor Q5 is turned on, the sixth transistor Q6 is turned off, the feedback voltage changes to a high level, the fourth transistor Q4 is turned on, the seventh transistor Q7 is turned off, the eighth transistor Q8 is turned on, and the output voltage Vout is inverted from a high level state to a low level state. The short-circuit current generated during the state change of the fifth transistor Q5 and the sixth transistor Q6 and the state change of the seventh transistor Q7 and the eighth transistor Q8 is limited by the constant protection current generated by the first current source I1 and the second current source I2, so that the current in the circuit when the output voltage Vout is inverted is less than the quiescent current of the circuit, and the normal operation of the whole chip and the circuit system is not affected.
Further, when the voltage value of the input voltage Vin changes from being greater than the threshold to being less than the threshold, since the turn-on threshold of the fourth transistor Q4 is less than the turn-on threshold of the third transistor Q3, the second transistor Q2 connected in series with the fourth transistor Q4 is turned off when the voltage value of the input voltage Vin decreases to a lower voltage value, and thus the level state of the output voltage Vout can be inverted. And the threshold value of the input voltage in the circuit is adjusted, and the application range of the level flip circuit with micro power consumption is enlarged.
Based on the same inventive concept, the invention also discloses a method for reducing the transient current in the micro power consumption circuit, and referring to fig. 9, fig. 9 shows a flow chart of the method for reducing the transient current in the micro power consumption circuit provided by the embodiment of the invention.
As shown in fig. 9, in this embodiment, the method for reducing the transient current in the micro power consumption circuit may be applied to the level flipping circuit of the micro power consumption shown in fig. 1 to 8b, and specifically includes executing step S1 and step S2:
in step S1, a current source is connected in series in the branch capable of generating a transient current when the micro power consumption circuit performs a switching of the operation mode or a level inversion, and the current source provides a protection current for the branch.
In this embodiment, a current source is connected in series in a branch capable of generating a transient current (the transient current is greater than a quiescent current of the micropower circuit) when the micropower circuit performs a working mode switching or a level flipping, and the current source provides a protection current for the branch includes: the number of the branches in the micro power consumption circuit is one, the number of the current sources connected in series in the branches is one, and the current sources provide protection current for the branches. Or, the number of the branches in the micro power consumption circuit is multiple, the number of the current sources connected in series in the branch is multiple, and each current source in the multiple current sources respectively provides a protection current for one branch in the multiple branches; or, the number of the branches in the micro power consumption circuit is multiple, the number of the current sources connected in series in the branch is one, and the current source simultaneously provides protection current for the multiple branches.
Preferably, the protection current provided by the current source is smaller than the transient current of the quiescent current of the micro power consumption circuit.
It should be noted that the branch circuits described herein are generic terms, and refer to a branch circuit in a micropower circuit, which generates a transient current larger than a quiescent current of the micropower circuit when performing an operation mode switching or a level flipping, and therefore it is understood that when a plurality of branch circuits are present in a circuit, the circuit structures of the plurality of branch circuits are not necessarily identical, but all of the plurality of branch circuits generate a large transient current when performing an operation mode switching or a level flipping.
In step S2, based on the protection current, the input voltage of the micro power consumption circuit is adjusted to perform the operation mode switching or level inversion of the circuit.
A current source is arranged in a branch circuit in the micro-power consumption circuit to provide a protection current smaller than the static current of the circuit, so that the transient large current in the circuit can be effectively inhibited. Under the condition that the current source provides protection current, the actual micro power consumption of the circuit can be realized by adjusting the input voltage of the micro power consumption circuit to switch the working mode or turn over the level of the circuit.
Further, the current source includes: the transistor is a depletion type NMOS transistor.
It should be noted that the method for reducing the transient current in the circuit with micro power consumption shown in this embodiment includes, but is not limited to, only applying to the level flip circuit with micro power consumption shown in fig. 1 to 8b, as long as the circuit includes a branch circuit (for example, an analog circuit that half contains the level flip circuit with micro power consumption shown in fig. 1 to 8 b) that generates a transient current larger than the quiescent current of the circuit with micro power consumption when the operation mode is switched or the level flip is performed. That is, by using the method for reducing the transient current in the micropower circuit shown in fig. 9, all transient large currents in the micropower circuit can be reduced, and thus the actual micropower of the circuit can be realized.
In summary, the part (output module) of the circuit for realizing level inversion is provided with the current source module, and the constant current output of the current source module limits the short-circuit current generated during level inversion, so that the influence of the short-circuit current on the power supply of the circuit and the system is reduced, and the micro-power consumption and normal work of the circuit and the system are realized.
It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.
Claims (12)
1. A level flip circuit of micro power consumption is characterized by comprising:
the bias voltage generating module is connected with the power supply end and used for providing bias voltage according to input voltage;
the output module is connected with the bias voltage generation module, receives the bias voltage and is used for generating output voltage and feedback voltage according to the bias voltage; and
a current source module connected between a power supply terminal and the output module or connected between the output module and a ground terminal, for providing a protection current to limit a short-circuit current when the output module is short-circuited,
wherein the level state of the output voltage is inverted when the voltage value of the input voltage changes and changes to exceed a threshold value.
2. The micro-power level flip circuit according to claim 1, wherein the protection current provided by the current source module is smaller than a quiescent current of the micro-power level flip circuit.
3. The level flip circuit with micro power consumption of claim 1, wherein the bias voltage generating module comprises:
the drain electrode of the first transistor is connected with the power supply end, and the source electrode of the first transistor is connected with the grid electrode of the first transistor through a first resistor;
a second transistor having a gate receiving the input voltage, a drain connected to the source of the first transistor through the first resistor, and a source connected to a ground terminal,
wherein the bias voltage generating module provides the bias voltage at a connection of the second transistor and the first resistor,
the first transistor is a depletion type NMOS transistor, and the second transistor is an enhancement type NMOS transistor.
4. The level flip circuit of claim 3, wherein the bias voltage generation module further comprises:
a third transistor, a drain of which is connected to the source of the second transistor, a source of which is connected to a ground terminal, and a gate of which receives the input voltage;
a fourth transistor having a drain connected to the source of the second transistor, a source connected to ground, and a gate receiving the feedback voltage,
wherein the third transistor and the fourth transistor are enhancement type NMOS transistors.
5. The level flip circuit of micro power consumption of claim 1, wherein the output module comprises:
a fifth transistor and a sixth transistor connected in series between a power supply terminal and the current source module or between the current source module and a ground terminal, and gates of the fifth transistor and the sixth transistor both receiving the bias voltage;
a seventh transistor and an eighth transistor connected in series between a power supply terminal and the current source module or between the current source module and a ground terminal, gates of the seventh transistor and the eighth transistor being connected to a connection node of the fifth transistor and the sixth transistor,
wherein the output module provides the feedback voltage at a connection node of the fifth transistor and the sixth transistor, generates an output voltage at a connection node of the seventh transistor and the eighth transistor,
the fifth transistor and the seventh transistor are both enhancement type PMOS transistors, and the sixth transistor and the eighth transistor are both enhancement type NMOS transistors.
6. The level flip circuit of micro power consumption of claim 5, wherein the current source module comprises:
a first current source connected between a power supply terminal and the fifth transistor or between the sixth transistor and a ground terminal;
and the second current source is connected between a power supply end and the seventh transistor or between the eighth transistor and a ground end.
7. The level flip circuit of micro power consumption of claim 5, wherein the current source module comprises:
and the input end of the third current source is connected with the power supply end, the output end of the third current source is respectively connected with the source electrode of the fifth transistor and the source electrode of the seventh transistor, or the input end of the third current source is respectively connected with the source electrode of the sixth transistor and the source electrode of the eighth transistor, and the output end of the third current source is connected with the grounding end.
8. The level shifter circuit with micro power consumption of claim 6, wherein the first current source comprises:
a ninth transistor and a second resistor connected in series between a power supply terminal and the fifth transistor or between the sixth transistor and a ground terminal, wherein a source of the ninth transistor is connected to a gate of the ninth transistor through the second resistor;
the second current source includes:
a tenth transistor and a third resistor connected in series between a power supply terminal and the seventh transistor or between the eighth transistor and a ground terminal, a source of the tenth transistor being connected to a gate of the tenth transistor through the third resistor,
wherein the ninth transistor and the tenth transistor are both depletion type NMOS transistors.
9. The level shifter circuit with micro power consumption of claim 7, wherein the third current source comprises:
an eleventh transistor having a drain connected to the power supply terminal, a source connected to a gate of the eleventh transistor through a fourth resistor, and the gates of the eleventh and seventh transistors being connected to the source of the fifth and seventh transistors, respectively, or
A drain of the eleventh transistor is connected to a source of the sixth transistor and a source of the eighth transistor, respectively, a source of the eleventh transistor is connected to a ground terminal through a fourth resistor, a gate of the eleventh transistor is connected to the ground terminal,
wherein the eleventh transistor is a depletion type NMOS transistor.
10. A method for reducing transient current in a micropower circuit, wherein the method for reducing transient current in a micropower circuit is applicable to the micropower level-shifting circuit of any one of claims 1 to 9, and the method comprises:
a current source is connected in series in a branch capable of generating transient current when the micro power consumption circuit switches working modes or overturns levels, the current source provides protection current for the branch, and the transient current is larger than the static current of the micro power consumption circuit;
based on the protection current, adjusting the input voltage of the micro power consumption circuit to perform the working mode switching or level inversion of the circuit,
wherein the protection current is smaller than a transient current of a quiescent current of the micro power consumption circuit.
11. The method of claim 10, wherein a current source is connected in series in a branch capable of generating transient current when the micro power consumption circuit performs switching of operation mode or level inversion, and the current source provides protection current for the branch comprises:
the number of the branches is multiple, the number of the current sources connected in series in the branches is multiple, and each current source in the multiple current sources respectively and correspondingly provides protection current for one branch in the multiple branches; or
The number of the branches is multiple, the number of the current sources connected in series in the branches is one, and one current source simultaneously provides protection current for each branch in the multiple branches.
12. A method for reducing transient current in a micropower circuit as recited in any one of claims 10 and 11, wherein said current source comprises:
a transistor and a resistor connected in series, a gate of the transistor being connected to a source of the transistor through the resistor,
wherein the transistor is a depletion type NMOS transistor.
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| CN202010776280.0A CN114070297A (en) | 2020-08-05 | 2020-08-05 | Level flip circuit with micro power consumption and method for reducing transient current in circuit |
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| CN202010776280.0A CN114070297A (en) | 2020-08-05 | 2020-08-05 | Level flip circuit with micro power consumption and method for reducing transient current in circuit |
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