JP2010045522A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of using a transistor operating at low voltage when executing level shift, and capable of easily improving an output change speed (operation speed) when the transistor carries out on/off operation with a small occupation area in a semiconductor chip. <P>SOLUTION: A level shift part 5 includes an MOS transistor N2, a resistor R2, and a resistor R1, which are connected in series to one another. A zener diode ZD1 is connected in parallel with the resistor R1. When the MOS transistor N2 is turned on from an off-state, the zener diode ZD1 clamps the output voltage LO of the level shift part 5 at a predetermined value. A zener diode ZD2 is connected in parallel between the drain and the source of the MOS transistor N2. When the MOS transistor N2 is in an off-state, the zener diode ZD2 clamps the voltage between the drain and the source of the MOS transistor N2 at a predetermined value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a level shift circuit applied to a bridge circuit such as a charge pump type DC-DC converter or a motor driver.

Conventionally, a circuit described in Patent Document 1 is known as a level conversion circuit (level shift circuit) that converts an ECL level logic signal into a logic signal of a TTL circuit.
The level shift circuit of Patent Document 1 is composed of a differential transistor. The MOS transistor to be used is required to be a transistor whose applied voltage between the drain terminal and the source terminal is a high voltage specification.
A circuit as shown in FIG. 4 is known as a level shift circuit that converts a signal level from a low voltage system to a high voltage system. The level shift circuit of FIG. 4 includes a CMOS inverter 1, a level shift unit 2, and a CMOS inverter 3.

The CMOS inverter 1 includes complementary MOS transistors P1 and N1, and operates with a power supply voltage of VDD [V] (for example, +5 V). The level shift unit 2 includes N-type MOS transistors N11 and N12 and P-type MOS transistors P11 to P14, and operates at a power supply voltage of VDDH [V] (for example, +48 V). The CMOS inverter 3 is composed of complementary MOS transistors P3 and N3, and operates with a power supply voltage of VDDH [V].
In the level shift circuit having such a configuration, the CMOS inverter 1 inverts the input signal IN. The level shift unit 2 level-shifts the VDD level output from the CMOS inverter 1 to the VDDH level. The CMOS inverter 3 inverts the output of the level shift unit 2 and outputs it as an output signal OUT.
In this level shift circuit, the VSS level is not level-shifted and is common.

Here, in the level shift circuit of FIG. 4, as the MOS transistors P1 and N1 used in the CMOS inverter 1, a transistor with a low voltage specification applied voltage between the drain terminal and the source terminal can be used. However, the MOS transistors used in the level shift unit 2 and the CMOS inverter 3 are required to have a high voltage specification applied voltage.
As described above, in the level shift circuit of Patent Document 1 or FIG. 4, a high-voltage specification transistor is required as a MOS transistor to be used, but it is desired to implement it with a low-voltage specification transistor instead. There is also.
On the other hand, the level shift circuit of FIG. 4 has a disadvantage that the area used in the semiconductor chip is increased because the transistors used in the level shift unit 2 have a high voltage specification and a total of six transistors are required. .

Therefore, the circuit shown in FIG. 5 is conceivable as a level shift circuit that satisfies the above-mentioned demand and eliminates the above-mentioned disadvantages. The level shift circuit of FIG. 5 includes a CMOS inverter 1, a level shift unit 4, and a CMOS inverter 3.
The CMOS inverter 1 includes complementary MOS transistors P1 and N1, and operates with a power supply voltage of VDD [V] (for example, +5 V). The level shift unit 4 includes a resistor R1, a resistor R2, and an N-type MOS transistor N2, which are connected in series, and operate at a power supply voltage of VDDH [V] (for example, +48 V). The CMOS inverter 3 is composed of complementary MOS transistors P3 and N3, and operates when the power supply voltage is between VSSH [V] and VDDH [V] (for example, between + 40V and + 48V).

In the level shift circuit having such a configuration, the CMOS inverter 1 inverts and outputs the input signal IN. The level shift unit 4 performs a level shift of the output of the CMOS inverter 1. The CMOS inverter 3 inverts the output of the level shift unit 4 and outputs it as an output signal OUT.
Here, if the voltage between the power supply voltages VDDH and VSSH is also a low voltage of about 5V, the MOS transistors P1 and N1 of the CMOS inverter 1 and the MOS transistors P3 and N3 of the CMOS inverter 3 are transistors of low voltage specifications. It becomes possible.
In addition, since the potential of VDDH (for example, 48V) is applied to the drain terminal when the MOS transistor N2 of the level shift unit 4 is turned off, the drain-source has a high voltage specification, but the gate-source has a low voltage. It can be used with the transistor of the specification.

Next, the operation of the level shift circuit of FIG. 5 will be described with reference to FIGS.
Now, when the MOS transistor N2 of the level shift unit 4 is switched from OFF to ON, the output voltage LO of the level shift unit 4 is as follows when the ON resistance value of the MOS transistor N2 is made smaller than the resistance value of R1. (1).
LO = VDDH− (I × R1) (1)
Here, VDDH is a power supply voltage applied to the level shift unit 4, and I is a current flowing through the resistor R1.
According to equation (1), in order to increase the change in the output voltage LO, the current I flowing through the resistor R1 may be increased to increase the value of (I × R1). For example, the current I may be increased by relatively reducing the resistance values of the resistors R1 and R2. The change in the output voltage LO in this case is as shown by a curve a in FIG.

On the other hand, in order to delay the change in the output voltage LO, the current I flowing through the resistor R1 may be decreased to reduce the value of (I × R1). For example, the current I may be reduced by relatively increasing the resistance values of the resistors R1 and R2. The change in the output voltage LO in this case is, for example, as shown by the curve b in FIG.
In these cases, when the output voltage LO changes from the power supply voltage VDDH [V] to a predetermined value corresponding to the resistance values of the resistors R1 and R2, the output voltage LO is fixed to the predetermined value. However, since the rate of change of the output voltage LO to the predetermined value and the predetermined value depend on the resistance values of the resistors R1 and R2, two of the quick switching of the output voltage LO and the reduction of the current consumption are simultaneously performed. It is difficult to satisfy.

Next, a case where the MOS transistor N2 of the level shift unit 4 is switched from on to off will be described.
In this case, the output voltage LO of the level shift unit 4 tends to rise from a predetermined value to the level of the power supply voltage VDDH. However, there is a problem in that there is a parasitic capacitance at the input terminal of the CMOS inverter 3, and it takes time to rise to the level of the power supply voltage VDDH by the charging current of this parasitic capacitance.
JP-A-5-276011

  Therefore, an object of the present invention is to use a transistor that operates at a low voltage specification when performing a level shift operation, and to improve the speed at which the level shift circuit output changes when the transistor is turned on and off. An object of the present invention is to provide a semiconductor device that can be easily realized with a small occupied area.

In order to solve the above problems and achieve the object of the present invention, each invention has the following configuration.
The first invention is a level that shifts the potential level of an input signal that changes between the first high potential and the first low potential into a signal that changes between the second high potential and the second low potential. In a semiconductor device having a level shift unit of a shift circuit, the level shift unit is connected in series between a first transistor that is turned on and off by the input signal, a drain terminal of the first transistor, and a second high potential. A first resistor, a first Zener diode having a cathode terminal connected to the drain terminal of the first transistor, an anode terminal connected to the source terminal, a cathode terminal connected to a second high potential, and an anode terminal connected to the first transistor; A second Zener diode connected to the other end of the resistor not connected to the second high potential.

According to a second invention, in the first invention, the source terminal is connected to the same second high potential as one end of the first resistor, and the gate terminal and the drain terminal are the second high potential of the first resistor. And a second transistor that is diode-connected to the other end not connected to.
According to a third invention, in the first or second invention, a second resistor is interposed between the first transistor and the first resistor.
In a fourth aspect based on the first to third aspects, the resistance value of the first resistor is set so that the output voltage of the level shift unit arbitrarily changes when the first transistor is switched from OFF to ON. The first Zener diode clamps the voltage applied to the drain terminal of the first transistor to a predetermined value when the output voltage changes arbitrarily.

According to a fifth invention, in the second to fourth inventions, when the first transistor is switched from on to off, the second transistor has a charge of parasitic capacitance at an input terminal at a rear stage of the level shift unit. It is designed to discharge.
According to the present invention having such a configuration, when performing level shift, a transistor with a low voltage specification can be used, and the output change speed (switching speed) when the transistor is turned on / off is improved. It can be easily realized with a small occupied area.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention includes a CMOS inverter 1 as an input unit, a level shift unit 5, and a CMOS inverter 3 as an output unit.
The CMOS inverter 1 inverts and outputs the input signal IN. Therefore, the CMOS inverter 1 is composed of complementary MOS transistors P1 and N1, and operates with a power supply voltage of VDD [V] (for example, +5 V).
The level shift unit 5 performs a level shift of the output of the CMOS inverter 1. Therefore, as shown in FIG. 1, the level shift unit 5 includes an N-type MOS transistor N2 that is driven on and off by the output of the CMOS inverter 1, a resistor R2, and a resistor R1, and these are connected in series. .

A Zener diode ZD1 is connected in parallel to the resistor R1. The Zener diode ZD1 clamps the output voltage LO of the level shift unit 5 to a predetermined value when the MOS transistor N2 switches from off to on.
A Zener diode ZD2 is connected in parallel between the output terminals of the MOS transistor N2 (between the drain terminal and the source terminal). The Zener diode ZD2 clamps the voltage between the drain terminal and the source terminal of the MOS transistor N2 to a predetermined value when the MOS transistor N2 is off.
More specifically, the output voltage of the CMOS inverter 1 is input to the gate of the MOS transistor N2. The cathode of the Zener diode ZD2 is connected to the drain terminal of the MOS transistor N2, and the anode of the Zener diode ZD2 is connected to the source terminal of the MOS transistor N2.

One end of the resistor R2 is connected to the drain terminal of the MOS transistor N2, and the other end of the resistor R2 is connected to one end of the resistor R1. A power supply voltage VDDH (for example, + 48V) is applied to the other end of the resistor R1. A Zener diode ZD1 is connected in parallel across the resistor R1. The voltage at the common connection of the resistors R1 and R2 is output as the output voltage LO of the level shift unit 5.
The CMOS inverter 3 is turned on / off by the output of the level shift unit 5 and outputs an output signal OUT corresponding to the on / off operation. Therefore, the CMOS inverter 3 is composed of complementary MOS transistors P3 and N3, and operates between a power supply voltage of VSSH [V] and VDDH [V] (for example, + 40V and + 48V).

Next, an operation example of the first embodiment having such a configuration will be described with reference to FIGS. 1 and 2.
When the MOS transistor N2 of the level shift unit 5 is switched from off to on, the output voltage LO of the level shift unit 5 can be expressed by the above equation (1). According to the equation (1), the output voltage LO can be arbitrarily set by the value of (I × R1). In other words, the change (rate of change) of the output voltage LO can be arbitrarily set by setting the magnitude (resistance value) of one or both of the resistors R1 and R2 to an arbitrary value.
Therefore, the resistance value of one or both of the resistors R1 and R2 is such that the output voltage LO of the level shift unit 5 changes rapidly when the MOS transistor N2 of the level shift unit 5 is switched from OFF to ON. Was set to. The change in the output voltage LO in this case is, for example, a curve c1 in FIG.

Here, it is assumed that the Zener diode ZD1 is not connected in parallel across the resistor R1. In this case, the output voltage LO changes as shown by a broken line following the curve c1 in FIG.
However, in the first embodiment, the Zener diode ZD1 is connected in parallel to both ends of the resistor R1. Therefore, when the MOS transistor N2 is switched from OFF to ON, the output voltage LO of the level shift unit 5 is clamped to a predetermined value by the Zener diode ZD1 as shown by the curve c2 in FIG. As a result, the voltage applied to the gate terminals of the MOS transistors P3 and N3 of the CMOS inverter 3 to which the output voltage LO of the level shift unit 5 is connected can be clamped to a predetermined value.

For this reason, since the output voltage LO of the level shift unit 5 can be changed within the range of the power supply voltage VDDH and its predetermined value, the MOS transistors P3 and N3 of the CMOS inverter 3 can use low voltage specification transistors.
Although the voltage drop of the output voltage LO of the level shift unit 5 can be reduced by reducing the current flowing through the resistor R1, the potential gradient as shown by the curve b in FIG. 6 results in a slow change in the output voltage LO. Therefore, a desired operation speed cannot be obtained by the level shift operation.
In the first embodiment, the Zener diode ZD2 is connected in parallel between the drain terminal and the source terminal of the MOS transistor N2. Therefore, the Zener diode ZD2 clamps the voltage between the drain terminal and the source terminal of the MOS transistor N2 to a predetermined value when the MOS transistor N2 is off. Therefore, a low voltage specification transistor can be used as the MOS transistor N2 of the level shift unit 5.

As described above, since the first embodiment is configured as described above, VDDH level (for example, 48 V) and VSSH (for example, 48 V) from a low voltage system signal of VDD level (for example, 5 V) and VSS level (for example, 0 V). For example, when the signal level is shifted to a high voltage system signal of 40V), a transistor having a low voltage specification can be used as the transistors constituting the CMOS inverter 1, the level shift unit 5, and the output unit.
Further, according to the first embodiment, when the MOS transistor N2 of the level shift unit 5 is switched from OFF to ON, a change in the output voltage LO of the level shift unit 5 can be arbitrarily set. Further, the level after the change of the output voltage LO of the level shift unit 5 can be set to a predetermined value and can be fixed to the predetermined value. For this reason, according to the first embodiment, the speed of the output change when the MOS transistor N2 is turned on can be easily set.

Furthermore, in the first embodiment, since the Zener diodes ZD1 and DZ2 are provided, the voltage applied to the MOS transistors N2, N3, and P3 falls within the low voltage range, and a low-voltage specification transistor can be used. As a result, it can be realized with a small occupation area in the semiconductor chip. Further, the MOS transistors N2, N3, and P3 can be protected from sudden fluctuations in the power supply, power supply surges, and the like.
In the first embodiment, the resistor R2 is interposed between the MOS transistor N2 and the resistor R1. However, when the desired curves c1 and c2 in FIG. 2 are obtained, the resistor R2 is not necessarily required and can be omitted. In this case, the curve c1 in FIG. 2 is determined by the resistance value of the resistor R1.

(Second Embodiment)
As shown in FIG. 3, the semiconductor device according to the second embodiment of the present invention includes a CMOS inverter 1 as an input unit, a level shift unit 5A, and a CMOS inverter 3 as an output unit.
The second embodiment is based on the configuration of the first embodiment shown in FIG. 1, and the level shift unit 5 in FIG. 1 is replaced with a level shift unit 5A in FIG. Specifically, as shown in FIG. 3, the level shift unit 5A is formed by diode-connecting a MOS transistor P2 to both ends of a resistor R1, and this portion is added.
That is, the gate terminal and the drain terminal of the MOS transistor P2 are connected in common, and this common connection is connected to one end of the resistor R1. The source terminal of the MOS transistor P2 is connected to the other end of the resistor R1.

Since the second embodiment is the same as the configuration of the first embodiment of FIG. 1 except for the additional portions, the same components are denoted by the same reference numerals and the description thereof is omitted.
In the second embodiment having such a configuration, the following operation is performed when the MOS transistor N2 of the level shift unit 5A is switched from on to off.
In this case, the output voltage LO of the level shift unit 5A tends to rise to the level of the power supply voltage VDDH from the potential represented by the equation (1). However, the rise of the resistor R1 and the parasitic capacitance present at the input terminal of the CMOS inverter 3 are delayed.

However, the MOS transistor P2 is diode-connected at both ends of the resistor R1 (the gate terminal and the drain terminal are commonly connected). For this reason, the MOS transistor P2 is in a conductive state, and the charge of the parasitic capacitance existing in the input capacitance of the CMOS inverter 3 and the input signal line to the CMOS inverter 3 is rapidly discharged, so that the output voltage LO is equal to the power supply voltage VDDH. Time to rise to level can be shortened.
Thus, according to the second embodiment, the effect of the first embodiment can be realized in addition to the above effect. In the second embodiment, the resistor R2 can be omitted as in the first embodiment.

1 is a circuit diagram showing a configuration of a first embodiment of a semiconductor device of the present invention. It is a wave form diagram explaining the operation | movement of the 1st Embodiment. It is a circuit diagram which shows the structure of 2nd Embodiment of the semiconductor device of this invention. It is a circuit diagram which shows the structure of the conventional apparatus. It is a circuit diagram which shows the other structure of the conventional apparatus. It is a wave form diagram explaining operation | movement of the conventional apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 3 ... CMOS inverter, 5, 5A ... Level shift part, N2, P2 ... MOS transistor, R1, R2 ... Resistance, ZD1, ZD2 ... Zener diode

Claims (5)

A level shift unit of a level shift circuit that shifts the potential level of an input signal that changes between the first high potential and the first low potential to a signal that changes between the second high potential and the second low potential In a semiconductor device having
The level shift unit includes:
A first transistor that is turned on and off by the input signal;
A first resistor connected in series between the drain terminal of the first transistor and a second high potential;
A first Zener diode having a cathode terminal connected to a drain terminal and an anode terminal connected to a source terminal of the first transistor;
A second Zener diode having a cathode terminal connected to a second high potential and an anode terminal connected to the other end of the first resistor not connected to the second high potential;
A semiconductor device comprising:   The source terminal is connected to the same second high potential as one end of the first resistor, and the gate terminal and the drain terminal are diode-connected to the other end not connected to the second high potential of the first resistor. The semiconductor device according to claim 1, further comprising a second transistor.   The semiconductor device according to claim 1, wherein a second resistor is interposed between the first transistor and the first resistor. The resistance value of the first resistor is set such that the output voltage of the level shift unit arbitrarily changes when the first transistor is switched from off to on,
The first Zener diode is configured to clamp a voltage applied to a drain terminal of the first transistor to a predetermined value when the output voltage changes arbitrarily. Item 4. The semiconductor device according to any one of Items 3.   3. The second transistor is configured to discharge a parasitic capacitance charge at an input terminal at a subsequent stage of the level shift unit when the first transistor is switched from on to off. The semiconductor device according to claim 4.

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