JP2012244215A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique capable of suppressing the generation of a through current in a semiconductor integrated circuit for driving an insulated gate semiconductor element.SOLUTION: The semiconductor integrated circuit includes a delay circuit 19 for outputting a delayed signal that is a delayed control signal Vto gate terminals of a PMOS 1 and an NMOS 2. A timing (t) of on-to-off switching of an NMOS 4 based on a change in a second output signal is not later than a timing (t) of off-to-on switching of the PMOS 1 based on a change in the delayed signal, and a timing (t) of on-to-off switching of a PMOS 3 based on a change in a first output signal is not later than a timing (t) of off-to-on switching of the NMOS 2 based on a change in the delayed signal.

Description

  The present invention relates to a semiconductor integrated circuit that drives an insulated gate semiconductor element based on a control signal.

  2. Description of the Related Art Semiconductor integrated circuits that drive insulated gate semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor field effect transistors) based on control signals are known.

  In this semiconductor integrated circuit, an unnecessary mirror voltage may be generated at the gate terminal at turn-off / turn-on due to the capacitance characteristics between the gate and the emitter of the insulated gate semiconductor element. When the generation time of the mirror voltage is long, there is a problem that the switching frequency cannot be increased.

  Various techniques have been proposed to solve this problem. For example, in Patent Document 1, first and second drive circuits are connected to the gate terminal of an insulated gate semiconductor element, and the voltage at the gate terminal is increased or decreased stepwise by the first and second drive circuits. Thus, a technique for shortening the generation time of the mirror voltage is disclosed.

JP 2000-253646 A

  However, the technique disclosed in Patent Document 1 has a problem in that a through current that is a consumption current is generated in the semiconductor integrated circuit at the timing when the first and second drive circuits are switched on and off. It was.

  Therefore, the present invention has been made in view of the above problems, and provides a technique capable of suppressing the occurrence of a through current in a semiconductor integrated circuit that drives an insulated gate semiconductor element. For the purpose.

  A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit that drives an insulated gate semiconductor device based on a control signal, each of which has a totem pole connection between a high potential and a low potential power source and a sink side The first and second drive circuits each comprising a pair of switching elements are provided. A connection point between the source-side and sink-side switching elements in each of the first and second driving circuits is connected to a gate terminal of the insulated gate semiconductor element. The semiconductor integrated circuit performs a calculation based on a comparator circuit that compares a voltage of a gate terminal of the insulated gate semiconductor element with a reference voltage, the control signal, and a comparison result in the comparator circuit, and A first operation circuit that outputs a first output signal indicating a calculation result to a gate terminal of the source side switching element of the second drive circuit; The semiconductor integrated circuit performs an operation based on the control signal and a comparison result in the comparator circuit, and outputs a second output signal indicating the operation result to the sink-side switching element of the second drive circuit. A second arithmetic circuit that outputs to the gate terminal; and a delay circuit that outputs a delay signal obtained by delaying the control signal to the gate terminals of the source-side and sink-side switching elements of the first drive circuit. . The timing at which the sink-side switching element of the second drive circuit is switched from on to off according to the change in the second output signal is that the source-side switching element of the first drive circuit is the delay signal. The timing at which the switching element on the source side of the second drive circuit is switched from on to off in response to a change in the first output signal is not later than the timing at which the switching is performed from off to on in accordance with the change in Is not later than the timing at which the sink-side switching element of the first drive circuit is switched from OFF to ON according to the change in the delay signal.

  According to the present invention, the timing at which the sink-side switching element of the second drive circuit is turned off is not later than the timing at which the source-side switching element of the first drive circuit is turned on. Therefore, a through current passing through the sink-side switching element and the source-side switching element can be suppressed. In addition, the timing at which the source side switching element of the second drive circuit is turned off is not later than the timing at which the sink side switching element of the first drive circuit is turned off. Therefore, a through current passing through the sink-side switching element and the source-side switching element can be suppressed.

1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment. 3 is a timing chart showing the operation of the semiconductor integrated circuit according to the first embodiment. FIG. 6 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment.

<Embodiment 1>
FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to Embodiment 1 of the present invention. This semiconductor integrated circuit, different voltage levels (HIGH, LOW) based on the control signal V _in to take selectively the insulated gate semiconductor device 31 (here NMOS) is a circuit for driving the.

  As shown in FIG. 1, the semiconductor integrated circuit according to the present embodiment includes first and second drive circuits 11 and 12, an inverter 15, a comparator circuit 16, and a NAND circuit 17 that is a first arithmetic circuit. A NOR circuit 18 as a second arithmetic circuit and a delay circuit 19 are provided.

The first drive circuit 11 is composed of a pair of PMOS1 (source side switching element) and NMOS2 (sink side switching element) connected totem-pole between high potential (V _CC ) and low potential (V _GND ) power supplies. ing. The gate terminals of PMOS 1 and NMOS 2 are connected to each other, the source terminal of PMOS 1 is connected to the power supply voltage V _CC, and the drain terminal of NMOS 2 is connected to the ground voltage V _GND . The drain terminal of the PMOS 1 and the drain terminal of the NMOS 2 are connected to each other, and the connection point between the PMOS 1 and the NMOS 2 is connected to the gate terminal of the insulated gate semiconductor element 31 via the terminal 25. .

The second drive circuit 12 is composed of a pair of a PMOS 3 (source side switching element) and an NMOS 4 (sink side switching element) that are totem-pole connected between a high potential (V _CC ) / low potential (V _GND ) power source. ing. The PMOS 3 and the NMOS 4 are connected in the same manner as the PMOS 1 and the NMOS 2, and the connection point between the PMOS 3 and the NMOS 4 is connected to the gate terminal of the insulated gate semiconductor element 31 through the terminal 25.

  In the following description, it is assumed that the gate terminal voltage of PMOS1 and NMOS2 is “gate voltage VG1”, the gate terminal voltage of PMOS3 is “gate voltage VG3”, and the gate terminal voltage of NMOS4 is “gate voltage VG4”. To do.

Inverter 15, the inverted signal obtained by inverting the control signal V _in, one input terminal of the NAND circuit 17, and is output to one input terminal of the NOR circuit 18.

The comparator circuit 16 compares the voltage VG at the gate terminal of the insulated gate semiconductor element 31 with the reference voltage Vref. The comparator circuit 16 outputs the comparison result to the other input terminal of the NAND circuit 17 and the other input terminal of the NOR circuit 18, respectively. In the present embodiment, the comparator circuit 16 outputs LOW as an output voltage (hereinafter referred to as “voltage V ₁₆ ”) when the gate voltage VG is lower than the reference voltage Vref, and the gate voltage VG is equal to or higher than the reference voltage Vref. In this case, HIGH is output as the voltage V ₁₆ . Here, an operational amplifier circuit is used as an example of the comparator circuit 16, and the same voltage as the threshold voltage Vth of the insulated gate semiconductor element 31 is set as the reference voltage Vref.

Based on the control signal V _in (inverted signal from the inverter 15 here) and the comparison result (voltage V ₁₆ ) in the comparator circuit 16, the NAND circuit 17 performs an operation of negating the logical product of them, A first output signal indicating the calculation result is output to the gate terminal of the PMOS 3 of the second drive circuit 12. That is, the NAND circuit 17 sets the gate voltage VG3 of the PMOS 3 to LOW when the inverted signal and the voltage V ₁₆ are both HIGH, and sets the gate voltage VG3 to HIGH otherwise.

The NOR circuit 18 performs an operation of negating the logical sum of the control signal V _in (here, the inverted signal from the inverter 15) and the comparison result (voltage V ₁₆ ) in the comparator circuit 16, A second output signal indicating the calculation result is output to the gate terminal of the NMOS 4 of the second drive circuit 12. That is, the NOR circuit 18 sets the gate voltage VG4 of the NMOS 4 to HIGH when the inverted signal and the voltage V ₁₆ are both LOW, and sets the gate voltage VG4 to LOW in other cases.

Delay circuit 19, a delay signal obtained by delaying the control signal V _in, and outputs to the gate terminals of PMOS1 and NMOS2 of the first driving circuit 11. In the present embodiment, the delay circuit 19 includes two inverters 19a and 19b connected in series, and is configured relatively simply. Incidentally, the delay circuit 19 is, for how much delay the control signal V _in, set forth in the following description of the operation.

FIG. 2 is a timing chart showing the operation of the semiconductor integrated circuit according to the present embodiment. This figure shows the source / drain voltage Vds between the source terminal and the drain terminal of the insulated gate semiconductor element 31, the drain current Id, and the switching loss Esw _in addition to the control signal Vin and the like described above. . Hereinafter, the operation of the semiconductor integrated circuit will be described with reference to FIG. In before time t _1, the gate voltage VG1, VG3, VG4 is HIGH, V ₁₆ is LOW, PMOS1,3 off shall NMOS2,4 is on.

First, at the time point t _1, the control signal V _in is switched from HIGH to "LOW". Since the change _in the control signal Vin is transmitted to the PMOS 1 and the NMOS 2 via the delay circuit 19 that delays the input signal, the gate voltage VG1 is not switched to LOW. Therefore, the switches of PMOS1 and NMOS2 are not switched. Similarly, since the change _in the control signal Vin is transmitted to the PMOS 3 through the inverter 15 and the NAND circuit 17 that delay the input signal in the same manner as the delay circuit, the gate voltages VG3 and VG4 do not change. Therefore, the switches of PMOS 3 and NMOS 4 are not switched.

After the time point t ₁ , “HIGH” of the inverted signal of the control signal V _in (LOW) and “LOW” of the voltage V ₁₆ are input to the NAND circuit 17 and the NOR circuit 18. Then, NAND circuit 17 is to keep the gate voltage VG3 even at the next time point t ₂ to "HIGH", NOR circuit 18, is switched to "LOW" gate voltage VG4 from HIGH in the next time t ₂ become.

Thereafter, “LOW” of the delay signal of the control signal V _in is input to the gate terminals of the PMOS 1 and the NMOS ₂ at time t ₂ . That is, the gate voltage VG1 is switched from HIGH to “LOW”. Therefore, the PMOS 1 is switched from off to on, and the NMOS 2 is switched from on to off. Further, at the time point t ₂ , the gate voltage VG 3 is maintained at “HIGH” as described above, so that the PMOS 3 is maintained off. On the other hand, since the gate voltage VG4 is switched to “LOW” by the NOR circuit 18 as described above, the NMOS 4 is switched from on to off.

Here, if, unless the delay circuit 19 is provided, the control signal V _in is a from being inputted to the gate terminal of the PMOS1 and NMOS2 without being delayed, the control signal V _in becomes "LOW" Almost simultaneously, the gate voltage VG1 of the PMOS1 and the NMOS2 becomes “LOW”. As a result, the timing when the gate voltage VG1 of the PMOS1 and the NMOS2 becomes “LOW” is earlier than the timing when the gate voltage VG4 of the NMOS4 becomes “LOW”. In this case, there is a time difference between the PMOS1 being turned on and the NMOS4 being turned off, so that both the PMOS1 and the NMOS4 are turned on, although only for a short time. As a result, a through current that becomes a consumption current flows through the PMOS 1 and the NMOS 4 at that time.

In this embodiment contrast, NMOS 4 is a timing switched from ON to OFF in accordance with a change of the second output signal (gate voltage VG4) at time t _1, is PMOS1, delay at the time t ₁ signal timing is switched from oFF to oN in response to changes in (gate voltage VG1), to coincide with each other at time t _2, it is set the delay time of the delay signal. That is, as indicated by the arrow on the left side of FIG. 2, the timing at which the gate voltage VG1 switches to LOW is delayed from the timing at which the gate voltage VG4 switches to LOW (time point t ₂ ). Therefore, it is possible to suppress a through current that becomes a consumption current from flowing through the PMOS 1 and the NMOS 4.

After time t ₂ , PMOS 1 is on and NMOS ₂ and 4 are off, so that the gate voltage VG of the insulated gate semiconductor element 31 increases.

At time t ₃ , when the gate voltage VG becomes equal to or higher than the threshold voltage Vth of the insulated gate semiconductor element 31 (that is, the reference voltage Vref), the comparator circuit 16 changes the voltage V ₁₆ from LOW to “HIGH”. Accordingly, the inverted signal “HIGH” and the voltage V ₁₆ of “HIGH” are input to the NAND circuit 17 and the NOR circuit 18. Then, since the NOR circuit 18 maintains the gate voltage VG4 at “LOW” even at the time point t ₃ , the NMOS 4 is kept off. On the other hand, since the NAND circuit 17 switches the gate voltage V3 from HIGH to “LOW” at the time point t ₃ , the PMOS 3 is switched from OFF to ON.

  As described above, in the present embodiment, the timing at which the PMOS 3 is switched from OFF to ON in accordance with the change in the first output signal (gate voltage VG3) is determined in accordance with the change in the delay signal (gate voltage VG1). Later than the timing of switching from off to on. Thus, until the gate voltage VG of the insulated gate semiconductor element 31 becomes equal to or higher than the threshold voltage Vth, the gate voltage VG is charged (charged) with a weak source capability, and when the gate voltage VG becomes equal to or higher than the threshold voltage Vth, it is strong. The gate voltage VG is charged by the source capability.

As a result, as shown in FIG. 2, the gate voltage VG when the PMOS ₃ is not turned on rises during the mirror period (t _{3 to} t ₄ ) until the gate voltage VG rises when the PMOS 3 is turned on (solid line) ( It can be shorter than the mirror period (t _{3 to} t ₅ ) up to the two-dot chain line). Therefore, since the time (solid line) until the source / drain voltage Vds of the insulated gate semiconductor element 31 completely falls can be shortened compared to the time when the PMOS 3 is not turned on (two-dot chain line), the switching loss is reduced. Esw can be reduced.

Then, at a time t _6, control signal V _in is switched to "HIGH" from LOW. At time t ₆ , the same delay as at time t ₁ occurs, so that the switches of PMOS ₁ and 3 and NMOS 2 and 4 are not switched.

After the time point t ₆ , “LOW” of the inverted signal of the control signal V _in (HIGH) and “HIGH” of the voltage V ₁₆ are input to the NAND circuit 17 and the NOR circuit 18. Then, NOR circuit 18 is to keep the gate voltage VG4 even at the next time point t ₇ to "LOW", NAND circuit 17, to switch to the "HIGH" and gate voltage VG3 from LOW is at the next time point t ₇ become.

Then, at time t _7, "HIGH" in the delay signal of the control signal V _in is input to the gate terminal of PMOS1 and NMOS 2. That is, the gate voltage VG1 is switched from LOW to “HIGH”. Therefore, PMOS1 is switched from on to off, and NMOS2 is switched from off to on. Further, at the time point t ₇ , the gate voltage VG4 is maintained at “LOW” as described above, so that the NMOS 4 is maintained off. On the other hand, since the gate voltage VG3 is switched to “HIGH” by the NAND circuit 17 as described above, the PMOS3 is switched from on to off.

Here, if, unless the delay circuit 19 is provided, the control signal V _in is a from being inputted to the gate terminal of the PMOS1 and NMOS2 without being delayed, the control signal V _in becomes "HIGH" Almost simultaneously, the gate voltage VG1 of the PMOS1 and the NMOS2 becomes “HIGH”. As a result, the timing when the gate voltage VG1 of the PMOS1 and the NMOS2 becomes “HIGH” is earlier than the timing when the gate voltage of the PMOS3 becomes “HIGH”. In this case, there is a time difference between the NMOS 2 being turned on and the PMOS 3 being turned off, so that both the PMOS 3 and the NMOS 2 are turned on for a short time. As a result, a through current that becomes a consumption current flows through the PMOS 3 and the NMOS 2 at that time.

On the other hand, in the present embodiment, the timing at which the PMOS 3 is switched from on to off according to the change in the first output signal (gate voltage VG3) at the time point t ₆ and the NMOS 2 are delayed at the same time point t _6. signal timing is switched from oFF to oN in response to changes in (gate voltage VG1), to coincide with each other at time t _7, it is set the delay time of the delay signal. That is, as indicated by the arrow on the right side of FIG. 2, the timing at which the gate VG1 switches to HIGH is delayed from the timing at which the gate voltage VG3 switches to HIGH (time point t ₇ ). Therefore, it is possible to suppress a through current that becomes a consumption current from flowing through the PMOS 3 and the NMOS 2.

After time t ₇ , the PMOS 1 and 3 are off and the NMOS 2 is on, so the gate voltage VG of the insulated gate semiconductor element 31 decreases.

When the gate voltage VG becomes lower than the threshold voltage Vth (Vref) of the insulated gate semiconductor element 31 at time t ₈ , the comparator circuit 16 changes the voltage V ₁₆ from HIGH to “LOW”. Therefore, the inverted signal “LOW” and the voltage V ₁₆ “LOW” are input to the NAND circuit 17 and the NOR circuit 18. Then, NAND circuit 17, since it maintains the gate voltage VG3 to "HIGH" even at time t _8, PMOS 3 is kept off. On the other hand, since the NOR circuit 18 switches the gate voltage VG4 from LOW to “HIGH” at the time point t ₈ , the NMOS 4 is switched from OFF to ON.

  Thus, in this embodiment, the timing at which the NMOS 4 is switched from OFF to ON in accordance with the change in the second output signal (gate voltage VG4) is that the NMOS 2 is in response to the change in the delay signal (gate voltage VG1). Later than the timing of switching from off to on. Thus, until the gate voltage VG of the insulated gate semiconductor element 31 becomes lower than the threshold voltage Vth, the gate voltage VG is discharged (discharged) with a weak sink capability, and when the gate voltage VG becomes lower than the threshold voltage Vth, it is strong. The gate voltage VG is discharged by the sink capability.

  As a result, as described above, the mirror period until the gate voltage VG falls when the NMOS 4 is turned on can be shortened compared to the mirror period when the NMOS 4 is not turned on. Therefore, the switching loss Esw can be reduced.

  According to the semiconductor integrated circuit according to the present embodiment that performs the operation as described above, the timing at which the NMOS 4 is turned off and the timing at which the PMOS 1 is turned on coincide with each other, and the PMOS 3 is turned on and off. The timing coincides with the timing at which the NMOS 2 is turned on from off. Therefore, it is possible to suppress a through current that becomes a consumption current.

  In addition, if only desiring to suppress the through current is not limited to the above configuration. Specifically, the timing at which the NMOS 4 is switched from on to off according to the change in the second output signal is not later than the timing at which the PMOS 1 is switched from off to on according to the change in the delay signal, and The timing at which the PMOS 3 is switched from on to off in response to a change in the first output signal may be less than the timing at which the NMOS 2 is switched from off to on in accordance with a change in the delay signal. Even in this case, the through current can be suppressed. However, if it is desired to speed up the above series of processing, it is desirable to match each timing as described above.

  Further, according to the semiconductor integrated circuit of the present embodiment, the timing at which the PMOS 3 is switched from OFF to ON is later than the timing at which the PMOS 1 is switched from OFF to ON, and the timing at which the NMOS 4 is switched from OFF to ON is It is later than the timing at which the NMOS 2 is switched from off to on. Therefore, the mirror period can be shortened, and the switching loss Esw can be reduced. In addition, higher switching frequency can be expected. Note that if the driving capability of the second driving circuit 12 (PMOS3 and NMOS4) is increased, the effect of shortening the mirror period can be enhanced.

  In this embodiment, two inverters 19a and 19b connected in series are used as the delay circuit 19. However, any other delay circuit can be used as long as the delay time can be set as shown in FIG. The configuration may be adopted.

  In the present embodiment, the reference voltage Vref of the comparator circuit 16 is the same voltage as the threshold voltage Vth of the insulated gate semiconductor element 31. However, since there are actually manufacturing variations, the threshold voltage Vth (mirror voltage) varies. Therefore, it is preferable to set the reference voltage Vref to the minimum value among the values that the threshold voltage Vth (mirror voltage) is expected to take.

  In the present embodiment, the first arithmetic circuit has been described as the NAND circuit 17, but other arithmetic circuits may be combined as long as the same arithmetic operation is performed. Similarly, although the second arithmetic circuit has been described as the NOR circuit 18 in the present embodiment, other arithmetic circuits may be combined as long as the same arithmetic operation is performed.

<Embodiment 2>
In general, the threshold voltage of a SiC MOSFET is as low as 2 V, for example. Therefore, when a SiC MOSFET is applied to the insulated gate semiconductor element 31, and the voltage of the LOW signal input to the gate terminal of the insulated gate semiconductor element 31 exceeds the threshold voltage due to manufacturing variations, etc. There is a possibility that the desired operation described in the first embodiment cannot be performed. Therefore, in the second embodiment of the present invention, even when a semiconductor element having a low threshold voltage (for example, a SiC MOSFET) is applied to the insulated gate semiconductor element 31, a desired operation can be reliably performed. It is possible.

  FIG. 3 is a circuit diagram showing a configuration of the semiconductor integrated circuit according to the present embodiment. Hereinafter, in the semiconductor integrated circuit according to the present embodiment, components similar to those described in the first embodiment are denoted by the same reference numerals, and different points from the first embodiment will be mainly described.

  As shown in FIG. 3, in the present embodiment, an internal power supply circuit 41 is added to the configuration of the first embodiment. The internal power supply circuit 41 is connected to the source terminal of the insulated gate semiconductor element 31 via the terminal 26, and applies a negative bias VE to the source terminal. In this case, even if the voltage Vx is applied to the source terminal of the insulated gate semiconductor element 31, it is equivalent to the voltage (Vx−VE) being applied to the source terminal due to the nature of the MOSFET. .

  Therefore, for example, when the threshold voltage Vth of the insulated gate semiconductor element 31 is 2V and the negative bias VE is 7V, the threshold voltage of the insulated gate semiconductor element 31 is substantially 9V. In this case, when a LOW signal is input to the gate terminal of the insulated gate semiconductor element 31, even if the voltage is slightly higher than the original threshold voltage 2V (for example, 3V), the LOW signal is It can be treated as a LOW signal.

  As described above, according to the present embodiment, even when a semiconductor element having a low threshold voltage is applied to the insulated gate semiconductor element 31, a desired operation can be reliably performed.

  In the present embodiment as well, since the second drive circuit 12 is provided as in the first embodiment, the gate voltage VG can be discharged with a strong sink capability. Therefore, since the voltage of the LOW signal can be lowered by this action, the negative bias VE of the internal power supply circuit 41 can be set relatively low. Therefore, the lifetime can be extended by that amount, and the effect of increasing the reliability of the semiconductor integrated circuit can be expected.

  DESCRIPTION OF SYMBOLS 1,3 PMOS, 2,4 NMOS, 11 1st drive circuit, 12 2nd drive circuit, 16 comparator circuit, 17 NAND circuit, 18 NOR circuit, 19 delay circuit, 31 Insulated gate type semiconductor element, 41 Internal power supply circuit

Claims (5)

A semiconductor integrated circuit for driving an insulated gate semiconductor element based on a control signal,
Each includes first and second drive circuits each consisting of a pair of switching elements on the source side and sink side that are totem-pole connected between the high-potential and low-potential power supplies,
A connection point between the source-side and sink-side switching elements in each of the first and second drive circuits is connected to a gate terminal of the insulated gate semiconductor element,
A comparator circuit for comparing a voltage of a gate terminal of the insulated gate semiconductor element with a reference voltage;
A calculation is performed based on the control signal and a comparison result in the comparator circuit, and a first output signal indicating the calculation result is output to the gate terminal of the switching element on the source side of the second drive circuit. One arithmetic circuit;
A calculation is performed based on the control signal and a comparison result in the comparator circuit, and a second output signal indicating the calculation result is output to the gate terminal of the sink-side switching element of the second drive circuit. Two arithmetic circuits;
A delay circuit that outputs a delay signal obtained by delaying the control signal to gate terminals of the source side and sink side switching elements of the first drive circuit;
The timing at which the sink-side switching element of the second drive circuit is switched from on to off according to the change in the second output signal is that the source-side switching element of the first drive circuit is the delay signal. Is not later than the timing of switching from off to on according to the change in
The timing at which the switching element on the source side of the second driving circuit is switched from on to off in response to a change in the first output signal is that the switching element on the sink side of the first driving circuit is the delay signal. A semiconductor integrated circuit that is not later than the timing at which it is switched from off to on in response to a change in. The semiconductor integrated circuit according to claim 1,
The timing at which the switching element on the sink side of the second drive circuit is switched from on to off in accordance with the change of the second output signal, and the switching element on the source side of the first drive circuit include the delay signal And the timing of switching from off to on according to the change in the same, and
The timing at which the switching element on the source side of the second driving circuit is switched from on to off according to the change of the first output signal, and the switching element on the sink side of the first driving circuit are configured to transmit the delay signal. A semiconductor integrated circuit in which the timing of switching from off to on in accordance with the change of the same coincides with each other. A semiconductor integrated circuit according to claim 1 or 2, wherein
The timing at which the source-side switching element of the second drive circuit is switched from OFF to ON according to the change in the first output signal is that the source-side switching element of the first drive circuit is the delay signal. Slower than the timing of switching from off to on in response to changes in
The timing at which the sink-side switching element of the second drive circuit is switched from OFF to ON according to a change in the second output signal is that the sink-side switching element of the first drive circuit is the delay signal. A semiconductor integrated circuit that is later than the timing at which it is switched from off to on in response to a change in. A semiconductor integrated circuit according to any one of claims 1 to 3,
A semiconductor integrated circuit further comprising an internal power supply circuit connected to a source terminal of the insulated gate semiconductor element and applying a negative bias to the source terminal. A semiconductor integrated circuit according to any one of claims 1 to 4,
The delay circuit is a semiconductor integrated circuit which is two inverters connected to each other.

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